RAMFOS/sdloader.inc at master · VWarlock/RAMFOS · GitHub

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CLC_PORT        = 0FFE5h
DATA_PORT       = 0FFE6h
CTL_PORT        = 0FFE7h
CLC_BIT         = 80h;
SEND_MODE       = 10010000b ; Íàñòðîéêà: 1 0 0 A ÑH 0 B CL   1=ââîä 0=âûâîä
RECV_MODE       = 10011001b

ERR_START  	= 040h
ERR_WAIT   	= 041h
ERR_OK_DISK 	= 042h
ERR_OK          = 043h
ERR_OK_READ	= 044h
ERR_OK_RKS  	= 047h

;----------------------------------------------------------------------------

Entry:
     ; Ïåðâûì ýòàïîì ïðîèñõîäèò ñèíõðîíèçàöèÿ ñ êîíòðîëëåðîì
     ; Ïðèíèìàåòñÿ 256 ïîïûòîê. Äëÿ ýòîãî â ðåãèñòð C çàíîñèòñÿ 0
     MVI	C, 0

RetrySync:
     ; Ðåæèì ïåðåäà÷è
     MVI	A, SEND_MODE
     STA	CTL_PORT

     ; Ïåðåäàåì íà÷àëî êîìàíäû
     MVI	A, 013h
     CALL	Send
     MVI	A, 0B4h
     CALL	Send
     MVI	A, 057h
     CALL	Send
     XRA	A
     CALL	Send

     ; Ðåæèì ïðèåìà
     MVI	A, RECV_MODE
     STA	CTL_PORT

     ; Åñëè åñòü ñèíõðîíèçàöèÿ, òî êîíòðîëëåð îòâåòèò ERR_START
     CALL	Recv
     CPI	ERR_START
     JZ 	Sync

     ; Ïàóçà / Ïðîïóñêàåì 256 áàéò, åñëè êîíòðîëëåð åùå ÷òî òî ïåðåäàåò.
     ; Â ñóììå áóäåò ïðîïóùåíî 64 Êá äàííûõ
     MVI	B, 0
RetrySync2:
     CALL	Recv
     DCR	B
     JNZ	RetrySync2

     ; Ïîïûòêè
     DCR	C
     JZ 	MONITOR ; Îøèáêà ñèíõðîíèçàöèè

     JMP	RetrySync

;----------------------------------------------------------------------------
; ×òî áû ÌÊ îñâîáîäèë øèíó

Error:
    CALL	Recv
    JMP 	MONITOR

;----------------------------------------------------------------------------

Sync:
     ; Æäåì ïîêà ÌÊ ïðî÷èòàåò ôàéë.
     CALL	WaitForReady
     CPI	ERR_OK_RKS
     JNZ	Error ; Îøèáêà ÷òåíèÿ ôàéëà

     ; Àäðåñ çàãðóçêè â BC
     CALL	Recv
     MOV	C, A
     CALL	Recv
     MOV	B, A

     ; Ñîõðàíÿåì â ñòåê àäðåñ çàïóñêà
     PUSH	B

RecvLoop:
     ; Ïîäîæäàòü
     CALL	WaitForReady
     CPI 	ERR_OK_READ
     JZ 	Recv	; Âñ¸ çàãðóæåíî, çàïóñê
     ORA A	; Îøèáêà, ïåðåçàãðóçêà
     JNZ 	Error	; Îøèáêà ÷òåíèÿ ôàéëà

     ; Äëèíà î÷åðåäíîãî áëîêà
     CALL	Recv
     MOV	E, A
     CALL	Recv
     MOV	D, A

     ; Èñïîëüçóåòñÿ íèæå
     LXI	H, CLC_PORT

     ; Ïðèíÿòü î÷åðåäíîé áëîê
     INR	D
     XRA	A
     ORA	E
     JZ 	RecvBlock2
RecvBlock1:
     MVI	M, CLC_BIT    ; 11
     MVI	M, 0          ; 11
     LDA	DATA_PORT     ; 13
     STAX	B             ; 7
     INX	B             ; 5
     DCR	E             ; 5
     JNZ	RecvBlock1    ; 10
RecvBlock2:
     DCR	D
     JNZ	RecvBlock1

     JMP	RecvLoop

;----------------------------------------------------------------------------
; Îòïðàâêà è ïðèåì áàéòà

Send:
     STA	DATA_PORT
Recv:
     MVI	A, CLC_BIT
     STA	CLC_PORT
     XRA	A
     STA	CLC_PORT
     LDA	DATA_PORT
     RET

;----------------------------------------------------------------------------
; Îæèäàíèå ãîòîâíîñòè ÌÊ

WaitForReady:
     CALL       Recv
     CPI	ERR_WAIT
     JZ		WaitForReady
     RET

;----------------------------------------------------------------------------

MONITOR: