From bdcfe1d3657a41af902a652a8988d8f19b07fa69 Mon Sep 17 00:00:00 2001 From: Jip Galema Date: Fri, 28 Nov 2025 14:36:26 +0100 Subject: [PATCH 1/4] [SEM-703] Turn on driver, overwrite GPU configuration in GPU --- configs/sx8m_defconfig | 3 +- dts/ultimainboard5-lvds.dtsi | 76 ++++++++++++++++++++++++++++-------- 2 files changed, 61 insertions(+), 18 deletions(-) diff --git a/configs/sx8m_defconfig b/configs/sx8m_defconfig index 70b0254..60e0c05 100644 --- a/configs/sx8m_defconfig +++ b/configs/sx8m_defconfig @@ -654,7 +654,7 @@ CONFIG_DRM_IMX_DCNANO=y CONFIG_DRM_IMX95_DPU=y CONFIG_DRM_IMX_DCSS=y CONFIG_DRM_IMX_CDNS_MHDP=y -CONFIG_DRM_ETNAVIV=m +CONFIG_DRM_ETNAVIV=y CONFIG_DRM_HISI_HIBMC=m CONFIG_DRM_HISI_KIRIN=m CONFIG_DRM_MXSFB=y @@ -972,7 +972,6 @@ CONFIG_TEE=y CONFIG_OPTEE=y CONFIG_MUX_MMIO=y CONFIG_MXC_SIM=y -CONFIG_MXC_GPU_VIV=y CONFIG_MXC_EMVSIM=y CONFIG_MXC_VIDEO_WAVE6=y CONFIG_EXT2_FS=y diff --git a/dts/ultimainboard5-lvds.dtsi b/dts/ultimainboard5-lvds.dtsi index a556748..f9a84e1 100644 --- a/dts/ultimainboard5-lvds.dtsi +++ b/dts/ultimainboard5-lvds.dtsi @@ -27,13 +27,57 @@ }; +/* 1. Disable the downstream NXP monolithic GPU node */ +&gpu { + status = "disabled"; +}; + +/* 2. Define the separate 3D and 2D cores expected by Etnaviv */ +&soc { + gpu_3d: gpu@38000000 { + compatible = "vivante,gc"; + reg = <0x38000000 0x8000>; + interrupts = ; + /* Map clocks: Core, Shader, Bus (AXI), Reg (AHB) */ + clocks = <&clk IMX8MM_CLK_GPU3D_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, /* Shader clock often dummy on MM */ + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB>; + clock-names = "core", "shader", "bus", "reg"; + power-domains = <&pgc_gpu>; + status = "okay"; + }; + + gpu_2d: gpu@38008000 { + compatible = "vivante,gc"; + reg = <0x38008000 0x8000>; + interrupts = ; + /* Map clocks: Core, Bus (AXI), Reg (AHB) */ + clocks = <&clk IMX8MM_CLK_GPU2D_ROOT>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB>; + clock-names = "core", "bus", "reg"; + power-domains = <&pgc_gpu>; + status = "okay"; + }; +}; + +/* 3. Group them in the generic GPU subsystem */ +/ { + gpu-subsystem { + compatible = "fsl,imx-gpu-subsystem"; + cores = <&gpu_3d &gpu_2d>; + status = "okay"; + }; +}; + /* Remove pins used in Ultiboard 5 from generic GPIOs pinctrl settings of imx8mm. */ &pinctrl_gpio1 { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x140 /* GPIO0 / CSI0 PWR */ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x140 /* TEST# */ MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* GPIO12 */ - MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* GPIO13 */ + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* GPIO13 */ >; }; @@ -55,9 +99,9 @@ }; /* SEM-503: We need to connect the IMX8MM pad UART3_RXD and UART3_TXD to the GPIO5 controller, - removing them from the UART1 controller. So we need to re-define these pin control groups + removing them from the UART1 controller. So we need to re-define these pin control groups here, since it is not possible to delete a pin from a fsl,pin array */ - + &pinctrl_gpio5 { fsl,pins = < MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x140 /* GPIO5 / PWMOUT */ @@ -80,7 +124,7 @@ >; }; - + /* Add GPIOs pinctrl for Ultboard 5. */ /* GPIO PAD setting */ @@ -98,10 +142,10 @@ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x100 /* GPIO3 / CSI1 RST / Led-0 Kernel Heartbeat */ >; }; - + pinctrl_i2c3_tca6416: i2c3_tca6416 { fsl,pins = < - MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x080 /* GPIO8 / U35 - TCA6416 INT */ + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x080 /* GPIO8 / U35 - TCA6416 INT */ >; }; }; @@ -128,7 +172,7 @@ Connecting the USB2514B to the I2C bus and increasing the POWER-ON TIME to 110 ms resolves the issue. In this configuration, we set it to 200 ms to be on the safe side. */ - + usb2514b@2c { compatible = "microchip,usb2514b"; reg = <0x2c>; @@ -138,7 +182,7 @@ individual-port-switching; power-on-time-ms = <200>; }; - + tca6416@20 { compatible = "ti,tca6416"; reg = <0x20>; @@ -148,12 +192,12 @@ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; gpio-controller; #gpio-cells = <2>; - gpio-line-names = "VCC5_EXT_EN", "VCC5_EXT_OK", "VCC5_FAN_EN", "VCC5_FAN_OK", - "HDMI_PWR_EN", "HDMI_PWR_OK", "VCC5_PH_EN", "VCC5_PH_OK", - "VCC24_HP_PG", "VCC24_MOT_PG", "LVDS_PWR_EN", "LVDS_PWR_OK", + gpio-line-names = "VCC5_EXT_EN", "VCC5_EXT_OK", "VCC5_FAN_EN", "VCC5_FAN_OK", + "HDMI_PWR_EN", "HDMI_PWR_OK", "VCC5_PH_EN", "VCC5_PH_OK", + "VCC24_HP_PG", "VCC24_MOT_PG", "LVDS_PWR_EN", "LVDS_PWR_OK", "SAFETY_BTN_STATUS", "SAFETY_RESET", "VCC24_PH_EN", "VCC24_MOT_EN"; }; - + cabin_light: pca9632@61 { compatible = "nxp,pca9632"; #address-cells = <1>; @@ -217,9 +261,9 @@ /* Set pin names for IMXRT control lines */ &gpio4 { - gpio-line-names = "TCA6416A_nINT", "USB2514B_Reset", "", "", "", "", "", "RESET_OUT", - "", "", "", "", "", "", "", "", - "", "", "", "", "IMXRT_nReset", "", "", "", + gpio-line-names = "TCA6416A_nINT", "USB2514B_Reset", "", "", "", "", "", "RESET_OUT", + "", "", "", "", "", "", "", "", + "", "", "", "", "IMXRT_nReset", "", "", "", "", "", "", "", "IMXRT_BootMode_En", "SAFETY_ENABLED", "", ""; }; @@ -228,7 +272,7 @@ /* SEM-503: The IMX8MM UART3_RXD pad (SMARC P138) is connected to the UMBus Drive Enable pin. It should be connected to VCC5 in HW, but up to now (2025-01-22) the current ultimainboard 5 still has it connected to wired to the SoM, without any specific reason / purpose. So here we claim this pin as gpio-hog and set it to high level and then it cannot be changed in runtime */ - + umbus_drive_enable_hog { gpio-hog; gpios = <26 GPIO_ACTIVE_HIGH>; From 370fe470ab9ad96a738bfcab34b95279dc80e8d2 Mon Sep 17 00:00:00 2001 From: Jip Galema Date: Mon, 1 Dec 2025 11:09:04 +0100 Subject: [PATCH 2/4] [SEM-703] Use single GPU core instead of 2. --- dts/ultimainboard5-lvds.dtsi | 57 +++++++++++++++--------------------- 1 file changed, 24 insertions(+), 33 deletions(-) diff --git a/dts/ultimainboard5-lvds.dtsi b/dts/ultimainboard5-lvds.dtsi index f9a84e1..5a0378a 100644 --- a/dts/ultimainboard5-lvds.dtsi +++ b/dts/ultimainboard5-lvds.dtsi @@ -27,50 +27,41 @@ }; -/* 1. Disable the downstream NXP monolithic GPU node */ +/* Overwriting the existing NXP gpu node to be a valid Single-Core Etnaviv node */ &gpu { - status = "disabled"; -}; + /* 1. Change binding to upstream Etnaviv */ + compatible = "vivante,gc"; -/* 2. Define the separate 3D and 2D cores expected by Etnaviv */ -&soc { - gpu_3d: gpu@38000000 { - compatible = "vivante,gc"; - reg = <0x38000000 0x8000>; - interrupts = ; - /* Map clocks: Core, Shader, Bus (AXI), Reg (AHB) */ - clocks = <&clk IMX8MM_CLK_GPU3D_ROOT>, - <&clk IMX8MM_CLK_DUMMY>, /* Shader clock often dummy on MM */ - <&clk IMX8MM_CLK_GPU_BUS_ROOT>, - <&clk IMX8MM_CLK_GPU_AHB>; - clock-names = "core", "shader", "bus", "reg"; - power-domains = <&pgc_gpu>; - status = "okay"; - }; + /* 2. FIX: Limit to ONE register range (The 3D Core only) */ + /* Original NXP node had 4 ranges here, causing confusion */ + reg = <0x0 0x38000000 0x0 0x8000>; - gpu_2d: gpu@38008000 { - compatible = "vivante,gc"; - reg = <0x38008000 0x8000>; - interrupts = ; - /* Map clocks: Core, Bus (AXI), Reg (AHB) */ - clocks = <&clk IMX8MM_CLK_GPU2D_ROOT>, - <&clk IMX8MM_CLK_GPU_BUS_ROOT>, - <&clk IMX8MM_CLK_GPU_AHB>; - clock-names = "core", "bus", "reg"; - power-domains = <&pgc_gpu>; - status = "okay"; - }; + /* 3. FIX: Limit to ONE interrupt (The 3D Core IRQ) */ + interrupts = ; + + /* 4. FIX: Rename clocks to match Etnaviv expectations */ + /* Etnaviv looks for "core", "shader", "bus", "reg" */ + clocks = <&clk IMX8MM_CLK_GPU3D_ROOT>, /* core */ + <&clk IMX8MM_CLK_GPU3D_ROOT>, /* shader */ + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, /* bus */ + <&clk IMX8MM_CLK_GPU_AHB>; /* reg */ + + clock-names = "core", "shader", "bus", "reg"; + + /* 5. Ensure power domain is active */ + power-domains = <&pgc_gpu>; + + status = "okay"; }; -/* 3. Group them in the generic GPU subsystem */ +/* Define the subsystem with just this single node */ / { gpu-subsystem { compatible = "fsl,imx-gpu-subsystem"; - cores = <&gpu_3d &gpu_2d>; + cores = <&gpu>; status = "okay"; }; }; - /* Remove pins used in Ultiboard 5 from generic GPIOs pinctrl settings of imx8mm. */ &pinctrl_gpio1 { fsl,pins = < From a49fec18ed13c7bd604eff9b84e01cc8654c2fda Mon Sep 17 00:00:00 2001 From: Jip Galema Date: Tue, 2 Dec 2025 12:29:20 +0100 Subject: [PATCH 3/4] Fixup! Use single GPU core instead of 2 --- dts/ultimainboard5-lvds.dtsi | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/dts/ultimainboard5-lvds.dtsi b/dts/ultimainboard5-lvds.dtsi index 5a0378a..d6d3bf9 100644 --- a/dts/ultimainboard5-lvds.dtsi +++ b/dts/ultimainboard5-lvds.dtsi @@ -27,19 +27,19 @@ }; -/* Overwriting the existing NXP gpu node to be a valid Single-Core Etnaviv node */ +/* SEM-703: Overwriting the existing NXP gpu node to use the GCNanoUltra GPU + The IMX8 mini were using has two GPU's one for 3D rendering and one for 2D blitting. + For our application only 3D rendering is needed. When enabling both the 2D and 3D core, + were running into memory crashes which seem related to the amount of memory used by both + chips. + */ &gpu { - /* 1. Change binding to upstream Etnaviv */ compatible = "vivante,gc"; - - /* 2. FIX: Limit to ONE register range (The 3D Core only) */ - /* Original NXP node had 4 ranges here, causing confusion */ reg = <0x0 0x38000000 0x0 0x8000>; - /* 3. FIX: Limit to ONE interrupt (The 3D Core IRQ) */ + /* Limit to ONE interrupt (The 3D Core IRQ) */ interrupts = ; - /* 4. FIX: Rename clocks to match Etnaviv expectations */ /* Etnaviv looks for "core", "shader", "bus", "reg" */ clocks = <&clk IMX8MM_CLK_GPU3D_ROOT>, /* core */ <&clk IMX8MM_CLK_GPU3D_ROOT>, /* shader */ @@ -48,9 +48,7 @@ clock-names = "core", "shader", "bus", "reg"; - /* 5. Ensure power domain is active */ power-domains = <&pgc_gpu>; - status = "okay"; }; From 38e0db0825a21ede31125e2491510629d0688ccd Mon Sep 17 00:00:00 2001 From: Sergio Soto Date: Thu, 4 Dec 2025 11:13:36 +0100 Subject: [PATCH 4/4] fixup! Fixup! Use single GPU core instead of 2 --- dts/ultimainboard5-lvds.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/dts/ultimainboard5-lvds.dtsi b/dts/ultimainboard5-lvds.dtsi index d6d3bf9..c3258b4 100644 --- a/dts/ultimainboard5-lvds.dtsi +++ b/dts/ultimainboard5-lvds.dtsi @@ -28,9 +28,9 @@ /* SEM-703: Overwriting the existing NXP gpu node to use the GCNanoUltra GPU - The IMX8 mini were using has two GPU's one for 3D rendering and one for 2D blitting. + The IMX8 mini we're using has two GPU's one for 3D rendering and one for 2D blitting. For our application only 3D rendering is needed. When enabling both the 2D and 3D core, - were running into memory crashes which seem related to the amount of memory used by both + we're running into memory crashes which seem related to the amount of memory used by both chips. */ &gpu { @@ -313,4 +313,3 @@ status = "disabled"; }; }; -