From 3ba0c3fc7a644f257443cbd401367bdece7536db Mon Sep 17 00:00:00 2001 From: Miche Date: Thu, 12 Mar 2026 00:27:29 -0400 Subject: [PATCH 1/5] reset and aes multi tests --- test/results_comp_queue.xml | 8 ++ test/test_comp_queue.py | 173 +++++++++++++++++++++++++++++++++--- 2 files changed, 170 insertions(+), 11 deletions(-) create mode 100644 test/results_comp_queue.xml diff --git a/test/results_comp_queue.xml b/test/results_comp_queue.xml new file mode 100644 index 0000000..dbf7d1d --- /dev/null +++ b/test/results_comp_queue.xml @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/test/test_comp_queue.py b/test/test_comp_queue.py index 856a486..0726a84 100644 --- a/test/test_comp_queue.py +++ b/test/test_comp_queue.py @@ -1,16 +1,167 @@ import cocotb +import random from cocotb.clock import Clock -from cocotb.triggers import RisingEdge, ClockCycles +from cocotb.triggers import RisingEdge, ClockCycles, ReadOnly -async def reset(dut): - dut.rst_n.value = 0 - dut.valid_in_aes.value = 0 - dut.valid_in_sha.value = 0 - dut.dest_addr_aes.value = 0 - dut.dest_addr_sha.value = 0 - dut.ready_in.value = 0 - await ClockCycles(dut.clk, 5) - dut.rst_n.value = 1 - await ClockCycles(dut.clk, 2) +class CompQueueDriver: + + def __init__(self, dut): + self.dut = dut + + async def reset(self): + self.dut.rst_n.value = 0 + self.dut.valid_in_aes.value = 0 + self.dut.valid_in_sha.value = 0 + self.dut.dest_addr_aes.value = 0 + self.dut.dest_addr_sha.value = 0 + self.dut.ready_in.value = 0 + await ClockCycles(self.dut.clk, 5) + self.dut.rst_n.value = 1 + await ClockCycles(self.dut.clk, 2) + + async def send_aes(self, addr): + while self.dut.ready_out_aes.value == 0: + await RisingEdge(self.dut.clk) + self.dut.dest_addr_aes.value = addr + self.dut.valid_in_aes.value = 1 + + await RisingEdge(self.dut.clk) + + self.dut.valid_in_aes.value = 0 + self.dut.dest_addr_aes.value = 0 + + async def send_sha(self, addr): + while self.dut.ready_out_sha.value == 0: + await RisingEdge(self.dut.clk) + + self.dut.dest_addr_sha.value = addr + self.dut.valid_in_sha.value = 1 + + await RisingEdge(self.dut.clk) + + self.dut.valid_in_sha.value = 0 + self.dut.dest_addr_sha.value = 0 + + async def dequeue(self): + while self.dut.valid_out.value == 0: + await RisingEdge(self.dut.clk) + + self.dut.ready_in.value = 1 + + await RisingEdge(self.dut.clk) + + self.dut.ready_in.value = 0 + + + +class CompQueueMonitor: + + def __init__(self, dut): + self.dut = dut + self.transactions = [] + self.samples = [] + self._running = False + self._task = None + + async def start(self): + if self._running: + return + self._running = True + self._task = cocotb.start_soon(self._run()) + + async def stop(self): + if not self._running: + return + self._running = False + if self._task is not None: + await self._task + self._task = None + + def clear(self): + self.transactions.clear() + + async def _run(self): + while self._running: + await RisingEdge(self.dut.clk) + await ReadOnly() + + sample = { + "time": int(cocotb.utils.get_sim_time(units="ns")), + "ready_out_aes": int(self.dut.ready_out_aes.value), + "ready_out_sha": int(self.dut.ready_out_sha.value), + "valid_out": int(self.dut.valid_out.value), + "data_out": int(self.dut.data_out.value), + } + + self.samples.append(sample); + + + if int(self.dut.valid_out.value) == 1 and int(self.dut.ready_in.value) == 1: + + self.transactions.append(sample.copy()) + + +@cocotb.test() +async def test_reset(dut): + + dut._log.info( "==================== RESET TEST ====================") + driver = CompQueueDriver(dut) + monitor = CompQueueMonitor(dut) + + await monitor.start() + await driver.reset() + + await ClockCycles(dut.clk, 1) + + await monitor.stop() + + actual = monitor.samples[-1] if monitor.samples else None + expected = { + "ready_out_aes": 1, + "ready_out_sha": 1, + "valid_out": 0, + "data_out": 0 + } + + assert actual is not None, "No samples captured during reset" + assert actual["ready_out_aes"] == expected["ready_out_aes"], f"ready_out_aes mismatch: expected {expected['ready_out_aes']}, got {actual['ready_out_aes']}" + assert actual["ready_out_sha"] == expected["ready_out_sha"], f"ready_out_sha mismatch: expected {expected['ready_out_sha']}, got {actual['ready_out_sha']}" + assert actual["valid_out"] == expected["valid_out"], f"valid_out mismatch: expected {expected['valid_out']}, got {actual['valid_out']}" + assert actual["data_out"] == expected["data_out"], f"data_out mismatch: expected {expected['data_out']}, got {actual['data_out']}" + + +@cocotb.test() +async def test_aes_multi(dut): + dut._log.info( "==================== AES MULTI TEST ====================") + driver = CompQueueDriver(dut) + monitor = CompQueueMonitor(dut) + + expected_transactions = [] + + await monitor.start() + await driver.reset() + + for _ in range(5): + addr = random.randint(0, 10000) + expected_transactions.append({"data_out": addr}) + await driver.send_aes(addr) + + for _ in range(5): + await driver.dequeue() + await ClockCycles(dut.clk, 1) + + await ClockCycles(dut.clk, 10) + await monitor.stop() + + actual_transactions = monitor.transactions + + # print("Actual transactions:") + # for t in actual_transactions: + # print(t) + + # assert len(actual_transactions) == len(expected_transactions), f"Expected {len(expected_transactions)} transactions, got {len(actual_transactions)}" + + for i, (actual, expected) in enumerate(zip(actual_transactions, expected_transactions)): + assert actual["data_out"] == expected["data_out"], f"Transaction {i} data_out mismatch: expected {expected['data_out']}, got {actual['data_out']}" \ No newline at end of file From c664dd62c97adfac077a6d9b7249c44f97174e1e Mon Sep 17 00:00:00 2001 From: Miche Date: Sun, 15 Mar 2026 13:36:17 -0400 Subject: [PATCH 2/5] more comp queue tests --- test/test_comp_queue.py | 273 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 269 insertions(+), 4 deletions(-) diff --git a/test/test_comp_queue.py b/test/test_comp_queue.py index 0726a84..f4569dc 100644 --- a/test/test_comp_queue.py +++ b/test/test_comp_queue.py @@ -43,7 +43,24 @@ async def send_sha(self, addr): self.dut.valid_in_sha.value = 0 self.dut.dest_addr_sha.value = 0 - + + async def send_both(self, addr_aes, addr_sha): + while self.dut.ready_out_aes.value == 0 or self.dut.ready_out_sha.value == 0: + await RisingEdge(self.dut.clk) + + self.dut.dest_addr_aes.value = addr_aes + self.dut.valid_in_aes.value = 1 + self.dut.dest_addr_sha.value = addr_sha + self.dut.valid_in_sha.value = 1 + + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + self.dut.valid_in_aes.value = 0 + self.dut.dest_addr_aes.value = 0 + self.dut.valid_in_sha.value = 0 + self.dut.dest_addr_sha.value = 0 + async def dequeue(self): while self.dut.valid_out.value == 0: await RisingEdge(self.dut.clk) @@ -53,8 +70,7 @@ async def dequeue(self): await RisingEdge(self.dut.clk) self.dut.ready_in.value = 0 - - + class CompQueueMonitor: @@ -164,4 +180,253 @@ async def test_aes_multi(dut): # assert len(actual_transactions) == len(expected_transactions), f"Expected {len(expected_transactions)} transactions, got {len(actual_transactions)}" for i, (actual, expected) in enumerate(zip(actual_transactions, expected_transactions)): - assert actual["data_out"] == expected["data_out"], f"Transaction {i} data_out mismatch: expected {expected['data_out']}, got {actual['data_out']}" \ No newline at end of file + assert actual["data_out"] == expected["data_out"], f"Transaction {i} data_out mismatch: expected {expected['data_out']}, got {actual['data_out']}" + + +@cocotb.test() +async def test_sha_multi(dut): + dut._log.info( "==================== AES MULTI TEST ====================") + driver = CompQueueDriver(dut) + monitor = CompQueueMonitor(dut) + + expected_transactions = [] + + await monitor.start() + await driver.reset() + + for _ in range(5): + addr = random.randint(0, 10000) + expected_transactions.append({"data_out": addr}) + await driver.send_sha(addr) + + for _ in range(5): + await driver.dequeue() + await ClockCycles(dut.clk, 1) + + await ClockCycles(dut.clk, 10) + await monitor.stop() + + actual_transactions = monitor.transactions + + for i, (actual, expected) in enumerate(zip(actual_transactions, expected_transactions)): + assert actual["data_out"] == expected["data_out"], f"Transaction {i} data_out mismatch: expected {expected['data_out']}, got {actual['data_out']}" + + +@cocotb.test() +async def test_round_robin(dut): + dut._log.info( "==================== ROUND ROBIN TEST ====================") + driver = CompQueueDriver(dut) + monitor = CompQueueMonitor(dut) + + expected_transactions = [] + + await monitor.start() + await driver.reset() + + addr_aes = [0xAAAA, 0xBBBB, 0xCCCC, 0xDDDD, 0xEEEE] + addr_sha = [0x1111, 0x2222, 0x3333, 0x4444, 0x5555] + + for i in range(5): + await driver.send_aes(addr_aes[i]) + + for i in range(5): + await driver.send_sha(addr_sha[i]) + + for i in range(5): + aes = addr_aes[i] + sha = addr_sha[i] + expected_transactions.append({"data_out": aes}) + expected_transactions.append({"data_out": sha}) + + for _ in range(10): + await driver.dequeue() + await ClockCycles(dut.clk, 1) + + await ClockCycles(dut.clk, 10) + await monitor.stop() + + actual_transactions = monitor.transactions + + print("Actual transactions:") + for t in actual_transactions: + print(t) + + for i, (actual, expected) in enumerate(zip(actual_transactions, expected_transactions)): + assert actual["data_out"] == expected["data_out"], f"Transaction {i} data_out mismatch: expected {expected['data_out']}, got {actual['data_out']}" + +@cocotb.test() +async def test_enqueue_round_robin(dut): + dut._log.info( "==================== BOTH ROUND ROBIN TEST ====================") + driver = CompQueueDriver(dut) + monitor = CompQueueMonitor(dut) + + expected_transactions = [] + + await monitor.start() + await driver.reset() + + aes = [0xAAAA, 0xBBBB, 0xCCCC, 0xDDDD, 0xEEEE] + sha = [0x1111, 0x2222, 0x3333, 0x4444, 0x5555] + + for i in range(5): + addr_aes = aes[i] + addr_sha = sha[i] + expected_transactions.append({"data_out": addr_aes}) + expected_transactions.append({"data_out": addr_sha}) + await driver.send_both(addr_aes, addr_sha) + + for _ in range(10): + await driver.dequeue() + await ClockCycles(dut.clk, 1) + + await ClockCycles(dut.clk, 10) + await monitor.stop() + + actual_transactions = monitor.transactions + + for i, (actual, expected) in enumerate(zip(actual_transactions, expected_transactions)): + assert actual["data_out"] == expected["data_out"], f"Transaction {i} data_out mismatch: expected {expected['data_out']}, got {actual['data_out']}" + + +@cocotb.test() +async def test_enqueue_full(dut): + dut._log.info( "==================== ENQUEUE FULL TEST ====================") + driver = CompQueueDriver(dut) + monitor = CompQueueMonitor(dut) + + await driver.reset() + await monitor.start() + + queueDepth = 32 + expected = [] + + for i in range(queueDepth): + aes_addr = random.randint(0, 10000) + expected.append({"data_out": aes_addr}) + await driver.send_aes(aes_addr) + + driver.send_aes(0xDEAD) + driver.send_aes(0xBEEF) + + await ClockCycles(dut.clk, 1) + + assert int(dut.ready_out_aes.value) == 0, f"ready_out_aes should be 0 after {queueDepth} enqueues, got {int(dut.ready_out_aes.value)}" + assert int(dut.ready_out_sha.value) == 0, f"ready_out_sha should be 0 after {queueDepth} enqueues, got {int(dut.ready_out_sha.value)}" + + for i in range(queueDepth): + await driver.dequeue() + await ClockCycles(dut.clk, 1) + assert int(dut.ready_out_aes.value) == 1, f"ready_out_aes should be 1 during dequeue of transaction {i}, got {int(dut.ready_out_aes.value)}" + assert int(dut.ready_out_sha.value) == 1, f"ready_out_sha should be 1 during dequeue of transaction {i}, got {int(dut.ready_out_sha.value)}" + + actual = monitor.transactions + + for i, (actual, expected) in enumerate(zip(actual, expected)): + assert actual["data_out"] == expected["data_out"], f"Transaction {i} data_out mismatch: expected {expected['data_out']}, got {actual['data_out']}" + + +@cocotb.test() +async def test_not_ready_dequeue(dut): + dut._log.info( "==================== NOT READY DEQUEUE TEST ====================") + driver = CompQueueDriver(dut) + monitor = CompQueueMonitor(dut) + + await driver.reset() + await monitor.start() + + dut.ready_in.value = 0 + + headAddr = random.randint(0, 10000) + + await driver.send_aes(headAddr) + + for _ in range(5): + await driver.send_aes(random.randint(0, 10000)) + + await ClockCycles(dut.clk, 1) + + assert int(dut.valid_out.value) == 1, f"valid_out should be 1 after enqueue, got {int(dut.valid_out.value)}" + + for _ in range(5): #check that data is not being dequeued + await ClockCycles(dut.clk, 1) + assert int(dut.data_out.value) == headAddr, f"data_out should be {headAddr}, got {int(dut.data_out.value)}" + + dut.ready_in.value = 1 + + await driver.dequeue() + + assert int(dut.data_out.value) != headAddr, f"data_out should have changed after dequeue, got {int(dut.data_out.value)}" + + +@cocotb.test() +async def test_concurrent_enqueue_dequeue(dut): + dut._log.info( "==================== CONCURRENT ENQUEUE DEQUEUE TEST ====================") + driver = CompQueueDriver(dut) + monitor = CompQueueMonitor(dut) + + await driver.reset() + await monitor.start() + + expected = [] + + addr1 = random.randint(0, 10000) + addr2 = random.randint(0, 10000) + expected.append({"data_out": addr1}) + + while dut.ready_out_aes.value == 0: + await RisingEdge(dut.clk) + + dut.dest_addr_aes.value = addr1 + dut.valid_in_aes.value = 1 + + await RisingEdge(dut.clk) + + dut.dest_addr_aes.value = addr2 + dut.valid_in_aes.value = 1 + + await driver.dequeue() + + await monitor.stop() + + acutal = monitor.transactions + + assert acutal[0]["data_out"] == expected[0]["data_out"], f"Transaction 0 data_out mismatch: expected {expected[0]['data_out']}, got {acutal[0]['data_out']}" + + +@cocotb.test() +async def test_large_quantity(dut): + dut._log.info( "==================== LARGE QUANTITY TEST ====================") + driver = CompQueueDriver(dut) + monitor = CompQueueMonitor(dut) + + await driver.reset() + await monitor.start() + + queueDepth = 32 + expected = [] + + for i in range(queueDepth): + # aes_addr = random.randint(0, 10000) + aes_addr = i + await driver.send_aes(aes_addr) + + for i in range(queueDepth): + await driver.dequeue() + await ClockCycles(dut.clk, 1) + + for i in range(5): + # addr = random.randint(0, 10000) + addr = i + expected.append({"data_out": addr}) + await driver.send_aes(addr) + + for _ in range(5): + await driver.dequeue() + await ClockCycles(dut.clk, 1) + + actual = monitor.transactions[-5:] + + for i in range(len(expected)): + assert actual[i]["data_out"] == expected[i]["data_out"], f"Transaction {i} data_out mismatch: expected {expected[i]['data_out']}, got {actual[i]['data_out']}" + + \ No newline at end of file From a8d07e99d81830772f8ae843d3f30c64a27bc19f Mon Sep 17 00:00:00 2001 From: Miche Date: Wed, 18 Mar 2026 13:27:40 -0400 Subject: [PATCH 3/5] remove incorrect rr test, add comments --- test/test_comp_queue.py | 61 ++++++++--------------------------------- 1 file changed, 12 insertions(+), 49 deletions(-) diff --git a/test/test_comp_queue.py b/test/test_comp_queue.py index f4569dc..e093a06 100644 --- a/test/test_comp_queue.py +++ b/test/test_comp_queue.py @@ -119,9 +119,9 @@ async def _run(self): self.transactions.append(sample.copy()) +# Test reset @cocotb.test() async def test_reset(dut): - dut._log.info( "==================== RESET TEST ====================") driver = CompQueueDriver(dut) monitor = CompQueueMonitor(dut) @@ -148,6 +148,7 @@ async def test_reset(dut): assert actual["data_out"] == expected["data_out"], f"data_out mismatch: expected {expected['data_out']}, got {actual['data_out']}" +# Test multiple AES transactions to ensure they are processed in order and correctly @cocotb.test() async def test_aes_multi(dut): dut._log.info( "==================== AES MULTI TEST ====================") @@ -173,19 +174,15 @@ async def test_aes_multi(dut): actual_transactions = monitor.transactions - # print("Actual transactions:") - # for t in actual_transactions: - # print(t) - - # assert len(actual_transactions) == len(expected_transactions), f"Expected {len(expected_transactions)} transactions, got {len(actual_transactions)}" - for i, (actual, expected) in enumerate(zip(actual_transactions, expected_transactions)): assert actual["data_out"] == expected["data_out"], f"Transaction {i} data_out mismatch: expected {expected['data_out']}, got {actual['data_out']}" + +# Test multiple SHA transactions to ensure they are processed in order and correctly @cocotb.test() async def test_sha_multi(dut): - dut._log.info( "==================== AES MULTI TEST ====================") + dut._log.info( "==================== SHA MULTI TEST ====================") driver = CompQueueDriver(dut) monitor = CompQueueMonitor(dut) @@ -212,48 +209,8 @@ async def test_sha_multi(dut): assert actual["data_out"] == expected["data_out"], f"Transaction {i} data_out mismatch: expected {expected['data_out']}, got {actual['data_out']}" -@cocotb.test() -async def test_round_robin(dut): - dut._log.info( "==================== ROUND ROBIN TEST ====================") - driver = CompQueueDriver(dut) - monitor = CompQueueMonitor(dut) - - expected_transactions = [] - - await monitor.start() - await driver.reset() - - addr_aes = [0xAAAA, 0xBBBB, 0xCCCC, 0xDDDD, 0xEEEE] - addr_sha = [0x1111, 0x2222, 0x3333, 0x4444, 0x5555] - - for i in range(5): - await driver.send_aes(addr_aes[i]) - - for i in range(5): - await driver.send_sha(addr_sha[i]) - - for i in range(5): - aes = addr_aes[i] - sha = addr_sha[i] - expected_transactions.append({"data_out": aes}) - expected_transactions.append({"data_out": sha}) - - for _ in range(10): - await driver.dequeue() - await ClockCycles(dut.clk, 1) - - await ClockCycles(dut.clk, 10) - await monitor.stop() - - actual_transactions = monitor.transactions - - print("Actual transactions:") - for t in actual_transactions: - print(t) - - for i, (actual, expected) in enumerate(zip(actual_transactions, expected_transactions)): - assert actual["data_out"] == expected["data_out"], f"Transaction {i} data_out mismatch: expected {expected['data_out']}, got {actual['data_out']}" +# Test that AES and SHA transactions are enqueued in a round-robin manner when both are sent concurrently @cocotb.test() async def test_enqueue_round_robin(dut): dut._log.info( "==================== BOTH ROUND ROBIN TEST ====================") @@ -288,6 +245,7 @@ async def test_enqueue_round_robin(dut): assert actual["data_out"] == expected["data_out"], f"Transaction {i} data_out mismatch: expected {expected['data_out']}, got {actual['data_out']}" +# Test that the queue correctly indicates when it is full and does not accept new transactions until space is available @cocotb.test() async def test_enqueue_full(dut): dut._log.info( "==================== ENQUEUE FULL TEST ====================") @@ -325,6 +283,7 @@ async def test_enqueue_full(dut): assert actual["data_out"] == expected["data_out"], f"Transaction {i} data_out mismatch: expected {expected['data_out']}, got {actual['data_out']}" +# Test that when ready_in is low, the queue does not dequeue and data_out remains stable until ready_in goes high @cocotb.test() async def test_not_ready_dequeue(dut): dut._log.info( "==================== NOT READY DEQUEUE TEST ====================") @@ -358,6 +317,7 @@ async def test_not_ready_dequeue(dut): assert int(dut.data_out.value) != headAddr, f"data_out should have changed after dequeue, got {int(dut.data_out.value)}" +# Test that the queue can handle concurrent enqueue and dequeue operations @cocotb.test() async def test_concurrent_enqueue_dequeue(dut): dut._log.info( "==================== CONCURRENT ENQUEUE DEQUEUE TEST ====================") @@ -393,8 +353,11 @@ async def test_concurrent_enqueue_dequeue(dut): assert acutal[0]["data_out"] == expected[0]["data_out"], f"Transaction 0 data_out mismatch: expected {expected[0]['data_out']}, got {acutal[0]['data_out']}" + +# Test wrap around of queue pointers @cocotb.test() async def test_large_quantity(dut): + dut._log.info( "==================== LARGE QUANTITY TEST ====================") driver = CompQueueDriver(dut) monitor = CompQueueMonitor(dut) From bde7ea551ab4bc31f593834070610e6aaa2bd8fc Mon Sep 17 00:00:00 2001 From: Miche Date: Wed, 18 Mar 2026 13:33:01 -0400 Subject: [PATCH 4/5] remove results xml --- test/results_comp_queue.xml | 8 -------- 1 file changed, 8 deletions(-) delete mode 100644 test/results_comp_queue.xml diff --git a/test/results_comp_queue.xml b/test/results_comp_queue.xml deleted file mode 100644 index dbf7d1d..0000000 --- a/test/results_comp_queue.xml +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - \ No newline at end of file From d94335b85e6036f9cbf6bfd126ae6ac25d8ee275 Mon Sep 17 00:00:00 2001 From: Miche Date: Thu, 2 Apr 2026 00:46:04 -0400 Subject: [PATCH 5/5] update comp queue valid out to be driven in sync with data_out --- src/comp_queue.v | 6 ++--- test/test_comp_queue.py | 49 +++++------------------------------------ 2 files changed, 8 insertions(+), 47 deletions(-) diff --git a/src/comp_queue.v b/src/comp_queue.v index fbef25e..12e1d27 100644 --- a/src/comp_queue.v +++ b/src/comp_queue.v @@ -86,10 +86,10 @@ module comp_queue #( data_out <= mem[head]; head <= (head + 1) % QDEPTH; count <= count - 1; + valid_out <= 1; + end else begin + valid_out <= 0; end - - // Update valid_out - valid_out <= !empty; end end diff --git a/test/test_comp_queue.py b/test/test_comp_queue.py index e093a06..ca64323 100644 --- a/test/test_comp_queue.py +++ b/test/test_comp_queue.py @@ -62,9 +62,6 @@ async def send_both(self, addr_aes, addr_sha): self.dut.dest_addr_sha.value = 0 async def dequeue(self): - while self.dut.valid_out.value == 0: - await RisingEdge(self.dut.clk) - self.dut.ready_in.value = 1 await RisingEdge(self.dut.clk) @@ -263,13 +260,9 @@ async def test_enqueue_full(dut): expected.append({"data_out": aes_addr}) await driver.send_aes(aes_addr) - driver.send_aes(0xDEAD) - driver.send_aes(0xBEEF) - await ClockCycles(dut.clk, 1) assert int(dut.ready_out_aes.value) == 0, f"ready_out_aes should be 0 after {queueDepth} enqueues, got {int(dut.ready_out_aes.value)}" - assert int(dut.ready_out_sha.value) == 0, f"ready_out_sha should be 0 after {queueDepth} enqueues, got {int(dut.ready_out_sha.value)}" for i in range(queueDepth): await driver.dequeue() @@ -283,40 +276,6 @@ async def test_enqueue_full(dut): assert actual["data_out"] == expected["data_out"], f"Transaction {i} data_out mismatch: expected {expected['data_out']}, got {actual['data_out']}" -# Test that when ready_in is low, the queue does not dequeue and data_out remains stable until ready_in goes high -@cocotb.test() -async def test_not_ready_dequeue(dut): - dut._log.info( "==================== NOT READY DEQUEUE TEST ====================") - driver = CompQueueDriver(dut) - monitor = CompQueueMonitor(dut) - - await driver.reset() - await monitor.start() - - dut.ready_in.value = 0 - - headAddr = random.randint(0, 10000) - - await driver.send_aes(headAddr) - - for _ in range(5): - await driver.send_aes(random.randint(0, 10000)) - - await ClockCycles(dut.clk, 1) - - assert int(dut.valid_out.value) == 1, f"valid_out should be 1 after enqueue, got {int(dut.valid_out.value)}" - - for _ in range(5): #check that data is not being dequeued - await ClockCycles(dut.clk, 1) - assert int(dut.data_out.value) == headAddr, f"data_out should be {headAddr}, got {int(dut.data_out.value)}" - - dut.ready_in.value = 1 - - await driver.dequeue() - - assert int(dut.data_out.value) != headAddr, f"data_out should have changed after dequeue, got {int(dut.data_out.value)}" - - # Test that the queue can handle concurrent enqueue and dequeue operations @cocotb.test() async def test_concurrent_enqueue_dequeue(dut): @@ -350,7 +309,8 @@ async def test_concurrent_enqueue_dequeue(dut): acutal = monitor.transactions - assert acutal[0]["data_out"] == expected[0]["data_out"], f"Transaction 0 data_out mismatch: expected {expected[0]['data_out']}, got {acutal[0]['data_out']}" + for i, (actual, expected) in enumerate(zip(acutal, expected)): + assert acutal["data_out"] == expected["data_out"], f"Transaction 0 data_out mismatch: expected {expected[0]['data_out']}, got {acutal[0]['data_out']}" @@ -389,7 +349,8 @@ async def test_large_quantity(dut): actual = monitor.transactions[-5:] - for i in range(len(expected)): - assert actual[i]["data_out"] == expected[i]["data_out"], f"Transaction {i} data_out mismatch: expected {expected[i]['data_out']}, got {actual[i]['data_out']}" + + for i, (actual, expected) in enumerate(zip(actual, expected)): + assert actual["data_out"] == expected["data_out"], f"Transaction {i} data_out mismatch: expected {expected['data_out']}, got {actual['data_out']}" \ No newline at end of file