[Module] SHA_Top

[smzalam]

Module Name

sha_top

Summary

Full pipeline: padder → blk_fifo → sha+controller → digest_fifo.

Port Interface

module sha256_top(
  input  wire         clk,
  input  wire         rst_n,

  // Message stream in (one message per in_last pulse)
  input  wire         in_valid,
  output wire         in_ready,
  input  wire [7:0]   in_data,
  input  wire         in_last,

  // Digest out (one per message)
  output wire         out_valid,
  input  wire         out_ready,
  output wire [255:0] out_digest
);

Functional Requirements

• Connect padder → (optional small FIFO) → sha256_controller.
• For the first block of a message, re-init core to IV.
• Produce one out_digest per message after last block completes.
• Handle backpressure on both input and output gracefully.

Handshake & Timing Notes (for everyone)

• Valid/Ready: all streaming interfaces use standard ready/valid.
• Schedule↔Round coupling: assert shift one cycle before you consume the next W_t.
• K/W alignment: K[t] and W[t] must feed the same round index.
• State adders: all additions are mod 2³²; use 32-bit wrap.
• Reset: synchronous rst_n recommended; clear counters/valids.

Test Plan

No response

Assignee (GitHub username)

No response

Acceptance Criteria

• Verilog module added to src/
• Testbench added to test/
• Module passes simulation
• info.yaml updated with source_files
• Documentation updated in docs/info.md