[Module] SHA_Controller

[smzalam]

Module Name

sha_controller

Summary

Coordinate schedule + round over 64 rounds, maintain/interleave the chaining state H[0..7], and produce the digest for each message block.

Port Interface

module sha_controller(
  input  wire         clk,
  input  wire         rst_n,

  // Block input (pre-padded 512b)
  input  wire         blk_valid,
  output wire         blk_ready,
  input  wire [511:0] blk_data,
  input  wire         start_new_msg,  // reinit H to IV at message start

  // Digest output (asserted after last block processed)
  output reg          digest_valid,
  input  wire         digest_ready,
  output reg  [255:0] digest,

  // Status
  output reg          busy
);

Functional Requirements

• Process one pre-padded 512-bit block at a time.
• On start: load IV into (a..h) and H[0..7] (for first block) or use supplied H (if extended later).
• Orchestrate 64 rounds with a t counter 0..63.
• For t≥15, assert shift to the message schedule so W_{t+1} is ready next cycle.
• After round 63, compute H[i] = H[i] + state_i (mod 2^32); output {H0..H7} as digest.
• Provide busy while hashing; pulse done when digest valid.

Test Plan

No response

Assignee (GitHub username)

No response

Acceptance Criteria

• Verilog module added to src/
• Testbench added to test/
• Module passes simulation
• info.yaml updated with source_files
• Documentation updated in docs/info.md