[Module] AESHash (Top-Level)

[smzalam]

Module Name

aes_hash

Summary

This is the main controller that connects all the other modules. It manages data flow, decides when to load input or keys, sequences the rounds, and outputs the final ciphertext. You can think of it as the conductor of an orchestra: every module performs its part, but the top-level design keeps them all in sync. It’s also the module that Tiny Tapeout will actually run on-chip — everything else feeds into it.

Port Interface

input  wire        clk,
input  wire        rst_n,
input  wire        start,
input  wire [7:0]  din,
input  wire        din_valid,
input  wire        din_is_key,    // 1=key byte, 0=plaintext byte
output wire [7:0]  dout,
output wire        dout_valid,
output wire        done

Functional Requirements

Wire loaders, round datapath, key schedule, and control. Provide byte-stream in/out interface and done when ciphertext (or hash stage) is ready.

Test Plan

• NIST AES Known Answer Tests (256): load key then plaintext, expect ciphertext.
• Back-to-back blocks; verify no cross-block contamination.
• Reset during operation; ensure clean restart.

Assignee (GitHub username)

No response

Acceptance Criteria

• Verilog module added to src/
• Testbench added to test/
• Module passes simulation
• info.yaml updated with source_files
• Documentation updated in docs/info.md