Why is RISC-V simulator memory set-up as Big Endian?

[asrberger]

Looking at memory screen while running a RISC-V program in assembly language, we noticed that the words in memory were stored in Big Endian format. Why Big Endian is allowed in the RISC-V world, most implementations follow Little Endian. For example, our FPGA implementation that we use for teaching Computer Architecture is implemented as Little Endian.

I think it would make sense to either:

1- Make RARS configurable to Big or Little Endian with a set-up option,
2- Come out with a Little Endian version.

Arnie
University of Washington