A 4bit Binary Counter with Parallel Load including a clock divider, a BCD decoder and a 7 segment display.
This is a VHDL project for DSD-I1* a Cyclone IV FPGA made in Quartus 18.1 and is based in the example of pjbal.
Diagram:
Behavioral VHDL code: nbit_syncCount_parLoad.vhd
Testbench VHDL code: nbit_syncCount_parLoad_tb.vhd
Modelsim:
FPGA:
*Note: DSD-i1: A Mixed Functionality Development Board Geared Towards Digital Systems Design Education DOI:10.1109/DSD.2019.00032
Copyright (c) 2019 Stavros Kalapothas (aka Stevaras) stavros@ubinet.gr. It is free software, and may be redistributed under the terms of the GNU Licence.