From 6a799539a015cf459e10bd7569256028721ad6eb Mon Sep 17 00:00:00 2001 From: CatalpaEel <139088727+CatalpaEel@users.noreply.github.com> Date: Mon, 9 Feb 2026 17:16:30 +0800 Subject: [PATCH 1/3] Fix zh_CN translation of pipeline --- .../SpinalHDL/Libraries/Pipeline/index.po | 12 +- .../Libraries/Pipeline/introduction.po | 307 +++++++----------- 2 files changed, 111 insertions(+), 208 deletions(-) diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/index.po index 512cbe3da89..6d48a6ee63c 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/index.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/index.po @@ -6,20 +6,12 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL\n" -"Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2024-01-22 03:53+0000\n" -"PO-Revision-Date: 2024-01-23 07:01+0000\n" -"Last-Translator: Readon \n" -"Language-Team: Chinese (Simplified) \n" "Language: zh_CN\n" +"Plural-Forms: nplurals=1; plural=0;\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=UTF-8\n" "Content-Transfer-Encoding: 8bit\n" -"Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Weblate 5.4-dev\n" -"Generated-By: Babel 2.14.0\n" #: ../../SpinalHDL/Libraries/Pipeline/index.rst:3 msgid "Pipeline" -msgstr "Pipeline" +msgstr "流水线" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/introduction.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/introduction.po index 03449213a35..056d2eac85d 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/introduction.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Pipeline/introduction.po @@ -6,38 +6,30 @@ msgid "" msgstr "" "Project-Id-Version: SpinalHDL\n" -"Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2025-11-24 11:23+0000\n" -"PO-Revision-Date: 2024-12-23 10:57+0800\n" -"Last-Translator: Readon \n" "Language: zh_CN\n" -"Language-Team: Chinese (Simplified) \n" "Plural-Forms: nplurals=1; plural=0;\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=utf-8\n" "Content-Transfer-Encoding: 8bit\n" -"Generated-By: Babel 2.17.0\n" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:3 msgid "Introduction" msgstr "简介" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:5 -#, fuzzy msgid "" "``spinal.lib.misc.pipeline`` provides a pipelining API. The main " "advantages over manual pipelining are :" -msgstr "spinal.lib.misc.pipeline提供了一套流水线API。相对于手动流水线它的主要优点是：" +msgstr "``spinal.lib.misc.pipeline`` 提供了一套流水线API。相对于手动流水线它的主要优点是：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:7 -#, fuzzy msgid "" "You don't have to predefine all the signal elements needed for the entire" " staged system upfront. You can create and consume stageable signals in a" " more ad hoc fashion as your design requires - without needing to " "refactor all the intervening stages to know about the signal" -msgstr "您不必预先准备好整个流水系统中所需的所有信号元素。您可以根据设计需要，以更特别的方式创建和使用可分级的信号，而无需重构所有中间阶段来处理信号" +msgstr "无需预先一次性定义好整个流水系统中所需的所有信号元素。" +"您可以根据设计需要，以更灵活的方式创建和使用可分级的信号，而无需重构所有中间阶段来适配该信号。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:8 msgid "" @@ -52,7 +44,7 @@ msgstr "流水线的信号可以利用SpinalHDL的强大参数化能力，并且 msgid "" "Manual retiming is much easier, as you don't have to handle the registers" " / arbitration manually" -msgstr "手动时序调整要容易得多，因为您不需要手动处理寄存器/仲裁器" +msgstr "手动重定时要容易得多，因为您不需要手动处理寄存器与仲裁逻辑。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:10 msgid "Manage the arbitration by itself" @@ -63,38 +55,34 @@ msgid "The API is composed of 4 main things :" msgstr "API由4个主要部分组成：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:14 -#, fuzzy msgid "``Node`` : which represents a layer in the pipeline" -msgstr "Node：表示管道中的层" +msgstr "``Node`` （节点）：表示管道中的层" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:15 -#, fuzzy msgid "``Link`` : which allows to connect nodes to each other" -msgstr "Link：允许节点相互连接" +msgstr "``Link`` （链接）：允许节点相互连接" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:16 -#, fuzzy msgid "" "``Builder`` : which will generate the hardware required for a whole " "pipeline" -msgstr "Builder：生成整个管道所需的硬件" +msgstr "``Builder`` （构建器）：生成整个管道所需的硬件" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:17 -#, fuzzy msgid "" "``Payload`` : which are used to retrieve hardware signals on nodes along " "the pipeline" -msgstr "Payload：用于获取流水线的节点上的硬件信号" +msgstr "``Payload`` （负载）：用于获取流水线的节点上的硬件信号" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:19 -#, fuzzy msgid "" "It is important to understand that ``Payload`` isn't a hardware " "data/signal instance, but a key to retrieve a data/signal on nodes along " "the pipeline, and that the pipeline builder will then automatically " "interconnect/pipeline every occurrence of a given ``Payload`` between " "nodes." -msgstr "重要的是，Payload不是硬件数据/信号实例，而是用于检索流水线在节点中数据/信号的关键，并且流水线构建器随后将在节点之间的每次给定Payload出现时自动互连/流水线。" +msgstr "需要注意的是，``Payload`` 不是硬件数据/信号实例，而是在流水线各节点检索数据/信号的键。" +"流水线构建器会据此自动完成所有节点间同一 ``Payload`` 实例的互连 / 流水线化处理。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:23 msgid "Here is an example to illustrate :" @@ -133,33 +121,31 @@ msgid "Payload" msgstr "Payload" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:153 -#, fuzzy msgid "" "``Payload`` objects are used to refer to data which can go through the " "pipeline. Technically speaking, ``Payload`` is a ``HardType`` which has a" " name and is used as a \"key\" to retrieve the signals in a certain " "pipeline stage." -msgstr "Payload对象用于引用可以通过流水线的数据。从技术上讲，Payload是一个HardType，它有一个名字，并被用作在流水线某个级中检索信号的“键”。" +msgstr "``Payload`` 对象指向可以通过流水线传输的数据。从技术上讲，``Payload`` 是一个具备名称属性的 ``HardType`` " +"它被用作在流水线特定阶段中检索信号的“键”。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:168 -#, fuzzy msgid "" "Note that I got used to name the ``Payload`` instances using uppercase. " "This is to make it very explicit that the thing isn't a hardware signal, " "but are more like a \"key/type\" to access things." -msgstr "请注意，我习惯于使用大写对Payload实例命名。这是为了让它非常明确，这不是一个硬件信号，更像是一个“键/类型”访问的东西。" +msgstr "请注意，我习惯于使用大写对 ``Payload`` 实例命名。这是为了明确，这不是一个硬件信号，而更像是一个“键/类型”的访问标识。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:172 msgid "Node" msgstr "Node" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:174 -#, fuzzy msgid "" "``Node`` mostly hosts the valid/ready arbitration signals, and the " "hardware signals required for all the ``Payload`` values going through " "it." -msgstr "Node主要托管有效/就绪仲裁信号，以及所有通过它的硬件信号所需的Payload。" +msgstr "``Node`` 主要托管有效/就绪仲裁信号，以及所有流经该节点的 ``Payload`` 所需的硬件信号。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:177 msgid "You can access its arbitration via :" @@ -187,9 +173,8 @@ msgid "Description" msgstr "描述" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:187 -#, fuzzy msgid "``node.valid``" -msgstr "node.valid" +msgstr "``node.valid``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:188 #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:191 @@ -198,45 +183,41 @@ msgid "RW" msgstr "RW" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:189 -#, fuzzy msgid "" "Is the signal which specifies if a transaction is present on the node. It" " is driven by the upstream. Once asserted, it must only be de-asserted " "the cycle after which either both ``valid`` and ``ready`` or " "``node.cancel`` are high. ``valid`` must not depend on ``ready``." -msgstr "指定节点上是否存在事务的信号。它是由上游逻辑驱动的。一旦置为1，则它必须且仅能在valid和ready同时置位或node.cancel为高的周期后解除置位。valid不依赖于ready。" +msgstr "指定节点上是否存在事务，由上游逻辑驱动。一旦置为1，" +"仅可在以下两种情况发生后的下一个时钟周期撤销置位： ``valid`` 和 ``ready`` 同时为1；或 ``node.cancel`` 为1。" +" ``valid`` 不得依赖于 ``ready``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:190 -#, fuzzy msgid "``node.ready``" -msgstr "node.ready" +msgstr "``node.ready``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:192 -#, fuzzy msgid "" "Is the signal which specifies if the node's transaction can proceed " "downstream. It is driven by the downstream to create backpressure. The " "signal has no meaning when there is no transaction (``node.valid`` being " "deasserted)." -msgstr "表示节点中的事务是否可以向下游传递的信号。它由下游驱动以创建反压。当没有事务（node.valid被置0）时，该信号无意义" +msgstr "表示节点中的事务是否可以向下游传递，由下游驱动以创建反压。当没有事务（ ``node.valid`` 被置0）时，该信号无意义" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:193 -#, fuzzy msgid "``node.cancel``" -msgstr "node.cancel" +msgstr "``node.cancel``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:195 -#, fuzzy msgid "" "Is the signal which specifies if the node's transaction in being canceled" " from the pipeline. It is driven by the downstream. The signal has no " "meaning when there is no transaction (``node.valid`` being deasserted)" -msgstr "指定节点的事务是否正在从流水线中取消的信号。它由下游驱动。当没有事务时（node.valid被置0），该信号没有意义" +msgstr "指定节点的事务是否正在从流水线中取消，由下游驱动。当没有事务时（ ``node.valid`` 被置0），该信号没有意义" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:196 -#, fuzzy msgid "``node.isValid``" -msgstr "node.isValid" +msgstr "``node.isValid``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:197 #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:200 @@ -248,80 +229,68 @@ msgid "RO" msgstr "RO" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:198 -#, fuzzy msgid "``node.valid``'s read only accessor" -msgstr "node.valid的只读访问器" +msgstr "``node.valid`` 的只读访问器" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:199 -#, fuzzy msgid "``node.isReady``" -msgstr "node.isReady" +msgstr "``node.isReady``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:201 -#, fuzzy msgid "``node.ready``'s read only accessor" -msgstr "node.ready的只读访问器" +msgstr "``node.ready`` 的只读访问器" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:202 -#, fuzzy msgid "``node.isCancel``" -msgstr "node.isCancel" +msgstr "``node.isCancel``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:204 -#, fuzzy msgid "``node.cancel``'s read only accessor" -msgstr "node.cancel的只读访问器" +msgstr "``node.cancel`` 的只读访问器" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:205 -#, fuzzy msgid "``node.isFiring``" -msgstr "node.isFiring" +msgstr "``node.isFiring``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:207 -#, fuzzy msgid "" "``True`` when the node transaction is successfully moving further " "(``valid && ready && !cancel``). Useful to commit state changes." -msgstr "当节点事务成功继续传递时为True（valid && ready && !cancel）。提交状态更改时非常有用。" +msgstr "当节点事务成功继续传递时为 ``True`` （ ``valid && ready && !cancel`` ）。这在提交状态更改时非常有用。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:208 -#, fuzzy msgid "``node.isMoving``" -msgstr "node.isMoving" +msgstr "``node.isMoving``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:210 -#, fuzzy msgid "" "``True`` when the node transaction will not be present anymore on the " "node (starting from the next cycle), either because downstream is ready " "to take the transaction, or because the transaction is canceled from the " "pipeline (``valid && (ready || cancel)``). Useful to \"reset\" states." msgstr "" -"当节点事务将不再存在于节点上时（从下一周期开始）为True，要么是因为下游准备好接收事务，要么是因为事务已从流水线中取消。（valid && " -"(ready || cancel)）用于“复位”(reset)状态。" +"当节点事务将不再存在于节点上时（从下一周期开始）为 ``True`` ，要么是因为下游准备好接收事务，要么是因为事务已从流水线中取消" +"（ ``valid && (ready || cancel)`` ）。这可以用于“复位”状态。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:213 -#, fuzzy msgid "``node.isCanceling``" -msgstr "node.isCanceling" +msgstr "``node.isCanceling``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:215 -#, fuzzy msgid "" "True when the node transaction is being cleaned up. Meaning that it will " "not appear anywhere in the pipeline in future cycles. It is equivalent to" " ``isValid && isCancel``." -msgstr "当节点事务正在被取消时为True。这意味着在将来的周期中它不会出现在流水线中的任何地方。" +msgstr "当节点事务正在被取消时为 ``True`` 。这意味着在将来的周期中它不会出现在流水线中的任何地方。" +"这等价于 ``isValid && isCancel`` 。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:217 -#, fuzzy msgid "" "Note that the ``node.valid``/``node.ready`` signals follows the same " "conventions than the :doc:`../stream`'s ones ." -msgstr "请注意，node.valid/node.ready信号遵循与 :doc:`../stream` 中相同的规范。" +msgstr "请注意， ``node.valid``/``node.ready`` 信号遵循与 :doc:`../stream` 中相同的规范。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:220 -#, fuzzy msgid "" "The ``Node`` controls (``valid``/``ready``/``cancel``) and status " "(``isValid``, ``isReady``, ``isCancel``, ``isFiring``, ...) signals are " @@ -329,15 +298,17 @@ msgid "" "backpressure by never referring to the ready signal. That's why it is " "important to use status signals when you want to read the status of " "something and only use control signals when you want to drive something." -msgstr "Node的控制信号（valid/ready/cancel）和状态信号（isValid、isReady、isCancel、isFiring等）是按需创建的。因此，当您想要读取某事物的状态时，使用状态信号很重要，只有当您想要驱动某事物时才使用控制信号。" +msgstr "``Node`` 的控制信号（ ``valid``/``ready``/``cancel`` ）和状态信号" +"（ ``isValid`` 、 ``isReady`` 、 ``isCancel`` 、 ``isFiring`` 等）是按需创建的。" +"例如，若从不引用 ``ready`` 信号，即可创建无反压的流水线。" +"这也是为何读取状态时应使用状态信号，而驱动操作时仅使用控制信号，这一点至关重要。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:226 -#, fuzzy msgid "" "Here is a list of arbitration cases you can have on a node. " "``valid``/``ready``/``cancel`` define the state we are in, while " "``isFiring``/``isMoving`` result of those :" -msgstr "以下是节点上可能出现的仲裁情况列表。valid/ready/cancel定义了我们所处的状态，而isFiring/isMoving是这些状态的结果：" +msgstr "以下是节点上可能出现的仲裁情况列表。``valid``/``ready``/``cancel`` 定义了我们所处的状态，而 ``isFiring``/``isMoving`` 是这些状态的结果：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:230 msgid "valid" @@ -405,18 +376,16 @@ msgid "You can access signals referenced by a Payload via:" msgstr "您可以通过以下方式访问由Payload引用的信号：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:252 -#, fuzzy msgid "``node(Payload)``" -msgstr "node(Payload)" +msgstr "``node(Payload)``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:253 msgid "Return the corresponding hardware signal" msgstr "返回对应的硬件信号" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:254 -#, fuzzy msgid "``node(Payload, Any)``" -msgstr "node(Payload, Any)" +msgstr "``node(Payload, Any)``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:255 msgid "" @@ -427,9 +396,8 @@ msgid "" msgstr "与上述相同，但包括一个用作“次要键”的第二个参数。这有助于构建多通道硬件。例如，当您有一个多发射CPU流水线时，您可以使用通道Int id作为次要键" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:256 -#, fuzzy msgid "``node.insert(Data)``" -msgstr "node.insert(Data)" +msgstr "``node.insert(Data)``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:257 msgid "" @@ -445,104 +413,87 @@ msgid "" msgstr "您不仅可以手动方式来驱动/读取流水线的第一/最后一级的仲裁信号/数据，也有一些实用工具可以连接这些边界上的级。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:282 -#, fuzzy msgid "``node.arbitrateFrom(Stream[T]])``" -msgstr "node.arbitrateFrom(Stream[T]])" +msgstr "``node.arbitrateFrom(Stream[T]])``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:283 -#, fuzzy msgid "Drive a node arbitration from a ``Stream``." msgstr "由反压流驱动节点仲裁。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:284 -#, fuzzy msgid "``node.arbitrateFrom(Flow[T]])``" -msgstr "node.arbitrateFrom(Flow[T]])" +msgstr "``node.arbitrateFrom(Flow[T]])``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:285 -#, fuzzy msgid "Drive a node arbitration from a ``Flow``." msgstr "由数据流驱动节点仲裁。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:286 -#, fuzzy msgid "``node.arbitrateTo(Stream[T]])``" -msgstr "node.arbitrateTo(Stream[T]])" +msgstr "``node.arbitrateTo(Stream[T]])``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:287 -#, fuzzy msgid "Drive a ``Stream`` arbitration from the node." msgstr "由节点驱动反压流仲裁。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:288 -#, fuzzy msgid "``node.arbitrateTo(Flow[T]])``" -msgstr "node.arbitrateTo(Flow[T]])" +msgstr "``node.arbitrateTo(Flow[T]])``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:289 -#, fuzzy msgid "Drive a ``Flow`` arbitration from the node." msgstr "由节点驱动数据流仲裁。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:290 -#, fuzzy msgid "``node.driveFrom(Stream[T]])((Node, T) => Unit)``" -msgstr "node.driveFrom(Stream[T]])((Node, T) => Unit)" +msgstr "``node.driveFrom(Stream[T]])((Node, T) => Unit)``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:291 -#, fuzzy msgid "" "Drive a node from a stream. The provided lambda function can be use to " "connect the data." msgstr "由反压流驱动节点。提供的lambda函数可以用于连接数据" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:292 -#, fuzzy msgid "``node.driveFrom(Flow[T]])((Node, T) => Unit)``" -msgstr "node.driveFrom(Flow[T]])((Node, T) => Unit)" +msgstr "``node.driveFrom(Flow[T]])((Node, T) => Unit)``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:293 #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:297 -#, fuzzy msgid "Same as above but for ``Flow``." -msgstr "与上述类似，但适用于Flow" +msgstr "与上述类似，但适用于 ``Flow`` 。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:294 -#, fuzzy msgid "``node.driveTo(Stream[T]])((T, Node) => Unit)``" -msgstr "node.driveTo(Stream[T]])((T, Node) => Unit)" +msgstr "``node.driveTo(Stream[T]])((T, Node) => Unit)``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:295 -#, fuzzy msgid "" "Drive a stream from the node. The provided lambda function can be use to " "connect the data." msgstr "由节点驱动反压流。提供的lambda函数可以用于连接数据" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:296 -#, fuzzy msgid "``node.driveTo(Flow[T]])((T, Node) => Unit)``" -msgstr "node.driveTo(Flow[T]])((T, Node) => Unit)" +msgstr "``node.driveTo(Flow[T]])((T, Node) => Unit)``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:317 -#, fuzzy msgid "" "In order to reduce verbosity, there is a set of implicit conversions " "between ``Payload`` toward their data representation which can be used " "when you are in the context of a ``Node`` :" -msgstr "为了减少冗长，在Payload与其数据表示之间有一组隐式转换，可在Node下使用：" +msgstr "为了减少冗长，在 ``Payload`` 与其数据表示之间有一组隐式转换，可在 ``Node`` 下使用：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:328 msgid "You can also use those implicit conversions by importing them :" msgstr "您还可以通过导入它们来使用这些隐式转换：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:341 -#, fuzzy msgid "" "There is also an API which allows you to create new ``Area`` which " "provide the whole API of a given node instance (including implicit " "conversion) without import :" -msgstr "还有一个API，它允许你创建新的Area，这个Area无需导入就可提供给定节点实例的全部API（包括隐式转换）：" +msgstr "还有一个API，它允许你创建新的 ``Area`` ，这个 ``Area`` 无需导入就可提供给定节点实例的全部API（包括隐式转换）：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:353 msgid "" @@ -555,228 +506,196 @@ msgid "Links" msgstr "Links" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:359 -#, fuzzy msgid "" "There is few different ``Link`` already implemented (but you could also " "create your own custom one). The idea of links is to connect two nodes " "together in various ways. They generally have a ``up`` Node and a " "``down`` ``Node``." msgstr "" -"目前已经实现了一些不同的Links（但您也可以创建自己的自定义Links）。Links的思想是以各种方式将两个节点连接在一起，它们通常有一个 " -"`up` 节点和一个 `down` 节点。" +"目前已经实现了一些不同的 ``Link`` （但您也可以创建自己的自定义 ``Link`` ）。" +" ``Links`` 的设计初衷是以各种方式将两个节点连接在一起，它们通常有一个 ``up`` 节点和一个 ``down`` 节点。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:364 msgid "DirectLink" msgstr "DirectLink" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:366 -#, fuzzy msgid "Very simple, it connect two nodes with signals only. Here is an example :" -msgstr "非常简单，它只使用导线连接两个节点。以下是一个示例：" +msgstr "非常简单，它只使用信号连接两个节点。以下是一个示例：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:375 msgid "StageLink" msgstr "StageLink" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:377 -#, fuzzy msgid "" "This connect two nodes using registers on the ``data``/``valid`` signals " "and some arbitration on the ``ready``." -msgstr "这使用data/valid信号上的寄存器和ready信号上的一些仲裁连接了两个节点。" +msgstr "通过 ``data``/``valid`` 信号上的寄存器和 ``ready`` 信号上的一些仲裁，实现两个节点的连接。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:385 msgid "S2mLink" msgstr "S2mLink" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:387 -#, fuzzy msgid "" "This connect two nodes using registers on the ``ready`` signal, which can" " be useful to improve backpressure combinatorial timings." -msgstr "这使用ready信号上的寄存器连接两个节点，这对于改进反压组合时序非常有用。" +msgstr "这使用 ``ready`` 信号上的寄存器连接两个节点，这对于改进反压组合时序非常有用。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:394 msgid "CtrlLink" msgstr "CtrlLink" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:396 -#, fuzzy msgid "" "This is a kind of special ``Link``, as it connects two nodes with " "optional flow control / bypass logic. Its API should be flexible enough " "to implement a CPU stage with it." -msgstr "这是一种特殊的 Link，用于连接两个节点，具有可选的流量控制/旁路逻辑。它的应用程序接口应该足够灵活，可以用它来实现 CPU 流水级。" +msgstr "这是一种特殊的 ``Link`` ，用于连接两个节点，具有可选的流量控制/旁路逻辑。它的应用程序接口应该足够灵活，可以用它来实现 CPU 流水级。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:399 msgid "Here is its flow control API (The Bool arguments enable the features) :" msgstr "以下是其流量控制 API（Bool 参数启用了相关功能）：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:407 -#, fuzzy msgid "``haltWhen(Bool)``" -msgstr "haltWhen(Bool)" +msgstr "``haltWhen(Bool)``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:408 -#, fuzzy msgid "" "Allows to block the current transaction (clear ``up.ready`` and " "``down.valid``)" -msgstr "允许阻止当前传输事务（清除 up.ready down.valid）" +msgstr "允许阻止当前传输事务（清除 ``up.ready`` 和 ``down.valid`` ）" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:409 -#, fuzzy msgid "``throwWhen(Bool)``" -msgstr "throwWhen(Bool)" +msgstr "``throwWhen(Bool)``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:410 -#, fuzzy msgid "" "Allows to cancel the current transaction from the pipeline (clear " "``down.valid`` and make the transaction driver forget its current state)" -msgstr "允许从流水线中取消当前事务（清除 down.valid，使事务驱动逻辑忘记其当前状态）" +msgstr "允许从流水线中取消当前事务（清除 ``down.valid`` ，使事务驱动逻辑忘记其当前状态）" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:411 -#, fuzzy msgid "``forgetOneWhen(Bool)``" -msgstr "forgetOneWhen(Bool)" +msgstr "``forgetOneWhen(Bool)``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:412 -#, fuzzy msgid "" "Allows to request the upstream to forget its current transaction (but " "doesn't clear the ``down.valid``)" -msgstr "允许请求上游节点忘记其当前事务（但不会清除 down.valid）" +msgstr "允许请求上游节点忘记其当前事务（但不会清除 ``down.valid`` ）" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:413 -#, fuzzy msgid "``ignoreReadyWhen(Bool)``" -msgstr "ignoreReadyWhen(Bool)" +msgstr "``ignoreReadyWhen(Bool)``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:414 -#, fuzzy msgid "Allows to ignore the downstream ready (set ``up.ready``)" -msgstr "允许忽略下游节点ready（设置 up.ready 为1）" +msgstr "允许忽略下游节点ready（设置 ``up.ready`` 为1）" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:415 -#, fuzzy msgid "``duplicateWhen(Bool)``" -msgstr "duplicateWhen(Bool)" +msgstr "``duplicateWhen(Bool)``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:416 -#, fuzzy msgid "Allows to duplicate the current transaction (clear ``up.ready``)" -msgstr "允许复制当前传输事务（清零 up.ready）" +msgstr "允许复制当前传输事务（清零 ``up.ready`` ）" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:417 -#, fuzzy msgid "``terminateWhen(Bool)``" -msgstr "terminateWhen(Bool)" +msgstr "``terminateWhen(Bool)``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:418 -#, fuzzy msgid "" "Allows to hide the current transaction from downstream (clear " "``down.valid``)" -msgstr "允许下游节点隐藏当前传输事务（清零 down.valid）" +msgstr "允许下游节点隐藏当前传输事务（清零 ``down.valid`` ）" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:420 -#, fuzzy msgid "" "Also note that if you want to do flow control in a conditional scope (ex " "in a ``when`` statement), you can call the following functions :" -msgstr "还要注意的是，如果要在条件作用域（例如在 when 语句中）进行通信流控制，可以调用以下函数 ：" +msgstr "还要注意的是，如果要在条件作用域（例如在 ``when`` 语句中）进行通信流控制，可以调用以下函数 ：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:423 -#, fuzzy msgid "" "``haltIt()``, ``duplicateIt()``, ``terminateIt()``, ``forgetOneNow()``, " "``ignoreReadyNow()``, ``throwIt()``" msgstr "" -"haltIt(), duplicateIt(), terminateIt(), forgetOneNow(), ignoreReadyNow()," -" throwIt()" +"``haltIt()``, ``duplicateIt()``, ``terminateIt()``, ``forgetOneNow()``, " +"``ignoreReadyNow()``, ``throwIt()``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:436 -#, fuzzy msgid "" "You can retrieve which nodes are connected to the ``Link`` using " "``node.up`` / ``node.down``." -msgstr "您可以使用 node.up / node.down 查看哪些节点连接到了链接。" +msgstr "您可以使用 ``node.up`` / ``node.down`` 查看哪些节点连接到了链接。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:438 -#, fuzzy msgid "The ``CtrlLink`` also provide an API to access ``Payload`` :" -msgstr "CtrlLink 还提供了访问Payload的 API：" +msgstr "``CtrlLink`` 还提供了访问 ``Payload`` 的 API：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:446 -#, fuzzy msgid "``link(Payload)``" -msgstr "link(Payload)" +msgstr "``link(Payload)``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:447 -#, fuzzy msgid "Same as ``Link.down(Payload)``" -msgstr "与 Link.down(Payload) 相同" +msgstr "与 ``Link.down(Payload)`` 相同" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:448 -#, fuzzy msgid "``link(Payload, Any)``" -msgstr "link(Payload, Any)" +msgstr "``link(Payload, Any)``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:449 -#, fuzzy msgid "Same as ``Link.down(Payload, Any)``" -msgstr "与 Link.down(Payload, Any) 相同" +msgstr "与 ``Link.down(Payload, Any)`` 相同" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:450 -#, fuzzy msgid "``link.insert(Data)``" -msgstr "link.insert(Data)" +msgstr "``link.insert(Data)``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:451 -#, fuzzy msgid "Same as ``Link.down.insert(Data)``" -msgstr "与 Link.down.insert(Data) 相同" +msgstr "与 ``Link.down.insert(Data)`` 相同" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:452 -#, fuzzy msgid "``link.bypass(Payload)``" -msgstr "link.bypass(Payload)" +msgstr "``link.bypass(Payload)``" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:453 -#, fuzzy msgid "" "Allows to conditionally override a ``Payload`` value between ``link.up`` " "-> ``link.down``. This can be used to fix data hazard in CPU pipelines " "for instance." -msgstr "允许在 link.up -> link.down 之间有条件地覆盖 Payload 值。例如，这可用于修复 CPU 流水线中的数据冲突。" +msgstr "允许在 ``link.up`` -> ``link.down`` 之间有条件地覆盖 ``Payload`` 值。例如，这可用于修复 CPU 流水线中的数据冲突。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:472 -#, fuzzy msgid "" "Note that if you create a ``CtrlLink`` without node arguments, it will " "create its own nodes internally." -msgstr "请注意，如果创建的 CtrlLink 不带节点参数，它将在内部创建自己的节点。" +msgstr "请注意，如果创建的 ``CtrlLink`` 不带节点参数，它将在内部创建自己的节点。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:483 msgid "Other Links" msgstr "其他链接" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:485 -#, fuzzy msgid "There is also a ``JoinLink`` / ``ForkLink`` implemented." -msgstr "此外，还实现了 JoinLink / ForkLink。" +msgstr "此外，还实现了 ``JoinLink`` / ``ForkLink`` 。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:488 msgid "Your custom Link" -msgstr "您的自定义链接" +msgstr "自定义链接" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:490 -#, fuzzy msgid "" "You can implement your custom links by implementing the ``Link`` base " "class." -msgstr "您可以通过实现 Link 基类来实现自定义链接。" +msgstr "您可以通过实现 ``Link`` 基类来实现自定义链接。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:503 msgid "But that API may change a bit, as it is still fresh." @@ -787,11 +706,10 @@ msgid "Builders" msgstr "Builders" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:508 -#, fuzzy msgid "" "To generate the hardware of your pipeline, you need to give a list of all" " the links used in your pipeline." -msgstr "要生成流水线硬件，您需要提供流水线中使用的所有链接列表。" +msgstr "要生成流水线硬件，你需要提供流水线中使用的所有链接列表。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:523 msgid "" @@ -804,15 +722,16 @@ msgid "StagePipeline" msgstr "StagePipeline" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:528 -#, fuzzy msgid "" "For instance there is the ``StagePipeline`` class which serve two " "purposes : - It ease the creation of simple pipelines which are composed " "of : ``Node`` -> ``StageLink`` -> ``Node`` -> ``StageLink`` -> ... - It " "extends the pipeline length on the fly" msgstr "" -"例如，StagePipeline 类有两个作用： - 它便于创建简单的流水线，这些流水线由后面部分组成：Node -> StageLink -> " -"Node -> StageLink -> ... - 它可以动态地扩展流水线长度" +"``StagePipeline`` 类有两个用途： " +"- 它便于创建简单的流水线，这类流水线的结构为：" +"``Node`` -> ``StageLink`` -> ``Node`` -> ``StageLink`` -> ... " +"- 它可以动态地扩展流水线长度" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:532 #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:573 @@ -843,35 +762,31 @@ msgid "StageCtrlPipeline" msgstr "StageCtrlPipeline" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:570 -#, fuzzy msgid "" "Very similar to ``StagePipeline``, but it replace Nodes by ``CtrlLink``, " "allowing to handle the arbitration / bypasses on each stages, which is " "for instance quite useful for CPU designs." msgstr "" -"与 StagePipeline 非常相似，但它用 StageLink 代替了 Nodes，允许在每个阶段上处理仲裁/旁路，这在 CPU " +"与 StagePipeline 非常相似，但它用 ``CtrlLink`` 代替了 ``Node``，允许在每个阶段上处理仲裁/旁路，这在 CPU " "设计中非常有用。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:577 -#, fuzzy msgid "Check the sum value and eventually drop the transaction at stage 2" msgstr "检查总和值，最终在第2级放弃该次传输" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:612 msgid "Composability" -msgstr "组合能力（Composability）" +msgstr "组合能力" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:614 -#, fuzzy msgid "" "One good thing about the API is that it easily allows to compose a " "pipeline with multiple parallel things. What it means by \"compose\" is " "that sometime the pipeline you need to design has parallel processing to " "do." -msgstr "该API的一个优点是，它可以轻松地将多个并行事物组成一个流水线。这里的 \"组成 \"是指有时你设计的流水线需要进行并行处理。" +msgstr "该API的一个优点是，它可以轻松地将多个并行事物组成一个流水线。这里的“组成”是指有时你设计的流水线需要进行并行处理。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:617 -#, fuzzy msgid "" "Imagine you need to do floating point multiplication on 4 pairs of " "numbers (to later sum them). If those 4 pairs are provided at the same " @@ -889,11 +804,10 @@ msgid "" msgstr "下面的示例展示了一种模式，它将多个通道组成一个流水线，来并行处理它们。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:666 -#, fuzzy msgid "" "This will produce the following data path (assuming ``lanesCount = 2``), " "arbitration not being shown :" -msgstr "这将产生以下数据路径（假设 lanesCount = 2），这里没有给出仲裁：" +msgstr "这将产生以下数据路径（假设 ``lanesCount = 2`` ），这里没有给出仲裁：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:673 msgid "Retiming / Variable length" @@ -920,11 +834,10 @@ msgid "If then you generate this component like this :" msgstr "如果像这样生成该组件：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:756 -#, fuzzy msgid "" "You will get 4 stages separated by 3 layers of flip-flops doing your " "processing :" -msgstr "您将获得由 3 层寄存器（flip flop）分隔的 4 个处理阶段：" +msgstr "您将获得由 3 层寄存器（flip-flops）分隔的 4 个处理阶段：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:761 msgid "" @@ -933,7 +846,6 @@ msgid "" msgstr "请注意，生成的硬件 verilog 还算干净（至少按我的标准来说是这样 :P）：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:876 -#, fuzzy msgid "" "Also, you can easily tweak how many stages and where you want the " "processing to be done, for instance you may want to move the inversion " @@ -942,24 +854,22 @@ msgid "" msgstr "此外，您还可以轻松调整处理的级数和位置，例如，您可能希望将翻转的硬件逻辑移到与加法器相同级上。具体方法如下：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:891 -#, fuzzy msgid "When you may want to remove the output register stage :" msgstr "那么您可能需要移除输出寄存器级：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:905 -#, fuzzy msgid "" "One thing about this example is the necessity intermediate val as " "``addNode``. I mean :" -msgstr "这个示例的一个特点是，中间值必须是 `addNode`。例如：" +msgstr "这个示例的一个特点是，中间值必须是 ``addNode`` 。例如：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:915 msgid "" "Unfortunately, scala doesn't allow to replace `new addNode.Area` with " "`new nodes(addAt).Area`. One workaround is to define a class as :" msgstr "" -"遗憾的是，scala 不允许用 `new nodes(addAt).Area` 替换 `new " -"addNode.Area`。一种变通方法是将其定义为一个类，比如：" +"遗憾的是，scala 不允许用 `new nodes(addAt).Area` 替换 `new addNode.Area`。" +"一种变通方法是将其定义为一个类，比如：" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:925 msgid "Depending the scale of your pipeline, it can payoff." @@ -992,9 +902,8 @@ msgid "" msgstr "下面是一个简单的测试平台，它实现了一个循环，使 led 计数值上升。" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:1029 -#, fuzzy msgid "Note" -msgstr "Node" +msgstr "Note" #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:1030 msgid "" @@ -1005,14 +914,16 @@ msgid "" "or ``node.valid`` signal creation (important if you use ``CtrlLink()`` or" " any other link where you want flow control) ``node(0).valid`` must be " "driven manually." -msgstr "" +msgstr "构建流水线时，只有 ``node(0).valid`` 或 ``node(n).ready`` （其中 ``n`` 是流水线中的最后一级）可能由用户逻辑驱动。" +"如果 ``node.ready`` 或 ``node.valid`` 信号未使用，构建器可能会优化掉它们。" +"为了保证 ``node.ready`` 或 ``node.valid`` 信号的创建（如果您使用 ``CtrlLink()`` 或任何其他您想要流量控制的链接，这一点很重要），必须手动驱动 ``node(0).valid`` 。 #: ../../SpinalHDL/Libraries/Pipeline/introduction.rst:1044 msgid "" "This is sufficient to ensure halting and ``CtrlLink`` behaviour works as " "intended (``node.valid`` or ``node.ready`` signals are not optimised " "away)." -msgstr "" +msgstr "这足以确保 halting 和 ``CtrlLink`` 行为按预期工作（``node.valid`` 或 ``node.ready`` 信号不会被优化掉）。" #~ msgid "" #~ "For instance there is the NodesBuilder" From fad3a20e5a19e8264dff8889c29ed0cb04d94453 Mon Sep 17 00:00:00 2001 From: CatalpaEel <139088727+CatalpaEel@users.noreply.github.com> Date: Wed, 11 Feb 2026 22:52:25 +0800 Subject: [PATCH 2/3] Fix most of the fuzzy in zh_CN translation --- .../LC_MESSAGES/SpinalHDL/Data types/AFix.po | 10 +- .../LC_MESSAGES/SpinalHDL/Data types/Fix.po | 19 ++-- .../LC_MESSAGES/SpinalHDL/Data types/Int.po | 32 +++--- .../LC_MESSAGES/SpinalHDL/Data types/Vec.po | 5 +- .../LC_MESSAGES/SpinalHDL/Data types/bool.po | 16 ++- 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.../Libraries/Bus/avalon/avalonmm.po | 1 - .../Libraries/Bus/tilelink/tilelink.po | 1 - .../Libraries/Bus/tilelink/tilelink_fabric.po | 21 ++-- .../SpinalHDL/Libraries/Com/usb_device.po | 17 +--- .../SpinalHDL/Libraries/Com/usb_ohci.po | 3 - .../SpinalHDL/Libraries/EDA/altera/qsysify.po | 1 - .../Libraries/Misc/PLIC/plic_mapper.po | 3 - .../SpinalHDL/Libraries/Misc/Plru.po | 27 +++-- .../LC_MESSAGES/SpinalHDL/Libraries/fiber.po | 18 +--- .../LC_MESSAGES/SpinalHDL/Libraries/flow.po | 1 - .../LC_MESSAGES/SpinalHDL/Libraries/index.po | 1 - .../LC_MESSAGES/SpinalHDL/Libraries/logic.po | 43 ++++---- .../LC_MESSAGES/SpinalHDL/Libraries/regIf.po | 10 +- .../LC_MESSAGES/SpinalHDL/Libraries/stream.po | 41 +++----- .../LC_MESSAGES/SpinalHDL/Libraries/utils.po | 9 +- .../Other language features/report.po | 3 +- .../Other language features/scope_property.po | 1 - .../SpinalHDL/Other language features/stub.po | 1 - .../Other language features/utils.po | 2 - .../vhdl_generation.po | 99 ++++++++++--------- .../SpinalHDL/Semantic/assignments.po | 13 +-- .../LC_MESSAGES/SpinalHDL/Semantic/rules.po | 11 +-- .../SpinalHDL/Semantic/when_switch.po | 6 +- .../SpinalHDL/Sequential logic/memory.po | 10 +- .../SpinalHDL/Sequential logic/registers.po | 18 ++-- .../SpinalHDL/Simulation/bootstraps.po | 1 - .../LC_MESSAGES/SpinalHDL/Simulation/clock.po | 12 +-- .../SpinalHDL/Simulation/install/GHDL.po | 1 - .../Simulation/install/Icarus Verilog.po | 1 - .../SpinalHDL/Simulation/install/VCS.po | 1 - .../SpinalHDL/Simulation/install/Verilator.po | 1 - .../SpinalHDL/Structuring/blackbox.po | 1 - .../SpinalHDL/Structuring/clock_domain.po | 12 +-- .../Structuring/components_hierarchy.po | 8 +- .../SpinalHDL/Structuring/index.po | 1 - .../SpinalHDL/Structuring/naming.po | 9 +- .../SpinalHDL/Structuring/parametrization.po | 3 - .../miscelenea/core/core_components.po | 12 +-- .../SpinalHDL/miscelenea/frequent_errors.po | 4 - 64 files changed, 244 insertions(+), 419 deletions(-) diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/AFix.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/AFix.po index 35011977ed4..96ac7d0284e 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/AFix.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/AFix.po @@ -11,8 +11,8 @@ msgstr "" "Language-Team:LANGUAGE MIME-Version:1.0Content-" "Type:text/plain; charset=UTF-8\n" "POT-Creation-Date: 2026-02-11 09:50+0000\n" -"PO-Revision-Date: 2024-01-27 15:40+0000\n" -"Last-Translator: Readon \n" +"PO-Revision-Date: 2026-02-11 20:37+0800\n" +"Last-Translator: CatalpaEel\n" "Language: zh_CN\n" "Language-Team: Chinese (Simplified) \n" @@ -68,16 +68,14 @@ msgid "``AFix.U(12 bits)`` will have a range of 0 to 4095." msgstr "``AFix.U(12 bits)`` 可表示的范围是 0 to 4095。" #: ../../SpinalHDL/Data types/AFix.rst:46 -#, fuzzy msgid "" "``AFix.SQ(8 bits, 4 bits)`` will have a range of -256 (internally " "-4096*2^-4) to 255.9375 (internally 4095*2^-4)" -msgstr "``AFix.SQ(8 bits, 4 bits)`` 的范围为 -4096 (-256) 到 4095 (255.9375)" +msgstr "``AFix.SQ(8 bits, 4 bits)`` 的范围为 -256 （内部值为-4096*2^-4） 到 255.9375（内部值为4095*2^-4）" #: ../../SpinalHDL/Data types/AFix.rst:48 -#, fuzzy msgid "``AFix.U(8 exp, 4 exp)`` will have a range of 0 to 240 (internally 15*2^4)" -msgstr "``AFix.U(8 exp, 4 exp)`` 的范围为 0 到 256" +msgstr "``AFix.U(8 exp, 4 exp)`` 的范围为 0 到 240 （内部值为 15*2^4）" #: ../../SpinalHDL/Data types/AFix.rst:51 msgid "" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Fix.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Fix.po index f2254fd7253..ddc267a7cfd 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Fix.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Fix.po @@ -11,8 +11,8 @@ msgstr "" "Language-Team:LANGUAGE MIME-Version:1.0Content-" "Type:text/plain; charset=UTF-8\n" "POT-Creation-Date: 2026-02-11 09:50+0000\n" -"PO-Revision-Date: 2023-12-14 06:03+0000\n" -"Last-Translator: Readon \n" +"PO-Revision-Date: 2026-02-11 20:49+0800\n" +"Last-Translator: CatalpaEel\n" "Language: zh_CN\n" "Language-Team: Chinese (Simplified) \n" @@ -508,27 +508,24 @@ msgid "Name" msgstr "名称" #: ../../SpinalHDL/Data types/Fix.rst:274 -#, fuzzy msgid "x.minExp" -msgstr "x.minValue" +msgstr "x.minExp" #: ../../SpinalHDL/Data types/Fix.rst:275 msgid "Return a negative number of bits used for the fractional part" msgstr "" #: ../../SpinalHDL/Data types/Fix.rst:276 -#, fuzzy msgid "Int" -msgstr "UInt" +msgstr "Int" #: ../../SpinalHDL/Data types/Fix.rst:277 msgid "x.maxValue" msgstr "x.maxValue" #: ../../SpinalHDL/Data types/Fix.rst:278 -#, fuzzy msgid "Return the largest positive real number storable" -msgstr "返回可存储的最小值" +msgstr "返回可存储的最大正实数" #: ../../SpinalHDL/Data types/Fix.rst:279 types/Fix.rst:282 types/Fix.rst:285 msgid "BigDecimal" @@ -539,14 +536,12 @@ msgid "x.minValue" msgstr "x.minValue" #: ../../SpinalHDL/Data types/Fix.rst:281 -#, fuzzy msgid "Return the largest negative real number storable" -msgstr "返回可存储的最小值" +msgstr "返回可存储的最大负实数" #: ../../SpinalHDL/Data types/Fix.rst:284 -#, fuzzy msgid "Return the smallest positive real number storable" -msgstr "返回可存储的最小值" +msgstr "返回可存储的最小正实数" #~ msgid "Return the maximum value storable" #~ msgstr "返回可存储的最大值" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Int.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Int.po index 8d9d2bdcf6c..03a4d9cb953 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Int.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Int.po @@ -11,8 +11,8 @@ msgstr "" "Language-Team:LANGUAGE MIME-Version:1.0Content-" "Type:text/plain; charset=UTF-8\n" "POT-Creation-Date: 2025-05-01 09:36+0000\n" -"PO-Revision-Date: 2024-01-13 05:06+0000\n" -"Last-Translator: tsy0123 <675526215@qq.com>\n" +"PO-Revision-Date: 2026-02-11 21:00+0800\n" +"Last-Translator: CatalpaEel\n" "Language: zh_CN\n" "Language-Team: Chinese (Simplified) \n" @@ -330,13 +330,12 @@ msgid "Set all bits to the given Bool value" msgstr "将所有位设置为给定的布尔值（Spinal Bool）" #: ../../SpinalHDL/Data types/Int.rst:142 -#, fuzzy msgid "" "Notice the difference in behavior between ``x >> 2`` (result 2 bit " "narrower than x) and ``x >> U(2)`` (keeping width) due to the Scala type " "of :code:`y`." msgstr "" -"请注意由于 :code:`y` 的 Scala 类型原因， ``x >> 2`` （结果比 x 窄 2 位）和 ``x >> " +"请注意由于 :code:`y` 的 Scala 类型不同， ``x >> 2`` （结果比 x 窄 2 位）和 ``x >> " "U(2)``（保持宽度）之间的行为有差异。" #: ../../SpinalHDL/Data types/Int.rst:145 @@ -696,9 +695,8 @@ msgid "Static bit access of y-th bit" msgstr "静态访问第 y 位" #: ../../SpinalHDL/Data types/Int.rst:383 -#, fuzzy msgid "x(y: UInt)" -msgstr "x(y: Int)" +msgstr "x(y: UInt)" #: ../../SpinalHDL/Data types/Int.rst:384 msgid "Variable bit access of y-th bit" @@ -1014,16 +1012,14 @@ msgid "About Rounding: https://en.wikipedia.org/wiki/Rounding" msgstr "关于舍入运算: https://en.wikipedia.org/wiki/Rounding" #: ../../SpinalHDL/Data types/Int.rst -#, fuzzy msgid "Spinal HDL" -msgstr "SpinalHDL" +msgstr "Spinal HDL" #: ../../SpinalHDL/Data types/Int.rst msgid "name" msgstr "" #: ../../SpinalHDL/Data types/Int.rst -#, fuzzy msgid "Wikipedia" msgstr "维基百科中的名称" @@ -1032,24 +1028,20 @@ msgid "API" msgstr "API" #: ../../SpinalHDL/Data types/Int.rst -#, fuzzy msgid "Mathematic" -msgstr "算术运算" +msgstr "数学运算" #: ../../SpinalHDL/Data types/Int.rst -#, fuzzy msgid "Algorithm" -msgstr "算术运算" +msgstr "算法" #: ../../SpinalHDL/Data types/Int.rst -#, fuzzy msgid "return" msgstr "返回类型" #: ../../SpinalHDL/Data types/Int.rst -#, fuzzy msgid "(align=false)" -msgstr "返回类型（align=false）" +msgstr "（align=false）" #: ../../SpinalHDL/Data types/Int.rst msgid "Sup-" @@ -1252,20 +1244,18 @@ msgid "" "different programming languages may be different." msgstr "" "你会发现 " -"`ROUNDUP`、`ROUNDDOWN`、`ROUNDTOZERO`、`ROUNDTOINF`、`ROUNDTOEVEN`、`ROUNTOODD`" +"`ROUNDUP`、`ROUNDDOWN`、`ROUNDTOZERO`、`ROUNDTOINF`、`ROUNDTOEVEN`、`ROUNDTOODD`" " 在行为上非常接近，`ROUNDTOINF` 是最常见的。不同编程语言中的舍入行为可能不同。" #: ../../SpinalHDL/Data types/Int.rst:594 -#, fuzzy msgid "language" -msgstr "范围" +msgstr "语言" #: ../../SpinalHDL/Data types/Int.rst:594 msgid "default-RoundType" msgstr "默认舍入类型" #: ../../SpinalHDL/Data types/Int.rst:594 -#, fuzzy msgid "example" msgstr "示例" @@ -1295,7 +1285,7 @@ msgstr "python2" #: ../../SpinalHDL/Data types/Int.rst:600 msgid "python3" -msgstr "蟒蛇3" +msgstr "python3" #: ../../SpinalHDL/Data types/Int.rst msgid "``round(1.5) == round(2.5) == 2``" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Vec.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Vec.po index 7f99f6cb519..3a2691c71ed 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Vec.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/Vec.po @@ -70,9 +70,8 @@ msgid "This constructor supports mixed element width." msgstr "此构造函数支持混合宽度的元素。" #: ../../SpinalHDL/Data types/Vec.rst:31 -#, fuzzy msgid "Vec.fill(n1, n2, ...)(type: Data)" -msgstr "Vec.fill(size: Int)(type: Data)" +msgstr "Vec.fill(n1, n2, ...)(type: Data)" #: ../../SpinalHDL/Data types/Vec.rst:32 msgid "Create a multi-dimensional vector. Supports up to 5 dimensions" @@ -175,7 +174,6 @@ msgid "x.sCount(condition: T => Bool)" msgstr "x.sCount(condition: T => Bool)" #: ../../SpinalHDL/Data types/Vec.rst:166 -#, fuzzy msgid "Count the number of occurrence matching a given condition in the Vec." msgstr "计算 Vec 中与给定条件匹配的次数。" @@ -188,7 +186,6 @@ msgid "x.sCount(value: T)" msgstr "x.sCount(value: T)" #: ../../SpinalHDL/Data types/Vec.rst:169 -#, fuzzy msgid "Count the number of occurrence of a value in the Vec." msgstr "计算 Vec 中某个值出现的次数。" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/bool.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/bool.po index a99d2fb0e9f..c3e8d8b457d 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/bool.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/bool.po @@ -11,8 +11,8 @@ msgstr "" "Language-Team:LANGUAGE MIME-Version:1.0Content-" "Type:text/plain; charset=UTF-8\n" "POT-Creation-Date: 2025-02-12 09:08+0000\n" -"PO-Revision-Date: 2024-01-13 05:06+0000\n" -"Last-Translator: tsy0123 <675526215@qq.com>\n" +"PO-Revision-Date: 2026-02-11 20:47+0800\n" +"Last-Translator: CatalpaEel\n" "Language: zh_CN\n" "Language-Team: Chinese (Simplified) \n" @@ -37,18 +37,16 @@ msgid "Description" msgstr "描述" #: ../../SpinalHDL/Data types/bool.rst:9 -#, fuzzy msgid "" "The ``Bool`` type corresponds to a boolean value (True or False) or a " "single bit/signal used in a hardware design. While named similarly it " "should not be confused with Scala `Boolean` type which does not describe " "hardware but truth values in the Scala generator code." msgstr "" -"``Bool`` 类型对应于硬件设计中使用的布尔值（True 或 False）或单个位/线。虽然名称类似，但不应与 Scala `Boolean`" +"``Bool`` 类型对应于硬件设计中使用的布尔值（True 或 False）或单个比特/信号。虽然名称类似，但不应与 Scala `Boolean`" " 类型混淆，后者不描述硬件，而是描述 Scala 生成器代码中的真值。" #: ../../SpinalHDL/Data types/bool.rst:14 -#, fuzzy msgid "" "An important concept and rule-of-thumb to understand is that the Scala " "`Boolean` type is used in places where elaboration-time HDL code-" @@ -56,8 +54,8 @@ msgid "" "program it affects execution of the Scala program that is SpinalHDL at " "the time the program is being run to perform HDL code generation." msgstr "" -"需要理解的一个重要概念和经验是，Scala `Boolean` 类型用于在实例细化时决定如何生成 HDL 代码。与任何常规程序一样，在运行 " -"SpinalHDL 程序以执行 HDL 代码生成时，它会影响 Scala 程序的执行。" +"需要理解的一个重要概念和经验是，Scala `Boolean` 类型用于在实例细化时决定如何生成 HDL 代码。与任何常规程序一样，" +"它会影响 SpinalHDL 这一 Scala 程序在运行以执行 HDL 代码生成时的执行过程。" #: ../../SpinalHDL/Data types/bool.rst:20 msgid "" @@ -99,7 +97,6 @@ msgstr "" "实例指示它是给定赋值的源（提供状态）还是接收器（捕获状态）。" #: ../../SpinalHDL/Data types/bool.rst:37 -#, fuzzy msgid "" "Multiple uses of the assignment operator are allowed, such that it is " "normal for a signal to act as a source (provides a value to drive HDL " @@ -315,7 +312,6 @@ msgid "" msgstr "所有边缘检测函数都将通过 :ref:`RegNext ` 实例化一个附加寄存器，以获取相关 ``Bool`` 的延迟值（一拍）。" #: ../../SpinalHDL/Data types/bool.rst:178 -#, fuzzy msgid "" "This feature does not reconfigure a D-type flip-flop to use an " "alternative CLK source, it uses two D-type flip-flop in series chain " @@ -323,7 +319,7 @@ msgid "" "combinational logic to perform edge detection based on the output Q " "states." msgstr "" -"此功能不会重新配置 D 型触发器以使用其他 CLK 时钟，它使用串联链中的两个 D 型触发器（两个 CLK 引脚都继承默认的 " +"此功能不会重新配置 D 型触发器以使用其他 CLK 时钟，而是采用两个 D 型触发器串联（两者 CLK 引脚都继承默认的 " "ClockDomain）。它具有组合逻辑，可根据输出 Q 状态进行边缘检测。" #: ../../SpinalHDL/Data types/bool.rst:190 diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/index.po index 494434705d8..fcc37c604ea 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/index.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Data types/index.po @@ -62,7 +62,6 @@ msgid ":ref:`Floating-point ` numbers (experimental support)" msgstr ":ref:`Floating-point ` 浮点小数（实验性支持）" #: ../../SpinalHDL/Data types/index.rst:22 -#, fuzzy msgid "" "Additionally, if you want to assign a don't care value to some hardware, " "for instance, to provide a default value, you can use the assignDontCare " diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/partially_assigned_register.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/partially_assigned_register.po index 0ec4b8c919e..b83d997fb75 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/partially_assigned_register.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/partially_assigned_register.po @@ -3,14 +3,13 @@ # This file is distributed under the same license as the SpinalHDL package. # FIRST AUTHOR , 2025. # -#, fuzzy msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" "POT-Creation-Date: 2025-12-09 17:37+0000\n" -"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" -"Last-Translator: FULL NAME \n" +"PO-Revision-Date: 2026-02-11 21:09+0800\n" +"Last-Translator: CatalpaEel\n" "Language: zh_CN\n" "Language-Team: zh_CN \n" "Plural-Forms: nplurals=1; plural=0;\n" @@ -21,11 +20,11 @@ msgstr "" #: ../../SpinalHDL/Design errors/partially_assigned_register.rst:2 msgid "Partially assigned register" -msgstr "" +msgstr "寄存器部分赋值(Partially assigned register)" #: ../../SpinalHDL/Design errors/partially_assigned_register.rst:5 msgid "Introduction" -msgstr "" +msgstr "简介" #: ../../SpinalHDL/Design errors/partially_assigned_register.rst:7 msgid "" @@ -33,53 +32,54 @@ msgid "" "bits of the register must at least be assigned once. If some bits are " "left unassigned, it can lead to unintended hardware behavior such as " "latches or unpredictable values." -msgstr "" +msgstr "SpinalHDL 会进行检查：当寄存器被条件赋值时，其所有位都必须至少被赋值一次。" +"若某些位未被赋值，可能导致意外的硬件行为，例如生成锁存器或出现不可预测的值。" #: ../../SpinalHDL/Design errors/partially_assigned_register.rst:9 msgid "This error occurs when:" -msgstr "" +msgstr "此错误发生于以下情况：" #: ../../SpinalHDL/Design errors/partially_assigned_register.rst:11 msgid "A register is assigned within a conditional block (``when``/``switch``)" -msgstr "" +msgstr "寄存器在条件块内( ``when`` / ``switch`` )赋值" #: ../../SpinalHDL/Design errors/partially_assigned_register.rst:12 msgid "Only some bits of the register are assigned" -msgstr "" +msgstr "寄存器只有部分比特被赋值" #: ../../SpinalHDL/Design errors/partially_assigned_register.rst:13 msgid "Other bits are left without assignment in that path" -msgstr "" +msgstr "该分支上，其他位未被赋值" #: ../../SpinalHDL/Design errors/partially_assigned_register.rst:16 msgid "Example" -msgstr "" +msgstr "示例" #: ../../SpinalHDL/Design errors/partially_assigned_register.rst:18 msgid "The following code:" -msgstr "" +msgstr "下面的代码：" #: ../../SpinalHDL/Design errors/partially_assigned_register.rst:39 msgid "will throw:" -msgstr "" +msgstr "会报错：" #: ../../SpinalHDL/Design errors/partially_assigned_register.rst:49 msgid "How to fix it" -msgstr "" +msgstr "修复方法" #: ../../SpinalHDL/Design errors/partially_assigned_register.rst:51 msgid "There are several ways to fix this error:" -msgstr "" +msgstr "有以下几种方法可修复此错误：" #: ../../SpinalHDL/Design errors/partially_assigned_register.rst:53 msgid "**Solution 1: Assign the complete register**" -msgstr "" +msgstr "**方法一：完整赋值寄存器**" #: ../../SpinalHDL/Design errors/partially_assigned_register.rst:75 msgid "**Solution 2: Explicitly handle all bits**" -msgstr "" +msgstr "**方法二：显式处理所有位**" #: ../../SpinalHDL/Design errors/partially_assigned_register.rst:97 msgid "**Solution 3: Provide a default value**" -msgstr "" +msgstr "**方法三：提供默认值**" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/spinal_cant_clone.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/spinal_cant_clone.po index 5a8b883abb9..8f32b9b9301 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/spinal_cant_clone.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Design errors/spinal_cant_clone.po @@ -59,7 +59,6 @@ msgid "Example 2" msgstr "例子2" #: ../../SpinalHDL/Design errors/spinal_cant_clone.rst:72 -#, fuzzy msgid "raises an exception:" msgstr "报错：" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/spinalhdl_datamodel.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/spinalhdl_datamodel.po index 751526d97a8..79ce4c00544 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/spinalhdl_datamodel.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/spinalhdl_datamodel.po @@ -112,15 +112,13 @@ msgstr "" "这样的实用工具，它会迭代 *myExpression* 中使用的所有表达式，并将它们替换为您提供的表达式。" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:44 -#, fuzzy msgid "" "More generally, most of the graph checks and transformations done by " "SpinalHDL are located in " "" msgstr "" "通常来说，SpinalHDL 完成的大多数图(graph)关系检查和转换都位于 " -"" +"" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:47 msgid "Exploring the datamodel" @@ -200,9 +198,8 @@ msgid "" msgstr "mySignal.removeAssignments ：将删除所有先前对给定信号的赋值 `:=`" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:159 -#, fuzzy msgid "mySignal.removeStatement : Will void the existence of the signal" -msgstr "mySignal.removeStatement：将消除存在的信号" +msgstr "mySignal.removeStatement：将移除信号" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:160 msgid "" @@ -243,13 +240,13 @@ msgid "You can use the code in the following manner: :" msgstr "您可以通过以下方式使用该代码：" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:197 -#, fuzzy msgid "" "Here is a function that enables you to execute the body code as if the " "current component's context did not exist. This can be particularly " "useful for defining new signals without the influence of the current " "conditional scope (such as `when` or `switch`)." -msgstr "这是一个函数，使您能够执行主体代码，就好像当前组件的上下文不存在一样。这对于定义新信号特别有用，这样信号不受当前条件范围（例如when或switch）的影响。" +msgstr "这个函数使您能够执行主体代码，就好像当前组件的上下文不存在一样。" +"这在定义新信号特别有用，这样信号不受当前条件范围（例如 `when` 或 `switch`）的影响。" #: ../../SpinalHDL/Developers area/spinalhdl_datamodel.rst:238 msgid "" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/types.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/types.po index 48a3be30886..a97c4c18c4d 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/types.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Developers area/types.po @@ -255,12 +255,11 @@ msgid "The BitVector family - (``Bits``, ``UInt``, ``SInt``)" msgstr "BitVector 系列 - (``Bits``, ``UInt``, ``SInt``)" #: ../../SpinalHDL/Developers area/types.rst:120 -#, fuzzy msgid "" "``BitVector`` is a family of types for storing multiple bits of " "information in a single value. This type has three subtypes that can be " "used to model different behaviors:" -msgstr "``BitVector`` 是一个系列的类型，用于在单个值中存储多位信息。该类型具有三个子类型，可用于描述不同的行为：" +msgstr "``BitVector`` 是一类用于在单个值中存储多位信息的类型。该类型具有三个子类型，可用于描述不同的行为：" #: ../../SpinalHDL/Developers area/types.rst:121 msgid "" @@ -914,7 +913,6 @@ msgid "" msgstr "然后，您还可以根据需要将一个线束实例放置在另一个线束中（没有深度限制）：" #: ../../SpinalHDL/Developers area/types.rst:494 -#, fuzzy msgid "And finally instantiate your Bundles inside the hardware :" msgstr "最后在硬件中实例化您的线束：" @@ -990,7 +988,6 @@ msgid "Use the VHDL enumeration system, this is the default encoding" msgstr "使用VHDL枚举系统，这是默认编码" #: ../../SpinalHDL/Developers area/types.rst:668 -#, fuzzy msgid "binarySequential" msgstr "二进制顺序" @@ -1135,9 +1132,8 @@ msgid "" msgstr "字面量通常用作常量值。但您也可以使用它们一次完成两件事：" #: ../../SpinalHDL/Developers area/types.rst:748 -#, fuzzy msgid "Define a signal which is assigned with a constant value" -msgstr "定义一条分配有常量值的连线" +msgstr "定义一个分配有常量值的信号" #: ../../SpinalHDL/Developers area/types.rst:749 msgid "Setup inferred type: UInt(4 bits)" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/slots.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/slots.po index e62ad932e1a..7ed8348f58b 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/slots.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/slots.po @@ -8,8 +8,8 @@ msgstr "" "Type:text/plain; charset=UTF-8\n" "Report-Msgid-Bugs-To: EMAIL@ADDRESS\n" "POT-Creation-Date: 2025-05-01 09:36+0000\n" -"PO-Revision-Date: 2023-12-31 10:03+0000\n" -"Last-Translator: Readon \n" +"PO-Revision-Date: 2026-02-11 21:23+0800\n" +"Last-Translator: CatalpaEel\n" "Language: zh_CN\n" "Language-Team: Chinese (Simplified) \n" @@ -28,7 +28,6 @@ msgid "Introduction" msgstr "简介" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:9 -#, fuzzy msgid "" "Let's say you have some hardware which has to keep track of multiple " "similar ongoing activities, you may want to implement an array of " @@ -36,21 +35,19 @@ msgid "" "``OHMasking.first``, ``onMask`` and ``reader``." msgstr "" "假设您有一些硬件必须跟踪多个相似的正在进行的活动，您可能需要实现一组“插槽”来执行此操作。此示例展示如何使用 " -"Area、OHMasking.first、onMask和reader来完成此操作。" +" ``Area`` 、 ``OHMasking.first`` 、 ``onMask`` 和 ``reader`` 来完成此操作。" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:15 msgid "Implementation" msgstr "实现" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:17 -#, fuzzy msgid "" "This implementation avoid the use of ``Vec``. Instead, it use Area which " "allow to mix signals, registers and logic definitions in each slot." -msgstr "此实现避免使用Vec。相反，它使用允许在每个插槽中混合信号、寄存器和逻辑定义的逻辑区。" +msgstr "此实现不使用Vec，相反，它使用Area，从而允许在每个插槽中混合定义信号、寄存器和逻辑。" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:20 -#, fuzzy msgid "Note that the ``reader`` API is for SpinalHDL version coming after 1.9.1" msgstr "请注意， `reader` API 适用于1.9.1之后推出的SpinalHDL版本" @@ -59,30 +56,29 @@ msgid "In practice" msgstr "应用" #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:29 -#, fuzzy msgid "" "For instance, this kind of slot pattern is used in Tilelink coherency hub" " to keep track of all ongoing memory probes in flight `in SpinalHDL code " "`_." -msgstr "https://github.com/SpinalHDL/SpinalHDL/blob/008c73f1ce18e294f137efe7a1442bd3f8fa2ee0/lib/src/main/scala/spinal/lib/bus/tilelink/coherent/Hub.scala#L376" +msgstr "例如，在Tilelink一致性中心中，这类槽位模式被用于追踪所有正在进行的传输中内存探针，详见 `SpinalHDL代码" +" `_." #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:34 -#, fuzzy msgid "" "As well in the DRAM / SDR / DDR memory controller to implement the " "handling of multiple memory transactions at once (having multiple " "precharge / active / read / write running at the same time to improve " "performances) `here " "`_." -msgstr "以及在 DRAM / SDR / DDR 内存控制器中实现同时处理多个内存事务（同时运行多个预充电/激活/读/写以提高性能）：" +msgstr "以及在 DRAM / SDR / DDR 内存控制器中实现并发处理多个内存事务（同时进行预充电/激活/读/写以提高性能）：详见 `此处 " +"`_." #: ../../SpinalHDL/Examples/Advanced ones/slots.rst:38 -#, fuzzy msgid "" "As well in the NaxRiscv (out of order CPU) load-store-unit to handle the " "store-queue / load-queue hardware (a bit too scary to show here in the " "doc XD)." -msgstr "以及在NaxRiscv（乱序 CPU）的加载存储单元中处理存储队列/加载队列的硬件（难度有些可怕，不宜在文档中展示XD）" +msgstr "以及在NaxRiscv（乱序 CPU）的加载存储单元中处理存储队列/读取队列的硬件（难度有些可怕，不宜在文档中展示XD）" #~ msgid "" #~ "For instance, this kind of slot " diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/timer.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/timer.po index ab9690ce2a5..def4edeaf5b 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/timer.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Advanced ones/timer.po @@ -270,7 +270,6 @@ msgid "0" msgstr "0" #: ../../SpinalHDL/Examples/Advanced ones/timer.rst:126 -#, fuzzy msgid "" "Each ``ticks`` bool can be activated if the corresponding ``ticksEnable``" " bit is high." @@ -289,7 +288,6 @@ msgid "16" msgstr "16" #: ../../SpinalHDL/Examples/Advanced ones/timer.rst:132 -#, fuzzy msgid "" "Each ``clears`` bool can be activated if the corresponding " "``clearsEnable`` bit is high." diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/vga.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/vga.po index dfc72994613..867a85b7e70 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/vga.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Examples/Intermediates ones/vga.po @@ -8,8 +8,8 @@ msgstr "" "Type:text/plain; charset=UTF-8\n" "Report-Msgid-Bugs-To: EMAIL@ADDRESS\n" "POT-Creation-Date: 2024-08-19 09:12+0000\n" -"PO-Revision-Date: 2024-01-23 07:01+0000\n" -"Last-Translator: Readon \n" +"PO-Revision-Date: 2026-02-11 21:28+0800\n" +"Last-Translator: CatalpaEel\n" "Language: zh_CN\n" "Language-Team: Chinese (Simplified) \n" @@ -99,7 +99,7 @@ msgstr "master" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:40 msgid "Vertical synchronization, indicate the beginning of a new frame" -msgstr "垂直同步，表示新帧的开始" +msgstr "场同步，表示新帧的开始" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:41 msgid "hSync" @@ -107,7 +107,7 @@ msgstr "hSync" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:43 msgid "Horizontal synchronization, indicate the beginning of a new line" -msgstr "水平同步，表示新行的开始" +msgstr "行同步，表示新行的开始" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:44 msgid "colorEn" @@ -145,7 +145,7 @@ msgstr "VGA接口使用8种不同的时序进行驱动。以下是一个能够 msgid "" "But this not a very good way to specify it because it is redundant for " "vertical and horizontal timings." -msgstr "但这并不是一种很好的指定方式，因为在垂直和水平时序方面存在冗余。" +msgstr "但这并不是一种很好的指定方式，因为在行场时序方面存在冗余。" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:84 msgid "Let's write it in a clearer way:" @@ -187,7 +187,7 @@ msgstr "timings" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:117 msgid "Specify VGA horizontal and vertical timings" -msgstr "指定 VGA 水平和垂直时序" +msgstr "指定 VGA 行场时序参数" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:118 msgid "pixels" @@ -254,24 +254,23 @@ msgstr "" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:146 msgid "Horizontal and vertical logic" -msgstr "水平和垂直逻辑" +msgstr "行场逻辑" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:148 -#, fuzzy msgid "" "The logic that generates horizontal and vertical synchronization signals " "is quite the same. It kind of resembles ~PWM~. The horizontal one counts " "up each cycle, while the vertical one use the horizontal synchronization " "signal as to increment." -msgstr "产生水平和垂直同步信号的逻辑完全相同，它有点类似于〜PWM〜。水平同步每周期计数一次，垂直同步则利用水平同步信号递增。" +msgstr "产生行同步与场同步信号的逻辑基本一致，它有点类似于脉冲宽度调制（PWM）。" +"行同步信号在每个时钟周期递增计数，而场同步信号则以行同步信号作为计数时钟进行递增。" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:150 -#, fuzzy msgid "" "Let's define ``HVArea``\\ , which represents one ~PWM~ and then " "instantiate it two times: one for both horizontal and vertical " "synchronization." -msgstr "让我们定义 ``HVArea`` ，它代表一个~PWM~，然后实例化它两次：一次用于水平同步，一次用于垂直同步。" +msgstr "让我们定义 ``HVArea`` ，它代表单路脉冲宽度调制（PWM），然后实例化它两次：分别用于行同步与场同步。" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:160 msgid "" @@ -287,7 +286,7 @@ msgstr "互连" msgid "" "Now that we have timing generators for horizontal and vertical " "synchronization, we need to drive the outputs." -msgstr "现在我们有了水平和垂直同步的时序生成器，我们需要驱动输出。" +msgstr "现在我们有了行同步与场同步的时序生成器，我们需要驱动输出。" #: ../../SpinalHDL/Examples/Intermediates ones/vga.rst:176 msgid "Bonus" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Foreword/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Foreword/index.po index c6ff136eebd..73c91a2668c 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Foreword/index.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Foreword/index.po @@ -43,7 +43,6 @@ msgid "" msgstr "为了简洁，我们假设SystemVerilog是Verilog的最新版本。" #: ../../SpinalHDL/Foreword/index.rst:12 -#, fuzzy msgid "" "When reading this, we should not underestimate how much our attachment " "for our favorite HDL will bias our judgement." diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Formal verification/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Formal verification/index.po index 295504977db..f71c28e60bc 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Formal verification/index.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Formal verification/index.po @@ -177,11 +177,10 @@ msgid "Specifying the initial value of a signal" msgstr "指定信号的初始值" #: ../../SpinalHDL/Formal verification/index.rst:234 -#, fuzzy msgid "" "For instance, for the reset signal of the current clock domain (useful at" " the top)" -msgstr "例如，对于当前时钟域的复位信号（在顶部有用）" +msgstr "例如，对于当前时钟域的复位信号（在顶层模块尤为有用）" #: ../../SpinalHDL/Formal verification/index.rst:241 msgid "Specifying a initial assumption" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.po index c4916f85a54..aa93c06e390 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Help for VHDL people/vhdl_comp.po @@ -8,8 +8,8 @@ msgstr "" "Type:text/plain; charset=UTF-8\n" "Report-Msgid-Bugs-To: EMAIL@ADDRESS\n" "POT-Creation-Date: 2025-02-12 09:08+0000\n" -"PO-Revision-Date: 2023-12-15 15:56+0000\n" -"Last-Translator: Readon \n" +"PO-Revision-Date: 2026-02-11 21:31+0800\n" +"Last-Translator: CatalpaEel\n" "Language: zh_CN\n" "Language-Team: Chinese (Simplified) /environment``." msgstr "" -"要在 shell 中使用 oss-cad-suite，您需要加载它的环境，例如通过 ``souce /environment`` 实现。" #: ../../SpinalHDL/Getting Started/Install and setup.rst:87 @@ -305,7 +304,6 @@ msgstr "" "install>`。" #: ../../SpinalHDL/Getting Started/Install and setup.rst:149 -#, fuzzy msgid "" "An All-in-One solution offered by SpinalHDL maintainer `Readon " "`_ is available to install and run SpinalHDL " @@ -329,14 +327,13 @@ msgstr "" "默认控制台。另一种方法是使用“Windows Terminal”或类似 Tabby 的应用程序，并使用启动命令 " "``%MSYS2_ROOT%\\msys2_shell.cmd -defterm -here -no-start -mingw64``，其中 " "``%MSYS2_ROOT%`` 是 msys2 " -"安装的位置。值得注意的是，如果要离线使用，要仔细选择项目所依赖的库，否则需要手动下载安装包。有关更多详细信息，请参阅对应仓库的自述文件。" +"安装的位置。值得注意的是，如果要离线使用，要仔细选择项目所依赖的库，否则需要手动下载安装包。有关更多详细信息，请参阅对应仓库的README。" #: ../../SpinalHDL/Getting Started/Install and setup.rst:158 msgid "MSYS2 verilator for simulation" msgstr "用于仿真的 MSYS2 verilator工具" #: ../../SpinalHDL/Getting Started/Install and setup.rst:160 -#, fuzzy msgid "" "We recommend to install compiler/verilator through `MSYS2 " "`_. Other methods of installing gcc/make/shell " @@ -346,7 +343,6 @@ msgstr "" "的方法（例如 Chocolatey、scoop 等）也可能有效，但未经测试。" #: ../../SpinalHDL/Getting Started/Install and setup.rst:163 -#, fuzzy msgid "" "SpinalHDL maintainer `Readon `_ is maintaining" " a MSYS2 fork that default installs all needed officially available and " @@ -394,7 +390,6 @@ msgid "MSYS2 for formal verification" msgstr "用 MSYS2 实施形式化验证" #: ../../SpinalHDL/Getting Started/Install and setup.rst:198 -#, fuzzy msgid "" "In addition to the steps above we also need to install yosys, sby, z3 and" " yices. Both yosys(yosys-smtbmc workable) and sby are not available as " @@ -403,7 +398,7 @@ msgid "" "steps are not needed (you should check if there are newer packages " "available)." msgstr "" -"除了上面的步骤之外，我们还需要安装yosys、sby、z3和yices。 yosys(可用的yosys-smtbmc) 和 sby 并不使用 " +"除了上面的步骤之外，我们还需要安装yosys、sby、z3和yices。 yosys(需支持yosys-smtbmc) 和 sby 并不使用 " "MSYS2 官方提供的包（无法使用），而是由 `Readon ` " "提供。如果您使用他们的安装程序，则不需要后面这些步骤（您应该检查是否有更新的软件包可用）。" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Scala Guide/basics.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Scala Guide/basics.po index 8a1f6a3e04b..066d318190b 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Scala Guide/basics.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Getting Started/Scala Guide/basics.po @@ -156,7 +156,6 @@ msgid "" msgstr "``return`` 关键字不是必需的。如果没有它，Scala 会将函数的最后一条语句作为返回值。" #: ../../SpinalHDL/Getting Guide/basics.rst:101 Started/Scala -#, fuzzy msgid "Return type inference" msgstr "返回类型推断" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/A simple example.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/A simple example.po index a5a68e911a0..0f9f42175c3 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/A simple example.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/A simple example.po @@ -88,16 +88,14 @@ msgid "Types:" msgstr "类型：" #: ../../SpinalHDL/Introduction/A example.rst:78 simple -#, fuzzy msgid "``cond0``, ``cond1`` and ``flag`` are 1 bit each (as 3 individual signals)" -msgstr "``cond0``、``cond1`` 和 ``flag`` 各为一个比特（3 条单独的线）" +msgstr "``cond0`` 、``cond1`` 和 ``flag`` 各为一个比特（3 条独立的信号）" #: ../../SpinalHDL/Introduction/A example.rst:79 simple -#, fuzzy msgid "" "``state`` is an 8-bit unsigned integer (a bus of 8 signals representing " "an unsigned integer)" -msgstr "``state`` 是一个8位无符号整数（用一组8根线来表示一个无符号整数）" +msgstr "``state`` 是一个8位无符号整数（用一组8个信号来表示一个无符号整数）" #: ../../SpinalHDL/Introduction/A example.rst:84 simple msgid "" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Projects using SpinalHDL.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Projects using SpinalHDL.po index 4b694a4e451..d943399846e 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Projects using SpinalHDL.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Introduction/Projects using SpinalHDL.po @@ -27,7 +27,6 @@ msgid "Projects using SpinalHDL" msgstr "使用 SpinalHDL 的项目" #: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:4 using -#, fuzzy msgid "Note that the following lists are very incomplete." msgstr "请注意，以下列表非常不完整。" @@ -56,9 +55,8 @@ msgstr "" "`_" #: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:15 using -#, fuzzy msgid "`VexiiRiscv CPU `_" -msgstr "`VexRiscv CPU 和 SoC `_" +msgstr "VexiiRiscv CPU `_" #: ../../SpinalHDL/Introduction/Projects SpinalHDL.rst:16 using msgid "`open-rdma `_" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/hardware_toplevel.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/hardware_toplevel.po index 9e0d83f0359..3ea20a43330 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/hardware_toplevel.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/hardware_toplevel.po @@ -164,11 +164,10 @@ msgid "Reset controller" msgstr "复位控制器" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:89 -#, fuzzy msgid "" "First we need to define the reset controller clock domain, which has no " "reset signal, but use the FPGA bitstream loading to setup flip-flops." -msgstr "首先我们需要定义复位控制器时钟域，它没有复位线，而是使用FPGA比特流加载来设置触发器。" +msgstr "首先我们需要定义复位控制器时钟域，该时钟域没有复位信号，而是使用FPGA比特流加载来初始化触发器。" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:100 msgid "Then we can define a simple reset controller under this clock domain." @@ -363,7 +362,6 @@ msgid "" msgstr "该桥将用于将低带宽外设连接到AXI交叉开关。" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:411 -#, fuzzy msgid "" "The AXI4 crossbar that interconnect AXI4 masters and slaves together is " "generated by using an factory. The concept of this factory is to create " @@ -371,8 +369,8 @@ msgid "" "``build`` function to ask the factory to generate the corresponding " "hardware :" msgstr "" -"将AXI4主端和从端互连在一起的AXI4交叉开关是使用生成器(factory)生成的。这个生成器的概念是先创建它，然后调用它的许多函数来配置，最后调用" -" ``build`` 函数来使生成器生成相应的硬件：" +"将AXI4主端和从端互连在一起的AXI4交叉开关是使用生成器(factory)生成的。这个生成器的使用流程：先创建它，然后调用它的许多函数来配置，最后调用" +" ``build`` 函数生成相应的硬件：" #: ../../SpinalHDL/Legacy/pinsec/hardware_toplevel.rst:421 msgid "First you need to populate slaves interfaces :" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/introduction.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/introduction.po index 42c9494d8df..2cb77b07cb6 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/introduction.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Legacy/pinsec/introduction.po @@ -28,7 +28,6 @@ msgid "Introduction" msgstr "简介" #: ../../SpinalHDL/Legacy/pinsec/introduction.rst:10 -#, fuzzy msgid "" "This page only documents the SoC implemented with the first generation of" " RISC-V CPU created in SpinalHDL. This page does not document the " @@ -38,7 +37,7 @@ msgid "" msgstr "" "本页仅记录使用SpinalHDL创造的第一代用RISC-V CPU实现的SoC。本页面未记录VexRiscV CPU，这是该 SoC（和 " "CPU）的第二代，可在 `这里 `__ " -"获得，并提供更好的性能/面积/功能。" +"获得，它在性能/面积/功能方面均有更有表现。" #: ../../SpinalHDL/Legacy/pinsec/introduction.rst:17 msgid "" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/ahblite3.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/ahblite3.po index 91caa127a36..b0d2fce58df 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/ahblite3.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/ahblite3.po @@ -24,7 +24,6 @@ msgid "AHB-Lite3" msgstr "AHB-Lite3" #: ../../SpinalHDL/Libraries/Bus/amba3/ahblite3.rst:6 -#, fuzzy msgid "Configuration and instantiation" msgstr "配置和实例化" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/apb3.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/apb3.po index ef7c61b831d..1ae10eb49ef 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/apb3.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba3/apb3.po @@ -31,7 +31,6 @@ msgid "The AMBA3-APB bus is commonly used to interface low bandwidth peripherals msgstr "AMBA3-APB总线通常用于连接低带宽外设。" #: ../../SpinalHDL/Libraries/Bus/amba3/apb3.rst:8 -#, fuzzy msgid "Configuration and instantiation" msgstr "配置和实例化" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba4/axi4.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba4/axi4.po index 576712bf0df..0ab4d9ab44a 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba4/axi4.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/amba4/axi4.po @@ -31,7 +31,6 @@ msgid "The AXI4 is a high bandwidth bus defined by ARM." msgstr "AXI4是ARM定义的高带宽总线。" #: ../../SpinalHDL/Libraries/Bus/amba4/axi4.rst:7 -#, fuzzy msgid "Configuration and instantiation" msgstr "配置和实例化" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/avalon/avalonmm.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/avalon/avalonmm.po index c4c7b0c69b4..bc5a3f10574 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/avalon/avalonmm.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/avalon/avalonmm.po @@ -49,7 +49,6 @@ msgid "" msgstr "性能不如AXI，但使用的逻辑面积少得多（读取和写入命令使用相同的握手通道。主端不需要存储挂起请求的地址，从而避免读取/写入冒险）" #: ../../SpinalHDL/Libraries/Bus/avalon/avalonmm.rst:12 -#, fuzzy msgid "Configuration and instantiation" msgstr "配置和实例化" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink.po index c85c688465e..230b2bd3e74 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink.po @@ -24,7 +24,6 @@ msgid "Tilelink" msgstr "Tilelink" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink.rst:6 -#, fuzzy msgid "Configuration and instantiation" msgstr "配置和实例化" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.po index 6e8c32a18a7..3cd7eb7c939 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.po @@ -24,7 +24,6 @@ msgid "tilelink.fabric.Node" msgstr "tilelink.fabric.Node" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:5 -#, fuzzy msgid "" "tilelink.fabric.Node is an additional layer over the regular tilelink " "hardware instantiation which handle negotiation and parameters " @@ -32,7 +31,6 @@ msgid "" msgstr "tilelink.fabric.Node是常规tilelink硬件实例之上的附加层，用于处理SoC级别的协调和参数传递。" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:7 -#, fuzzy msgid "" "It is mostly based on the Fiber API, which allows to create elaboration " "time fibers (user-space threads), allowing to schedule future parameter " @@ -85,16 +83,15 @@ msgid "m2s.parameter : Handle[tilelink.M2sParameter] : The final bus parameter" msgstr "m2s.parameter : Handle[tilelink.M2sParameter]: 最终的总线参数" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:22 -#, fuzzy msgid "" "You can note that they all are Handles. Handle is a way in SpinalHDL to " "share a value between fibers. If a fiber read a Handle while this one has" " no value yet, it will block the execution of that fiber until another " "fiber provide a value to the Handle." -msgstr "您可以注意到它们都是句柄。Handle是SpinalHDL中在纤程之间共享值的一种方式。如果一个纤程读取一个句柄，而这个句柄还没有值，它将阻止该纤程的执行，直到另一个纤程向该句柄提供一个值。" +msgstr "您可以注意到它们都是句柄。Handle是SpinalHDL中在纤程之间共享值的一种方式。" +"如果一个纤程读取一个句柄，而这个句柄还没有值，它将阻塞该纤程的执行，直到另一个纤程向该句柄提供一个值。" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:24 -#, fuzzy msgid "" "There is also a set of attributes like m2s, but reversed (named s2m) " "which specify the parameters for the transactions initiated by the slave " @@ -137,39 +134,36 @@ msgid "Example GpioFiber" msgstr "GPIOFiber示例" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:76 -#, fuzzy msgid "" "``GpioFiber`` is a simple tilelink peripheral which can read / drive a 32" " bits tristate array." -msgstr "GpioFiber是一个简单的tilelink外设，可以读取/驱动32位三态阵列。" +msgstr "``GpioFiber`` 是一个简单的tilelink外设，可以读取/驱动32位三态阵列。" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:121 msgid "Example RamFiber" msgstr "RamFiber示例" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:123 -#, fuzzy msgid "``RamFiber`` is the integration layer of a regular tilelink Ram component." -msgstr "RamFiber是常规tilelink Ram组件的集成层。" +msgstr "``RamFiber`` 是常规tilelink Ram组件的集成层。" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:154 msgid "Example CpuFiber" msgstr "CpuFiber示例" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:156 -#, fuzzy msgid "``CpuFiber`` is an fictive example of a master integration." -msgstr "CpuFiber是一个虚拟的主端集成的示例。" +msgstr "``CpuFiber`` 是一个虚拟的主端集成的示例。" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:204 -#, fuzzy msgid "" "One particularity of Tilelink, is that it assumes a master will not emit " "requests to a unmapped memory space. To allow a master to identify what " "memory access it is allowed to do, you can use the " "``spinal.lib.system.tag.MemoryConnection.getMemoryTransfers`` tool as " "following :" -msgstr "Tilelink的一个特殊性是，它假设主端不会向未映射的内存空间发出请求。为了让主机识别允许访问哪些内存，您可以使用spinal.lib.system.tag.MemoryConnection.getMemoryTransfers工具，如下所示：" +msgstr "Tilelink的一个特性是，它假设主端不会向未映射的内存空间发出请求。" +"为了让主机识别允许访问哪些内存，您可以使用 ``spinal.lib.system.tag.MemoryConnection.getMemoryTransfers`` 工具，如下所示：" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:217 msgid "If you run this in the Cpu's fiber, in the following soc :" @@ -194,7 +188,6 @@ msgid "\"OT\" means OffsetTransformer(offset)" msgstr "\"OT\" 表示OffsetTransformer(offset)" #: ../../SpinalHDL/Libraries/Bus/tilelink/tilelink_fabric.rst:251 -#, fuzzy msgid "" "Note that you can also add PMA (Physical Memory Attributes) to nodes and " "retrieves them via this getMemoryTransfers utilities." diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_device.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_device.po index 1cd953a46cd..561c783f77d 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_device.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_device.po @@ -31,7 +31,6 @@ msgid "Here exists a USB device controller in the SpinalHDL library." msgstr "SpinalHDL库中存在一个USB设备控制器。" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:7 -#, fuzzy msgid "A few bullet points to summarize support:" msgstr "用几个要点总结支持的功能：" @@ -46,12 +45,10 @@ msgid "" msgstr "存储端点状态和事务描述符的内部RAM" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:11 -#, fuzzy msgid "Up to 16 endpoints (for virtually no price)" -msgstr "多达6个端点（几乎没有额外开销）" +msgstr "最多支持16个端点（几乎没有额外开销）" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:12 -#, fuzzy msgid "Support USB host full speed (12 Mbps)" msgstr "支持全速USB主机（12Mbps）" @@ -62,7 +59,6 @@ msgid "" msgstr "在Linux上使用自己的驱动程序进行测试(https://github.com/SpinalHDL/linux/blob/dev/drivers/usb/gadget/udc/spinal_udc.c)" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:14 -#, fuzzy msgid "Bmb memory interface for the configuration" msgstr "用于配置的Bmb内存接口" @@ -249,7 +245,6 @@ msgid "6-0" msgstr "6-0" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:68 -#, fuzzy msgid "" "The device will only listen at tokens with the specified address This " "field is automatically cleared on usb reset events" @@ -278,14 +273,12 @@ msgid "9" msgstr "9" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:73 -#, fuzzy msgid "" "Set the enable (see above) on the next EP0 IN token completion Cleared by" " the hardware after any EP0 completion" msgstr "在下一个EP0 IN令牌完成时置位enable（见上文），在任何EP0完成后由硬件清零" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:77 -#, fuzzy msgid "" "The idea here is to keep the whole register cleared until a USB " "SET_ADDRESS setup packet is received on EP0. At that moment, you can set " @@ -294,8 +287,9 @@ msgid "" "will then automatically turn on the address filtering at the completion " "of that descriptor." msgstr "" -"这里的想法是在EP0上收到USB " -"SET_ADDRESS的设置(setup)数据包前，保持整个寄存器清零。此时，您可以设置地址和触发字段，然后向EP0提供IN零长度描述符以完成SET_ADDRESS序列。控制器将在该描述符完成时自动打开地址过滤。" +"这里的想法是，在EP0上收到USB " +"SET_ADDRESS的设置(setup)数据包前，保持整个寄存器清零。" +"此时，您可以设置地址和触发字段，然后向EP0提供IN零长度描述符以完成SET_ADDRESS序列。控制器将在该描述符完成时自动打开地址过滤。" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:82 msgid "INTERRUPT (0xFF08)" @@ -522,7 +516,6 @@ msgid "ENDPOINTS (0x0000 - 0x003F)" msgstr "端点ENDPOINTS (0x0000 - 0x003F)" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:147 -#, fuzzy msgid "" "The endpoints status are stored at the beginning of the internal ram over" " one 32 bits word each." @@ -539,7 +532,6 @@ msgid "RW" msgstr "RW" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:152 -#, fuzzy msgid "If not set, the endpoint will ignore all the traffic" msgstr "如果不设置，端点将忽略所有流量" @@ -741,7 +733,6 @@ msgid "" msgstr "请注意，如果控制器接收到IN/OUT与描述符IN/OUT不匹配的帧，那么该帧将被忽略。" #: ../../SpinalHDL/Libraries/Com/usb_device.rst:220 -#, fuzzy msgid "Also, to initialize a descriptor, the CPU should set the code field to 0xF" msgstr "此外，要初始化描述符，CPU应将代码字段设置为0xF" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_ohci.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_ohci.po index c5d365d3c5c..b74f33a7bc5 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_ohci.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Com/usb_ohci.po @@ -31,7 +31,6 @@ msgid "Here exists a USB OHCi controller (host) in the SpinalHDL library." msgstr "SpinalHDL库中有USB OHCi控制器（主机）。" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:7 -#, fuzzy msgid "A few bullet points to summarize support:" msgstr "用几个要点总结支持的功能：" @@ -48,7 +47,6 @@ msgid "" msgstr "它已经与上游的linux/uboot OHCI驱动兼容。（tinyUSB上也有OHCI驱动）" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:11 -#, fuzzy msgid "" "This provides USB host full speed and low speed capabilities (12 Mbps and" " 1.5 Mbps)" @@ -67,7 +65,6 @@ msgid "Bmb memory interface for DMA accesses" msgstr "用于DMA访问的Bmb存储器接口" #: ../../SpinalHDL/Libraries/Com/usb_ohci.rst:15 -#, fuzzy msgid "Bmb memory interface for the configuration" msgstr "用于配置的Bmb内存接口" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/EDA/altera/qsysify.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/EDA/altera/qsysify.po index f05ca62030d..ddf78156e30 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/EDA/altera/qsysify.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/EDA/altera/qsysify.po @@ -27,7 +27,6 @@ msgid "QSysify" msgstr "QSysify" #: ../../SpinalHDL/Libraries/EDA/altera/qsysify.rst:5 -#, fuzzy msgid "" "QSysify is a tool which is able to generate a QSys IP (tcl script) from a" " SpinalHDL component by analyzing its IO definition. It currently " diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.po index e3b8330ae95..cdd949d2bb7 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/PLIC/plic_mapper.po @@ -102,19 +102,16 @@ msgid "" msgstr "此映射生成更轻量级的PLIC，但代价是缺少一些可选特性：" #: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:36 -#, fuzzy msgid "not reading the interrupt's priority" msgstr "不读取中断优先级" #: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:37 -#, fuzzy msgid "" "not reading the interrupt's pending bit (must use the claim/complete " "mechanism)" msgstr "不读取中断的挂起位（必须使用声明(claim)/完成(complete)机制）" #: ../../SpinalHDL/Libraries/Misc/PLIC/plic_mapper.rst:38 -#, fuzzy msgid "not reading the target's threshold" msgstr "不读取目标的阈值" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/Plru.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/Plru.po index e1d207cd075..ba5b1099fd8 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/Plru.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/Misc/Plru.po @@ -3,14 +3,13 @@ # This file is distributed under the same license as the SpinalHDL package. # FIRST AUTHOR , 2025. # -#, fuzzy msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" "POT-Creation-Date: 2026-02-11 09:50+0000\n" -"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" -"Last-Translator: FULL NAME \n" +"PO-Revision-Date: 2026-02-11 21:51+0800\n" +"Last-Translator: CatalpaEel\n" "Language: zh_CN\n" "Language-Team: zh_CN \n" "Plural-Forms: nplurals=1; plural=0;\n" @@ -21,49 +20,49 @@ msgstr "" #: ../../SpinalHDL/Libraries/Misc/Plru.rst:5 msgid "Plru" -msgstr "" +msgstr "伪最近最少使用逻辑（Plru）" #: ../../SpinalHDL/Libraries/Misc/Plru.rst:8 msgid "Introduction" -msgstr "" +msgstr "简介" #: ../../SpinalHDL/Libraries/Misc/Plru.rst:9 msgid "Pseudo least recently used combinatorial logic" -msgstr "" +msgstr "伪最近最少使用组合逻辑" #: ../../SpinalHDL/Libraries/Misc/Plru.rst:10 msgid "io.context.state need to be handled externally." -msgstr "" +msgstr "io.context.state 需由外部逻辑处理。" #: ../../SpinalHDL/Libraries/Misc/Plru.rst:11 msgid "" "When you want to specify a access to a entry, you can use the io.update " "interface to get the new state value." -msgstr "" +msgstr "当需要指定对某表项的访问时，可通过 io.update 接口获取新的状态值。" #: ../../SpinalHDL/Libraries/Misc/Plru.rst:12 msgid "plru.io.evict.id tells you the id of the next block to be evicted" -msgstr "" +msgstr "plru.io.evict.id 指示下一个将被淘汰的块 ID" #: ../../SpinalHDL/Libraries/Misc/Plru.rst:13 msgid "plru.io.update.id lets you update what you recently used" -msgstr "" +msgstr "plru.io.update.id 用于更新最近使用的表项" #: ../../SpinalHDL/Libraries/Misc/Plru.rst:16 msgid "PLRU Code" -msgstr "" +msgstr "伪LRU 代码" #: ../../SpinalHDL/Libraries/Misc/Plru.rst:40 msgid "Example usage in a cache" -msgstr "" +msgstr "缓存中使用示例" #: ../../SpinalHDL/Libraries/Misc/Plru.rst:54 msgid "Get the ID of the way to evict from" -msgstr "" +msgstr "获取待淘汰路（way）的ID" #: ../../SpinalHDL/Libraries/Misc/Plru.rst:60 msgid "Update recently used way" -msgstr "" +msgstr "更新最近使用的路" #~ msgid "io.context.state need to be handled externaly." #~ msgstr "" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fiber.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fiber.po index 00a4657ac69..baa356ece74 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fiber.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/fiber.po @@ -27,20 +27,18 @@ msgid "Fiber framework" msgstr "纤程框架" #: ../../SpinalHDL/Libraries/fiber.rst:10 -#, fuzzy msgid "" "This framework is not expected to be used for general RTL generation and " "targets large system design management and code generation. It is " "currently used as toplevel integration tool in SaxonSoC and VexiiRiscv." -msgstr "该框架设计目标不是用于一般 RTL 生成，而是针对大型系统设计管理和代码生成。它目前在 SaxonSoC 中用作顶级集成工具。" +msgstr "该框架设计目标不是用于一般 RTL 生成，而是针对大型系统设计管理和代码生成。" +"它目前在 SaxonSoC 和 VexiiRiscv 中用作顶级集成工具。" #: ../../SpinalHDL/Libraries/fiber.rst:14 -#, fuzzy msgid "Currently in development." msgstr "目前正在开发中。" #: ../../SpinalHDL/Libraries/fiber.rst:16 -#, fuzzy msgid "" "Fiber is a framework to run the hardware elaboration in an out of order " "manner, a bit similarly to Makefile, where you can define rules and " @@ -57,7 +55,6 @@ msgid "" msgstr "使用这个框架可能会使简单的事情复杂化，但为复杂的情况提供了一些强大的功能：" #: ../../SpinalHDL/Libraries/fiber.rst:22 -#, fuzzy msgid "" "You can define things before even knowing all their requirements, for " "example : instantiating an interruption controller, before knowing how " @@ -65,19 +62,17 @@ msgid "" msgstr "您甚至可以在知道所有要求之前就定义事物，例如：在知道需要多少中断信号线之前实例化中断控制器" #: ../../SpinalHDL/Libraries/fiber.rst:24 -#, fuzzy msgid "" "Abstract/lazy/partial SoC architecture definition allowing the creation " "of SoC template for further specializations" -msgstr "抽象/懒惰化/部分化SoC架构定义，允许创建SoC模板以供进一步专门化" +msgstr "抽象/延迟/部分SoC架构定义，允许创建SoC模板以供进一步专门化" #: ../../SpinalHDL/Libraries/fiber.rst:26 -#, fuzzy msgid "" "Automatic requirement negotiation between multiple agents in a " "decentralized way, for example : between masters and slaves of a memory " "bus" -msgstr "以分散方式在多个代理之间自动进行需求协商，例如：内存总线的主设备和从设备之间" +msgstr "以去中心化方式在多个代理之间自动进行需求协商，例如：内存总线的主设备和从设备之间" #: ../../SpinalHDL/Libraries/fiber.rst:29 msgid "The framework is mainly composed of :" @@ -88,11 +83,10 @@ msgid "``Handle[T]``, which can be used later to store a value of type ``T``." msgstr "``Handle[T]``，稍后可用于存储 ``T`` 类型的值。" #: ../../SpinalHDL/Libraries/fiber.rst:32 -#, fuzzy msgid "" "``handle.load``, which allow to set the value of a handle (will " "reschedule all tasks waiting on it)" -msgstr "``handle.load`` 允许设置句柄的值（将启动等待它的所有任务）" +msgstr "``handle.load`` 允许设置句柄的值（将重新调度所有等待它的任务）" #: ../../SpinalHDL/Libraries/fiber.rst:33 msgid "" @@ -118,7 +112,6 @@ msgid "Simple dummy example" msgstr "简单的示例" #: ../../SpinalHDL/Libraries/fiber.rst:44 -#, fuzzy msgid "Here is a simple example :" msgstr "这是一个简单的例子：" @@ -180,7 +173,6 @@ msgid "soon(handle)" msgstr "soon(handle)" #: ../../SpinalHDL/Libraries/fiber.rst:104 -#, fuzzy msgid "" "In order to maintain a proper graph of dependencies between tasks and " "Handle, a task can specify in advance that it will load a given handle. " diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/flow.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/flow.po index 416a4718a98..8df50cf377d 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/flow.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/flow.po @@ -132,7 +132,6 @@ msgid "x.m2sPipe()" msgstr "x.m2sPipe()" #: ../../SpinalHDL/Libraries/flow.rst -#, fuzzy msgid "Return a Flow driven by x" msgstr "返回一个由 x 驱动的流" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/index.po index 4afb32de000..b70713b4bd6 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/index.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/index.po @@ -53,7 +53,6 @@ msgid "Provide some example to get the spirit of spinal" msgstr "提供一些例子以理解spinal的精髓" #: ../../SpinalHDL/Libraries/index.rst:14 -#, fuzzy msgid "Provide some tools and facilities (latency analyzer, QSys converter, ...)" msgstr "提供一些工具和功能（延迟分析器、QSys转换器……）" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/logic.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/logic.po index e02da7c8183..81537d99f39 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/logic.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/logic.po @@ -3,14 +3,13 @@ # This file is distributed under the same license as the SpinalHDL package. # FIRST AUTHOR , 2025. # -#, fuzzy msgid "" msgstr "" "Project-Id-Version: SpinalHDL \n" "Report-Msgid-Bugs-To: \n" "POT-Creation-Date: 2026-02-11 09:50+0000\n" -"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" -"Last-Translator: FULL NAME \n" +"PO-Revision-Date: 2026-02-11 22:06+0800\n" +"Last-Translator: CatalpaEel\n" "Language: zh_CN\n" "Language-Team: zh_CN \n" "Plural-Forms: nplurals=1; plural=0;\n" @@ -21,7 +20,7 @@ msgstr "" #: ../../SpinalHDL/Libraries/logic.rst:2 msgid "Logic Simplification Utilities and Decoder" -msgstr "" +msgstr "逻辑化简工具与解码器" #: ../../SpinalHDL/Libraries/logic.rst:4 #, python-format @@ -29,80 +28,82 @@ msgid "" "A minimal Boolean simplification and decode-table utility for decoders " "using the `Quine–McCluskey algorithm " "`_." -msgstr "" +msgstr "一个基于 `奎因-麦克拉斯基算法 `._ " +"的最小化布尔化简与解码表生成工具。" #: ../../SpinalHDL/Libraries/logic.rst:7 msgid "" "Provides masked pattern matching, Quine–McCluskey style logic reduction, " "and a high-level decode-table builder." -msgstr "" +msgstr "提供掩码模式匹配、奎因-麦克拉斯基式逻辑化简以及高层级解码表构建器。" #: ../../SpinalHDL/Libraries/logic.rst:11 msgid "`Masked`" -msgstr "" +msgstr "掩码模式" #: ../../SpinalHDL/Libraries/logic.rst:13 msgid "" "Represents a bit pattern with care (significant) and don't-care bits. - " "`value` = bit values - `care` = which bits must match (1 = match, 0 = " "don't care)" -msgstr "" +msgstr "表示具有有效位与无关位的比特模式。- `value` = 比特值 - `care` = 需匹配的位掩码（1=需匹配，0=无关）" #: ../../SpinalHDL/Libraries/logic.rst:17 #: ../../SpinalHDL/Libraries/logic.rst:47 msgid "Example:" -msgstr "" +msgstr "示例：" #: ../../SpinalHDL/Libraries/logic.rst:25 msgid "e.g RISC-V instructions:" -msgstr "" +msgstr "例如 RISC-V 指令：" #: ../../SpinalHDL/Libraries/logic.rst:32 msgid "Used to define instruction encodings for decode tables." -msgstr "" +msgstr "用于定义解码表的指令编码。" #: ../../SpinalHDL/Libraries/logic.rst:35 msgid "`DecodingSpec`" -msgstr "" +msgstr "解码规格" #: ../../SpinalHDL/Libraries/logic.rst:37 msgid "High-level builder for decode tables using `Masked` patterns." -msgstr "" +msgstr "基于 `Masked` 模式的高层级解码表构建器。" #: ../../SpinalHDL/Libraries/logic.rst:43 msgid "Methods:" -msgstr "" +msgstr "方法：" #: ../../SpinalHDL/Libraries/logic.rst:40 msgid "`addNeeds(key : Masked, value : Masked)`" -msgstr "" +msgstr "`addNeeds(key : Masked, value : Masked)`" #: ../../SpinalHDL/Libraries/logic.rst:41 msgid "`addNeeds(keys : Seq[Masked], value : Masked)`" -msgstr "" +msgstr "`addNeeds(keys : Seq[Masked], value : Masked)`" #: ../../SpinalHDL/Libraries/logic.rst:42 msgid "`build(sel, coverAll)`" -msgstr "" +msgstr "`build(sel, coverAll)`" #: ../../SpinalHDL/Libraries/logic.rst:43 msgid "`setDefault(value : Masked)`" -msgstr "" +msgstr "`setDefault(value : Masked)`" #: ../../SpinalHDL/Libraries/logic.rst:45 msgid "This generate simplified decode logic." -msgstr "" +msgstr "该方法生成化简后的解码逻辑。" #: ../../SpinalHDL/Libraries/logic.rst:56 msgid "Generates minimized combinational decode logic." -msgstr "" +msgstr "生成最小化的组合解码逻辑。" #: ../../SpinalHDL/Libraries/logic.rst:58 msgid "" "The practical use is to define bit patterns as `Masked` and feed them " "into `DecodingSpec` to build compact decode logic (e.g., RISC-V). The " "output hardware is then minimized (fewer LUTs / simpler gates)." -msgstr "" +msgstr "实际应用中，先将比特模式定义为 `Masked`，再将其送入 `DecodingSpec` " +"以构建紧凑的解码逻辑（例如 RISC-V）。最终生成的硬件经过最小化优化（占用更少的查找表、逻辑门更简洁）。" #~ msgid "" #~ "A minimal Boolean simplification and " diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/regIf.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/regIf.po index 9fecc63c4e2..9ac90495c34 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/regIf.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/regIf.po @@ -567,7 +567,6 @@ msgid "example1: clock gate software enable" msgstr "示例1：时钟门软件使能" #: ../../SpinalHDL/Libraries/regIf.rst:262 -#, fuzzy msgid "example2: interrupt raw reg with force interface for software" msgstr "示例2：使用软件的带强制(force)接口的中断原始(raw)状态寄存器" @@ -651,9 +650,8 @@ msgstr "MASK" #: ../../SpinalHDL/Libraries/regIf.rst:414 #: ../../SpinalHDL/Libraries/regIf.rst:433 -#, fuzzy msgid "int mask register, 1: off; 0: open; default 1 int off" -msgstr "中断掩码寄存器，1：关闭；0：打开；默认1 中断关闭" +msgstr "中断掩码寄存器，1：关闭；0：打开；默认 1 中断关闭" #: ../../SpinalHDL/Libraries/regIf.rst:415 #: ../../SpinalHDL/Libraries/regIf.rst:434 @@ -747,7 +745,6 @@ msgstr "" "triggers: Bool*)``" #: ../../SpinalHDL/Libraries/regIf.rst:457 -#, fuzzy msgid "create RAW/FORCE/MASK(SET/CLR)/STATUS for pulse event at addrOffset" msgstr "在addrOffset处为脉冲事件创建RAW/FORCE/MASK(SET/CLR)/STATUS" @@ -760,7 +757,6 @@ msgstr "" "String, levels: Bool*)``" #: ../../SpinalHDL/Libraries/regIf.rst:458 -#, fuzzy msgid "create RAW/FORCE/MASK(SET/CLR)/STATUS for level event at addrOffset" msgstr "在addrOffset处为电平事件创建RAW/FORCE/MASK(SET/CLR)/STATUS" @@ -784,7 +780,6 @@ msgid "Developers Area" msgstr "开发者区域" #: ../../SpinalHDL/Libraries/regIf.rst:516 -#, fuzzy msgid "You can add your document Type by extending the `BusIfVisitor` Trait" msgstr "您可以通过扩展 `BusIfVistor` 特征来添加文档类型" @@ -794,9 +789,8 @@ msgid "``case class Latex(fileName : String) extends BusIfVisitor{ ... }``" msgstr "``case class Latex(fileName : String) extends BusIfVisitor{ ... }``" #: ../../SpinalHDL/Libraries/regIf.rst:520 -#, fuzzy msgid "BusIfVisitor give access BusIf.RegInsts to do what you want" -msgstr "BusIfVistor给予访问BusIf.RegInsts的权限来执行您想要的操作" +msgstr "BusIfVisitor 给予访问 BusIf.RegInsts 的权限来执行您想要的操作" #~ msgid "Interrupt Design Spec" #~ msgstr "中断设计规范" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/stream.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/stream.po index 14ffdf7be3f..77de7cae28a 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/stream.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/stream.po @@ -11,8 +11,8 @@ msgstr "" "Language-Team:LANGUAGE MIME-Version:1.0Content-" "Type:text/plain; charset=UTF-8\n" "POT-Creation-Date: 2025-05-01 09:36+0000\n" -"PO-Revision-Date: 2024-06-15 00:17+0000\n" -"Last-Translator: Readon \n" +"PO-Revision-Date: 2026-02-11 22:17+0800\n" +"Last-Translator: CatalpaEel\n" "Language: zh_CN\n" "Language-Team: Chinese (Simplified) \n" @@ -162,13 +162,12 @@ msgid "When manually reading/driving the signals of a Stream keep in mind that:" msgstr "当手动读取/驱动反压流的信号时，请记住：" #: ../../SpinalHDL/Libraries/stream.rst:82 -#, fuzzy msgid "" "After being asserted, ``valid`` may only be deasserted once the current " "payload was acknowledged. This means ``valid`` can only toggle to 0 the " "cycle after a the slave did a read by asserting ``ready``." msgstr "" -"当 ``valid`` 被置为有效后，它只有在当前负载被使用后才能被置为无效。这意味着 ``valid`` 只能在从端通过置高 ``ready``" +"当 ``valid`` 被置为有效后，它只有在当前负载被确认后才能被置为无效。这意味着 ``valid`` 只能在从端通过置高 ``ready``" " 完成一次读取后的下一个周期，才可以切换到0。" #: ../../SpinalHDL/Libraries/stream.rst:83 @@ -261,9 +260,8 @@ msgid "Return True when a transaction is stall on the bus (valid && ! ready)" msgstr "当总线上的传输停滞时返回True(valid && ! ready)" #: ../../SpinalHDL/Libraries/stream.rst:116 -#, fuzzy msgid "x.isFree" -msgstr "x.fire" +msgstr "x.isFree" #: ../../SpinalHDL/Libraries/stream.rst:117 msgid "Return True when the bus isn't stuck with a transaction (!isStall)" @@ -290,7 +288,6 @@ msgid "x.stage()" msgstr "x.stage()" #: ../../SpinalHDL/Libraries/stream.rst -#, fuzzy msgid "Return a Stream driven by x" msgstr "返回由x驱动的Stream反压流" @@ -299,9 +296,8 @@ msgid "through a register stage that cut valid/payload paths" msgstr "通过寄存器，切断valid/payload路径" #: ../../SpinalHDL/Libraries/stream.rst -#, fuzzy msgid "Cost = (payload width + 1) flip-flops" -msgstr "Cost = (payload width + 1) 触发器" +msgstr "开销 = (负载位宽 + 1) 个触发器" #: ../../SpinalHDL/Libraries/stream.rst:130 #: ../../SpinalHDL/Libraries/stream.rst:142 @@ -319,9 +315,8 @@ msgid "ready paths is cut by a register stage" msgstr "通过寄存器级断开ready路径" #: ../../SpinalHDL/Libraries/stream.rst -#, fuzzy msgid "Cost = payload width * (mux2 + 1 flip-flops)" -msgstr "Cost = payload width * (mux2 + 1 flip flop)" +msgstr "开销 = 负载位宽 * (2选1选择器 + 1 个触发器)" #: ../../SpinalHDL/Libraries/stream.rst:136 #: ../../SpinalHDL/Libraries/stream.rst:147 @@ -342,9 +337,8 @@ msgid "valid/ready/payload paths are cut by some register" msgstr "valid/ready/payload路径通过一些寄存器分割" #: ../../SpinalHDL/Libraries/stream.rst -#, fuzzy msgid "Cost = (payload width + 2) flip-flops, bandwidth divided by two" -msgstr "成本 = (payload位宽 + 2)个触发器，带宽除以二" +msgstr "开销 = (负载位宽 + 2) 个触发器，带宽除以二" #: ../../SpinalHDL/Libraries/stream.rst msgid "x << y" @@ -475,9 +469,8 @@ msgstr "" #: ../../SpinalHDL/Libraries/stream.rst:233 #: ../../SpinalHDL/Libraries/stream.rst:249 -#, fuzzy msgid "Name" -msgstr "io名称" +msgstr "名称" #: ../../SpinalHDL/Libraries/stream.rst:236 #: ../../SpinalHDL/Libraries/stream.rst:316 @@ -559,9 +552,8 @@ msgid "Use an ``Vec`` of register instead of a Mem to store the content" msgstr "" #: ../../SpinalHDL/Libraries/stream.rst:264 -#, fuzzy msgid "initPayload" -msgstr "payload" +msgstr "initPayload" #: ../../SpinalHDL/Libraries/stream.rst:265 msgid "``None``" @@ -809,7 +801,6 @@ msgid "sequentialOrder" msgstr "sequentialOrder" #: ../../SpinalHDL/Libraries/stream.rst -#, fuzzy msgid "Could be used to retrieve transaction in a sequential order" msgstr "可用于按顺序遍历任务" @@ -882,7 +873,6 @@ msgid "StreamFork" msgstr "StreamFork" #: ../../SpinalHDL/Libraries/stream.rst:514 -#, fuzzy msgid "" "A StreamFork will clone each incoming data to all its output streams. If " "synchronous is true, all output streams will always fire together, which " @@ -890,7 +880,10 @@ msgid "" "synchronous is false, output streams may be ready one at a time, at the " "cost of an additional flip-flop (1 bit per output). The input stream will" " block until all output streams have processed each item regardlessly." -msgstr "StreamFork会将每个传入数据克隆到其所有输出流。如果synchronous为true，则所有输出流将始终一起触发，这意味着直到所有输出流准备就绪前该流将都将暂停。如果synchronous为false，那么一次可能只有一个输出流准备就绪，但需要一个额外的触发器（每个输出1位）。直到所有输出流都处理完每个项目前，输入流将阻塞。" +msgstr "StreamFork会将每个传入数据克隆到其所有输出流。" +"如果synchronous为true，则所有输出流将始终一起触发，这意味着直到所有输出流准备就绪前该流将都将暂停。" +"如果synchronous为false，那么一次可能只有一个输出流准备就绪，但需要一个额外的触发器（每路输出1位）。" +"无论采用何种模式，输入流都将阻塞，直至所有输出流完成对每个数据项的处理。" #: ../../SpinalHDL/Libraries/stream.rst:526 msgid "or" @@ -961,7 +954,6 @@ msgstr "" "次到输出传输的功能。每当为单个负载而触发inputStream时，都会捕获并寄存 ``count`` 。" #: ../../SpinalHDL/Libraries/stream.rst:597 -#, fuzzy msgid "" "This ``extender`` provides several status signals, such as ``working``, " "``last``, ``done`` where ``working`` means there is one input transfer " @@ -971,8 +963,8 @@ msgid "" "process complete and ready to start another transaction." msgstr "" "该 ``extender`` 提供了多种状态信号，例如 ``working`` 、 ``last`` 、``done`` ，其中 " -"``working`` 表示有一个输入传输已接受并正在进行中， ``last`` 表示最后一个输出传输已准备好并等待完成，``done`` " -"变为有效表示最后一个输出传输正在触发，并使当前输入传输任务处理完成且准备好启动另一个传输。" +"``working`` 表示有一个输入传输已接受并正在进行中， ``last`` 表示最后一个输出传输已就绪并等待完成，``done`` " +"变为有效表示最后一个输出传输正在触发，标志着当前输入事务处理完成，并可开始新的事务。" #: ../../SpinalHDL/Libraries/stream.rst:618 msgid "" @@ -1018,9 +1010,8 @@ msgid "" msgstr "Testbench中主端通过调用函数来应用值（如果可用）以驱动值。如果值可用，则函数必须返回。支持随机的延迟。" #: ../../SpinalHDL/Libraries/stream.rst:635 -#, fuzzy msgid "StreamReadyRandomizer" -msgstr "StreamReadyRandmizer" +msgstr "StreamReadyRandomizer" #: ../../SpinalHDL/Libraries/stream.rst:636 msgid "Randomizes ``ready`` for reception of data, testbench is the slave side." diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/utils.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/utils.po index b06799cff79..a99083495fb 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/utils.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Libraries/utils.po @@ -314,11 +314,10 @@ msgid "BufferCC(input : T)" msgstr "BufferCC(input : T)" #: ../../SpinalHDL/Libraries/utils.rst:111 -#, fuzzy msgid "" "Return the input signal synchronized with the current clock domain by " "using 2 flip-flops" -msgstr "返回利用两个触发器同步到当前时钟域的同步输入信号" +msgstr "通过两级触发器将输入信号同步至当前时钟域后返回" #: ../../SpinalHDL/Libraries/utils.rst:115 msgid "Counter" @@ -367,7 +366,6 @@ msgid "Starts at zero and ends at ``(1 << bitCount) - 1``" msgstr "从0开始到 ``(1 << bitCount) - 1`` 结束" #: ../../SpinalHDL/Libraries/utils.rst:134 -#, fuzzy msgid "A counter can be controlled by methods, and signals can be read:" msgstr "计数器可以通过方法控制，并且可以连线可以被读取：" @@ -444,15 +442,14 @@ msgid "asyncAssertSyncDeassert" msgstr "asyncAssertSyncDeassert" #: ../../SpinalHDL/Libraries/utils.rst:196 -#, fuzzy msgid "" "You can filter an asynchronous reset by using an asynchronously asserted " "synchronously deasserted logic. To do it you can use the " "``ResetCtrl.asyncAssertSyncDeassert`` function which will return you the " "filtered value." msgstr "" -"您可以使用“异步有效同步无效”的逻辑来构造异步复位。为此，可以使用 ``ResetCtrl.asyncAssertSyncDeassert`` " -"函数返回构造的复位信号。" +"您可以使用异步置位、同步复位的逻辑来构造异步复位。为此，可以使用 ``ResetCtrl.asyncAssertSyncDeassert`` " +"函数，该函数将返回过滤后的值。" #: ../../SpinalHDL/Libraries/utils.rst:202 msgid "Argument name" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/report.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/report.po index d683e01acbd..c6077e1f7f6 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/report.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/report.po @@ -36,11 +36,10 @@ msgid "Since SpinalHDL 1.4.4, the following syntax is also supported:" msgstr "从 SpinalHDL 1.4.4 开始，还支持以下语法：" #: ../../SpinalHDL/Other features/report.rst:33 language -#, fuzzy msgid "" "You can display the current simulation time using the `REPORT_TIME` " "object:" -msgstr "可以使用 REPORT_TIME 对象显示当前仿真时间" +msgstr "可以使用 REPORT_TIME 对象显示当前仿真时间：" #: ../../SpinalHDL/Other features/report.rst:39 language msgid "will result in:" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/scope_property.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/scope_property.po index 835b31b9478..8e2a3dc2fc1 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/scope_property.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/scope_property.po @@ -41,7 +41,6 @@ msgid "" msgstr "换句话说，它是全局变量、scala 隐式变量、线程本地变量（ThreadLocal） 的替代品。" #: ../../SpinalHDL/Other features/scope_property.rst:10 language -#, fuzzy msgid "" "To compare with global variable, It allow to run multiple thread running " "the same code independently" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/stub.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/stub.po index 7068b19fe18..5a3d1d8bb07 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/stub.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/stub.po @@ -51,7 +51,6 @@ msgid "then remove all children component" msgstr "然后删除所有子组件" #: ../../SpinalHDL/Other features/stub.rst:53 language -#, fuzzy msgid "then remove all assignment and logic we don't want" msgstr "然后删除我们不需要的所有赋值和逻辑" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/utils.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/utils.po index 344f0be4914..d61b339ee07 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/utils.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/utils.po @@ -111,7 +111,6 @@ msgid "``Cat(x: Iterable[Data])``" msgstr "``Cat(x: Iterable[Data])``" #: ../../SpinalHDL/Other features/utils.rst:35 language -#, fuzzy msgid "Concatenate arguments, from LSB to MSB, see `Cat`_" msgstr "连接参数, 从 LSB 到 MSB, 参见 `Cat`_" @@ -156,7 +155,6 @@ msgstr "" "将索引 0 放置在 LSB 处。" #: ../../SpinalHDL/Other features/utils.rst:65 language -#, fuzzy msgid "Cloning hardware data types" msgstr "克隆硬件数据类型" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/vhdl_generation.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/vhdl_generation.po index e80dfc2e33e..3fea88d6066 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/vhdl_generation.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Other language features/vhdl_generation.po @@ -8,8 +8,8 @@ msgstr "" "Type:text/plain; charset=UTF-8\n" "Report-Msgid-Bugs-To: EMAIL@ADDRESS\n" "POT-Creation-Date: 2026-02-11 09:50+0000\n" -"PO-Revision-Date: 2024-01-13 05:06+0000\n" -"Last-Translator: tsy0123 <675526215@qq.com>\n" +"PO-Revision-Date: 2026-02-11 22:31+0800\n" +"Last-Translator: CatalpaEel\n" "Language: zh_CN\n" "Language-Team: Chinese (Simplified) " @@ -207,206 +207,207 @@ msgstr "生成文件的目录。" #: ../../SpinalHDL/Other features/vhdl_generation.rst:84 language msgid "``oneFilePerComponent``" -msgstr "" +msgstr "``oneFilePerComponent``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:87 language msgid "" "Instead of generating one big VHDL/Verilog file, every component will get" " its own VHDL/Verilog file." -msgstr "" +msgstr "不为每个组件生成单一的 VHDL/Verilog 大文件，而是为每个组件分别生成独立的 VHDL/Verilog 文件。" #: ../../SpinalHDL/Other features/vhdl_generation.rst:88 language msgid "``netlistFileName``" -msgstr "" +msgstr "``netlistFileName``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:90 language msgid "ToplevelClassName.(vhd|v)" -msgstr "" +msgstr "顶层类名.(vhd|v)" #: ../../SpinalHDL/Other features/vhdl_generation.rst:91 language msgid "Allow to change the name of the generated VHDL/Verilog." -msgstr "" +msgstr "允许更改生成的 VHDL/Verilog 文件名。" #: ../../SpinalHDL/Other features/vhdl_generation.rst:92 language msgid "``globalPrefix``" -msgstr "" +msgstr "``globalPrefix``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:94 language msgid "\"\"" -msgstr "" +msgstr "\"\"" #: ../../SpinalHDL/Other features/vhdl_generation.rst:95 language msgid "" "Will add the given prefix in the front of every global symbols in the " "VHDL/Verilog (components/modules/enums). This allows to avoid naming " "conflict between multiple generated file." -msgstr "" +msgstr "在 VHDL/Verilog 中所有全局符号（组件/模块/枚举）前添加指定前缀。" +"这有助于避免多个生成文件之间的命名冲突。" #: ../../SpinalHDL/Other features/vhdl_generation.rst:96 language msgid "``privateNamespace``" -msgstr "" +msgstr "``privateNamespace``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:99 language msgid "" "Every generated Component/Modules names will get prefixed with the " "toplevel Component/Module name (excepted for the toplevel). This allows " "to avoid naming conflict between multiple generated file." -msgstr "" +msgstr "所有生成的组件/模块名称（顶层除外）都将以顶层组件/模块名为前缀。" +"这有助于避免多个生成文件之间的命名冲突。" #: ../../SpinalHDL/Other features/vhdl_generation.rst:100 language msgid "``formalAsserts``" -msgstr "" +msgstr "``formalAsserts``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:103 language msgid "Enable the generation of the formal assertions in the VHDL/Verilog." -msgstr "" +msgstr "启用 VHDL/Verilog 中形式化断言的生成。" #: ../../SpinalHDL/Other features/vhdl_generation.rst:104 language msgid "``anonymSignalPrefix``" -msgstr "" +msgstr "``anonymSignalPrefix``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:106 language msgid "\"zz\\_\"" -msgstr "" +msgstr "\"zz\\_\"" #: ../../SpinalHDL/Other features/vhdl_generation.rst:107 language msgid "Set the prefix added to unnamed signals." -msgstr "" +msgstr "设置添加到未命名信号的前缀。" #: ../../SpinalHDL/Other features/vhdl_generation.rst:108 language msgid "``inlineRom``" -msgstr "" +msgstr "``inlineRom``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:111 language msgid "" "Configure the Verilog backend to incorporate the ROM values " "initialization in the verilog itself instead of an bin file." -msgstr "" +msgstr "配置 Verilog 后端，将 ROM 初始化值内嵌于 Verilog 代码中，而非生成独立的二进制文件。" #: ../../SpinalHDL/Other features/vhdl_generation.rst:112 language msgid "``caseRom``" -msgstr "" +msgstr "``caseRom``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:115 language msgid "Generate the ROM as a big switch case." -msgstr "" +msgstr "以大型 switch case 语句形式生成 ROM。" #: ../../SpinalHDL/Other features/vhdl_generation.rst:116 language msgid "``mergeAsyncProcess``" -msgstr "" +msgstr "``mergeAsyncProcess``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:119 language msgid "" "Will merge process/always blocks for combinatorial signal which share at " "least one conditional assignment (if/switch statement)" -msgstr "" +msgstr "合并至少共享一个条件赋值（if/switch 语句）的组合逻辑信号的 process/always 块。" #: ../../SpinalHDL/Other features/vhdl_generation.rst:120 language msgid "``mergeSyncProcess``" -msgstr "" +msgstr "``mergeSyncProcess``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:122 #: features/vhdl_generation.rst:138 language msgid "true" -msgstr "" +msgstr "true" #: ../../SpinalHDL/Other features/vhdl_generation.rst:123 language msgid "" "Will merge process/always blocks for flip-flops which use the same clock " "domain (if/switch statement)" -msgstr "" +msgstr "合并使用相同时钟域的触发器（flip-flop）的 process/always 块（if/switch 语句）。" #: ../../SpinalHDL/Other features/vhdl_generation.rst:124 language msgid "``genLineComments``" -msgstr "" +msgstr "``genLineComments``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:127 language msgid "" "For each hardware assignment in the generated VHDL/Verilog code, will " "attach a comment which specifies in which scala file, at which line, the " "assignment happened. Ex : a = 1'b1; // @ MyDesign.scala l1135" -msgstr "" +msgstr "为生成的 VHDL/Verilog 代码中的每项硬件赋值附加注释，标明该赋值所在的 Scala 文件及行号。" +"例如：a = 1'b1; // @ MyDesign.scala l1135" #: ../../SpinalHDL/Other features/vhdl_generation.rst:128 language -#, fuzzy msgid "``noAssert``" -msgstr "``mode``" +msgstr "``noAssert``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:131 language msgid "Remove all the asserts from the generated code" -msgstr "" +msgstr "从生成的代码中移除所有断言" #: ../../SpinalHDL/Other features/vhdl_generation.rst:132 language msgid "``headerWithDate``" -msgstr "" +msgstr "``headerWithDate``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:135 language msgid "Add the date at which the VHDL/Verilog was generated in its header." -msgstr "" +msgstr "在 VHDL/Verilog 文件头中添加生成日期。" #: ../../SpinalHDL/Other features/vhdl_generation.rst:136 language msgid "``headerWithRepoHash``" -msgstr "" +msgstr "``headerWithRepoHash``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:139 language msgid "Add the current directory git hash in the generated VHDL/Verilog header." -msgstr "" +msgstr "在生成的 VHDL/Verilog 文件头中添加当前目录的 Git 哈希值。" #: ../../SpinalHDL/Other features/vhdl_generation.rst:140 language msgid "``dontCareGenAsZero``" -msgstr "" +msgstr "``dontCareGenAsZero``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:143 language msgid "Replace mySignal.assignDontCare() by mySignal := 0" -msgstr "" +msgstr "将 mySignal.assignDontCare() 替换为 mySignal := 0" #: ../../SpinalHDL/Other features/vhdl_generation.rst:144 language msgid "``obfuscateNames``" -msgstr "" +msgstr "``obfuscateNames``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:147 language msgid "Will obfuscate the generated components and signal names." -msgstr "" +msgstr "混淆生成的组件名与信号名。" #: ../../SpinalHDL/Other features/vhdl_generation.rst:148 language msgid "``rtlHeader``" -msgstr "" +msgstr "``rtlHeader``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:150 language msgid "disabled" -msgstr "" +msgstr "disabled" #: ../../SpinalHDL/Other features/vhdl_generation.rst:151 language msgid "Allow to manually specify the VHDL/Verilog file header" -msgstr "" +msgstr "允许手动指定 VHDL/Verilog 文件头" #: ../../SpinalHDL/Other features/vhdl_generation.rst:152 language msgid "``withTimescale``" -msgstr "" +msgstr "``withTimescale``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:154 language msgid "True" -msgstr "" +msgstr "True" #: ../../SpinalHDL/Other features/vhdl_generation.rst:155 language msgid "Enable the addition of the timescale in the generated Verilog" -msgstr "" +msgstr "在生成的 Verilog 代码中添加时间尺度（timescale）" #: ../../SpinalHDL/Other features/vhdl_generation.rst:156 language msgid "``normalizeComponentClockDomainName``" -msgstr "" +msgstr "``normalizeComponentClockDomainName``" #: ../../SpinalHDL/Other features/vhdl_generation.rst:158 language -#, fuzzy msgid "False" -msgstr "false" +msgstr "False" #: ../../SpinalHDL/Other features/vhdl_generation.rst:159 language msgid "" "When enabled, in each component, the pulled clockdomain's signals of the " "implicit clockdomain will be named clk/reset/enable instead of their " "original name." -msgstr "" +msgstr "启用后，在每个组件中，隐式时钟域所引出的时钟域信号将被命名为 clk/reset/enable，而非其原始名称。" #: ../../SpinalHDL/Other features/vhdl_generation.rst:162 language msgid "And this is the syntax to specify them:" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/assignments.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/assignments.po index 5adca9f217c..27e3e8e8516 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/assignments.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/assignments.po @@ -11,8 +11,8 @@ msgstr "" "Language-Team:LANGUAGE MIME-Version:1.0Content-" "Type:text/plain; charset=UTF-8\n" "POT-Creation-Date: 2025-02-12 09:08+0000\n" -"PO-Revision-Date: 2023-12-18 09:29+0000\n" -"Last-Translator: Readon \n" +"PO-Revision-Date: 2026-02-11 22:35+0800\n" +"Last-Translator: CatalpaEel\n" "Language: zh_CN\n" "Language-Team: Chinese (Simplified) \n" @@ -70,7 +70,6 @@ msgid "" msgstr "2 个信号或相同类型的两个信号线束之间的自动连接。通过使用信号定义（输入/输出）来推断方向。 （与 ``:=``\\ 类似的行为）" #: ../../SpinalHDL/Semantic/assignments.rst:19 -#, fuzzy msgid "" "When muxing (for instance using ``when``, see :doc:`when_switch`.), the " "last valid standard assignment ``:=`` wins. Else, assigning twice to the " @@ -80,7 +79,7 @@ msgid "" "can be programmatically permitted on a case by case basis. (see " ":doc:`../Design errors/assignment_overlap`)." msgstr "" -"当多路复用时（例如使用 ``when``，请参阅 :doc:`when_switch`。），最后一个有效的赋值 ``:=`` " +"当多路复用时（例如使用 ``when`` ，请参阅 :doc:`when_switch` 。），最后一个有效的赋值 ``:=`` " "为准。否则，向同一范围内的同一信号赋值两次会导致重叠错误。 SpinalHDL " "默认情况下会假设这是一个无意的设计错误，并因错误而停止实例细化。对于特殊用例，可以根据具体情况以编程方式允许重叠赋值。 （参见 " ":doc:`../Design errors/assignment_overlap`）。" @@ -215,12 +214,11 @@ msgid "" msgstr "``CombInit`` 可用于复制信号及其当前的组合逻辑赋值。主要用例是能够稍后覆盖复制后信号，而不影响原始信号。" #: ../../SpinalHDL/Semantic/assignments.rst:149 -#, fuzzy msgid "" "If we look at the resulting Verilog, ``b`` is not present. Since it is a " "copy of ``a`` by reference, these variables designate the same Verilog " "``wire``." -msgstr "如果我们查看生成的 Verilog，会发现``b`` 不存在。由于它是引用的 ``a`` 的副本，因此这些变量指代相同的 Verilog 信号。" +msgstr "如果我们查看生成的 Verilog，会发现 ``b`` 不存在。由于它是引用的 ``a`` 的副本，因此这些变量指代相同的 Verilog ``wire`` 。" #: ../../SpinalHDL/Semantic/assignments.rst:168 msgid "" @@ -229,7 +227,6 @@ msgid "" msgstr "``CombInit`` 在辅助函数中特别有用，可确保返回值不引用输入。" #: ../../SpinalHDL/Semantic/assignments.rst:181 -#, fuzzy msgid "" "Without ``CombInit``, if ``c`` == false (but not if ``c`` == true), " "``a1`` and ``a2`` reference the same signal and the zero assignment is " @@ -238,7 +235,7 @@ msgid "" msgstr "" "没有 ``CombInit`` 的话，如果 ``c`` == false（而不是 ``c`` == true），``a1`` 和 ``a2`` " "会引用相同的信号，并且 ``a1`` 被赋值为零。有了 ``CombInit`` ，无论 ``c`` " -"的值是多少，我们都有一致的行为（CombInit创建新的信号）。" +"的值是多少，行为均保持一致。" #~ msgid "" #~ "It also supports Bundle assignment. " diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/rules.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/rules.po index b480f9c5ace..0c80f4e47a0 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/rules.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/rules.po @@ -11,8 +11,8 @@ msgstr "" "Language-Team:LANGUAGE MIME-Version:1.0Content-" "Type:text/plain; charset=UTF-8\n" "POT-Creation-Date: 2024-08-19 09:12+0000\n" -"PO-Revision-Date: 2024-01-12 04:06+0000\n" -"Last-Translator: tsy0123 <675526215@qq.com>\n" +"PO-Revision-Date: 2026-02-11 22:36+0800\n" +"Last-Translator: CatalpaEel\n" "Language: zh_CN\n" "Language-Team: Chinese (Simplified) \n" @@ -106,14 +106,14 @@ msgstr "" "运算符对组合信号或寄存器进行多次分配，则可能执行的最后一次赋值生效（因此可以将值设置为该状态的结果）。" #: ../../SpinalHDL/Semantic/rules.rst:46 -#, fuzzy msgid "" "It could be said that top to bottom evaluation occurs based on the state " "that exists at that time. If your upstream signal inputs are driven from" " registers and so have synchronous behavior, then it could be said that " "at each clock cycle the assignments are re-evaluated based on the new " "state at the time." -msgstr "可以说，自上而下的评估计算是根据当时的状态进行的。如果您的上游信号输入是从寄存器驱动的，因此具有同步行为，那么可以说，在每个时钟周期，都会根据当时的新状态重新计算、赋值。" +msgstr "可以说，赋值语句的求值遵循自上而下的顺序，其结果基于求值时刻的当前状态。" +"若上游信号输入由寄存器驱动，从而具有同步行为，则可以认为在每个时钟周期内，赋值操作都会根据该时刻的新状态被重新求值。" #: ../../SpinalHDL/Semantic/rules.rst:51 msgid "" @@ -123,13 +123,12 @@ msgid "" msgstr "在硬件中，赋值语句可能无法在本时钟周期执行的一些原因，可能是由于它被包装在 ``when(cond)`` 子句中。" #: ../../SpinalHDL/Semantic/rules.rst:54 -#, fuzzy msgid "" "Another reason maybe that the SpinalHDL code never made it through " "elaboration because the feature was parameterized and disabled during HDL" " code-generation, see ``paramIsFalse`` use below." msgstr "" -"另一个原因，可能是 SpinalHDL 代码从未通过实力细化，因为该功能在 HDL 代码生成期间被参数化并禁用，请参阅下面 " +"另一个可能的原因是，该功能因参数化配置而在 HDL 代码生成阶段被禁用，导致 SpinalHDL 代码未能完成细化过程。请参阅下面 " "``paramIsFalse`` 的案例。" #: ../../SpinalHDL/Semantic/rules.rst:58 diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/when_switch.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/when_switch.po index 2e472248ba8..f9b4aaa87ce 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/when_switch.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Semantic/when_switch.po @@ -51,19 +51,17 @@ msgid "WhenBuilder" msgstr "WhenBuilder" #: ../../SpinalHDL/Semantic/when_switch.rst:46 -#, fuzzy msgid "" "Sometimes we need to generate some parameters for the when condition, and" " the original structure of ``when``/``otherwise`` is not very suitable. " "Therefore, we provide a 'whenBuilder' method to achieve this goal:" -msgstr "有时需要为when条件生成一些参数，而when else结构并不太合适。因此，我们提供了一个'whenBuilder'方法来实现这个目标" +msgstr "有时需要为when条件生成一些参数，而 ``when``/ ``otherwise`` 结构并不太合适。因此，我们提供了一个'whenBuilder'方法来实现这个目标" #: ../../SpinalHDL/Semantic/when_switch.rst:73 -#, fuzzy msgid "" "Compared to the ``when``/``elsewhen``/``otherwise`` approach, it might be" " more convenient for parameterization. we can also use like this:" -msgstr "与when/elsewhen/otherwise方法相比，它可能更方便于参数化。我们也可以这样使用" +msgstr "与 ``when``/``elsewhen``/``otherwise`` 方法相比，它可能更方便于参数化。我们也可以这样使用" #: ../../SpinalHDL/Semantic/when_switch.rst:94 msgid "" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Sequential logic/memory.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Sequential logic/memory.po index 767eb72d15d..661dc02a090 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Sequential logic/memory.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Sequential logic/memory.po @@ -395,18 +395,16 @@ msgid "Blackbox all memory." msgstr "黑盒化所有存储器。" #: ../../SpinalHDL/Sequential logic/memory.rst -#, fuzzy msgid "Throw an error on unblackboxable memory." -msgstr "对不可黑盒存储器抛出错误" +msgstr "遇到无法黑盒化的存储器时抛出错误。" #: ../../SpinalHDL/Sequential logic/memory.rst:231 msgid "``blackboxAllWhatsYouCan``" msgstr "``blackboxAllWhatsYouCan``" #: ../../SpinalHDL/Sequential logic/memory.rst:232 -#, fuzzy msgid "Blackbox every memory that is replaceable." -msgstr "黑盒所有可黑盒的存储器" +msgstr "黑盒化所有可黑盒的存储器" #: ../../SpinalHDL/Sequential logic/memory.rst:233 msgid "``blackboxRequestedAndUninferable``" @@ -423,14 +421,12 @@ msgid "``blackboxOnlyIfRequested``" msgstr "``blackboxOnlyIfRequested``" #: ../../SpinalHDL/Sequential logic/memory.rst -#, fuzzy msgid "Blackbox memory specified by the user." msgstr "用户指定的黑盒存储器" #: ../../SpinalHDL/Sequential logic/memory.rst:239 -#, fuzzy msgid "``blackboxByteEnables``" -msgstr "``blackboxAll``" +msgstr "``blackboxByteEnables``" #: ../../SpinalHDL/Sequential logic/memory.rst msgid "Blackbox every memory which use write port with byte mask." diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Sequential logic/registers.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Sequential logic/registers.po index 3ca971240d8..6831d202651 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Sequential logic/registers.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Sequential logic/registers.po @@ -11,8 +11,8 @@ msgstr "" "Language-Team:LANGUAGE MIME-Version:1.0Content-" "Type:text/plain; charset=UTF-8\n" "POT-Creation-Date: 2025-02-12 09:08+0000\n" -"PO-Revision-Date: 2024-01-13 05:06+0000\n" -"Last-Translator: tsy0123 <675526215@qq.com>\n" +"PO-Revision-Date: 2026-02-11 22:41+0800\n" +"Last-Translator: CatalpaEel\n" "Language: zh_CN\n" "Language-Team: Chinese (Simplified) \n" @@ -38,7 +38,6 @@ msgid "" msgstr "在 Spinal 中，没有 process/always 块。寄存器在声明时明确定义。这种与传统的事件驱动 HDL 的区别具有很大的影响：" #: ../../SpinalHDL/Sequential logic/registers.rst:11 -#, fuzzy msgid "" "You can assign registers and signals in the same scope, meaning the code " "doesn't need to be split between process/always blocks" @@ -176,7 +175,6 @@ msgid "Register vectors" msgstr "寄存器组" #: ../../SpinalHDL/Sequential logic/registers.rst:160 -#, fuzzy msgid "" "As for signals, it is possible to define a vector of registers with " "``Vec``." @@ -195,12 +193,10 @@ msgid "" msgstr "如果由于初始化值未知而必须推迟初始化，请使用如下例所示的函数。" #: ../../SpinalHDL/Sequential logic/registers.rst:208 -#, fuzzy msgid "Transforming a signal into a register" -msgstr "将线缆/信号转换为寄存器" +msgstr "将信号转换为寄存器" #: ../../SpinalHDL/Sequential logic/registers.rst:210 -#, fuzzy msgid "" "Sometimes it is useful to transform an existing signal into a register. " "For instance, when you are using a ``Bundle``, if you want some outputs " @@ -210,7 +206,7 @@ msgid "" "``io.myBundle.PORT := PORT``. To do this, you just need to use " "``.setAsReg()`` on the ports you want to control as registers:" msgstr "" -"有时将现有的连线转换为寄存器很有用。例如，当您使用线束（Bundle）时，如果您希望线束的某些输出成为寄存器，您可能更愿意编写 " +"有时将现有的连线转换为寄存器很有用。例如，在使用线束（Bundle）时，如果您希望线束的某些输出成为寄存器，您可能更愿意编写 " "``io.myBundle.PORT := newValue`` 而不用 ``val PORT = Reg( ...)`` 并将其输出连接到带有 " "``io.myBundle.PORT := PORT`` 的端口。为此，您只需在要实例化为寄存器的端口上使用 ``.setAsReg()``：" @@ -221,14 +217,12 @@ msgid "" msgstr "请注意，在上面的代码中，您还可以指定初始化值。" #: ../../SpinalHDL/Sequential logic/registers.rst:234 -#, fuzzy msgid "" "The register is created in the clock domain of the signal, and does not " "depend on the place where ``.setAsReg()`` is used." -msgstr "该寄存器是在线路/信号的时钟域中创建的，并且不依赖于使用 ``.setAsReg()`` 的位置。" +msgstr "该寄存器是在信号的时钟域中创建的，并且不依赖于使用 ``.setAsReg()`` 的位置。" #: ../../SpinalHDL/Sequential logic/registers.rst:237 -#, fuzzy msgid "" "In the example above, the signal is defined in the ``io`` Bundle, in the " "same clock domain as the component. Even if ``io.apb.PADDR.setAsReg()`` " @@ -236,7 +230,7 @@ msgid "" "register would use the clock domain of the component and not the one of " "the ``ClockingArea``." msgstr "" -"在上面的示例中，线路在 ``io`` 线束中定义，与组件位于同一时钟域中。即使 ``io.apb.PADDR.setAsReg()`` " +"在上面的示例中，信号在 ``io`` 线束中定义，与组件位于同一时钟域中。即使 ``io.apb.PADDR.setAsReg()`` " "这条代码写在具有不同时钟域的 ``ClockingArea`` 中，寄存器也将使用组件的时钟域，而不是 ``ClockingArea`` " "的时钟域。" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/bootstraps.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/bootstraps.po index 53169b30401..9389624fb8f 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/bootstraps.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/bootstraps.po @@ -233,7 +233,6 @@ msgid "" msgstr "对于 Verilator 后端，可以使用 ``SimConfig.setTestPath(path)`` 函数设置测试文件夹位置。" #: ../../SpinalHDL/Simulation/bootstraps.rst:165 -#, fuzzy msgid "" "You can retrieve the location of the test path during simulation by " "calling the currentTestPath() function." diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/clock.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/clock.po index 053cf731444..969c22f7305 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/clock.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/clock.po @@ -188,16 +188,14 @@ msgid "" msgstr "与 ``waitRisingEdge`` 相同，但针对 ``ClockDomainConfig`` 指定的边沿类型" #: ../../SpinalHDL/Simulation/clock.rst:57 -#, fuzzy msgid "``waitInactiveEdge([cyclesCount])``" -msgstr "``waitActiveEdge([cyclesCount])``" +msgstr "``waitInactiveEdge([cyclesCount])``" #: ../../SpinalHDL/Simulation/clock.rst:58 -#, fuzzy msgid "" "Same as ``waitFallingEdge`` but for the edge level specified by the " "``ClockDomainConfig``" -msgstr "与 ``waitRisingEdge`` 相同，但针对 ``ClockDomainConfig`` 指定的边沿类型" +msgstr "与 ``waitFallingEdge`` 相同，但针对 ``ClockDomainConfig`` 指定的边沿类型" #: ../../SpinalHDL/Simulation/clock.rst:59 msgid "``waitRisingEdgeWhere(condition)``" @@ -228,16 +226,14 @@ msgid "" msgstr "与 ``waitRisingEdgeWhere`` 相同，但针对 ``ClockDomainConfig`` 指定的边沿类型" #: ../../SpinalHDL/Simulation/clock.rst:65 -#, fuzzy msgid "``waitInactiveEdgeWhere(condition)``" -msgstr "``waitActiveEdgeWhere(condition)``" +msgstr "``waitInactiveEdgeWhere(condition)``" #: ../../SpinalHDL/Simulation/clock.rst:66 -#, fuzzy msgid "" "Same as ``waitFallingEdgeWhere``, but for the edge level specified by the" " ``ClockDomainConfig``" -msgstr "与 ``waitRisingEdgeWhere`` 相同，但针对 ``ClockDomainConfig`` 指定的边沿类型" +msgstr "与 ``waitFallingEdgeWhere`` 相同，但针对 ``ClockDomainConfig`` 指定的边沿类型" #: ../../SpinalHDL/Simulation/clock.rst:67 msgid "``waitSamplingWhere(condition) : Boolean``" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/GHDL.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/GHDL.po index 4ca429acffb..df3c9e74e21 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/GHDL.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/GHDL.po @@ -36,7 +36,6 @@ msgstr "" " 但您需要激活 oss-cad-suite 环境。" #: ../../SpinalHDL/Simulation/install/GHDL.rst:9 -#, fuzzy msgid "" "Even though GHDL is generally available in linux distributions package " "system, SpinalHDL depends on bugfixes of GHDL codebase that were added " diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Icarus Verilog.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Icarus Verilog.po index 9eb8c8a9c20..5c7ad89a226 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Icarus Verilog.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Icarus Verilog.po @@ -52,7 +52,6 @@ msgid "Linux" msgstr "Linux" #: ../../SpinalHDL/Simulation/install/Icarus Verilog.rst:20 -#, fuzzy msgid "" "Also the openjdk package that corresponds to your Java version has to be " "installed. Refer to " diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/VCS.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/VCS.po index bac1e393792..6d91a20a8ae 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/VCS.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/VCS.po @@ -220,7 +220,6 @@ msgid "Simulation with ``Blackbox``" msgstr "``Blackbox`` 仿真" #: ../../SpinalHDL/Simulation/install/VCS.rst:125 -#, fuzzy msgid "" "Sometimes, IP vendors will provide you with some design entities in " "Verilog/VHDL format and you want to integrate them into your SpinalHDL " diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Verilator.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Verilator.po index be499f9912c..6d43dfb4810 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Verilator.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Simulation/install/Verilator.po @@ -139,7 +139,6 @@ msgid "" msgstr "确保您的 ``PATH`` 环境变量指向 JDK 1.8 并且不包含 JRE 安装。" #: ../../SpinalHDL/Simulation/install/Verilator.rst:117 -#, fuzzy msgid "" "Adding the MSYS2 ``bin`` folders into your windows ``PATH`` could " "potentially have some side effects. This is why it is safer to add them " diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/blackbox.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/blackbox.po index 8ce467d6ab9..d80ec76aa67 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/blackbox.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/blackbox.po @@ -81,7 +81,6 @@ msgid "Clock and reset mapping" msgstr "时钟和复位信号的映射" #: ../../SpinalHDL/Structuring/blackbox.rst:117 -#, fuzzy msgid "" "In your blackbox definition you have to explicitly define clock and reset" " signals. To map signals of a ``ClockDomain`` to corresponding inputs of " diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/clock_domain.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/clock_domain.po index 2d73feee241..4e3f3338e06 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/clock_domain.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/clock_domain.po @@ -86,7 +86,6 @@ msgid "``clock``" msgstr "``clock``" #: ../../SpinalHDL/Structuring/clock_domain.rst:43 -#, fuzzy msgid "Clock signal that defines the domain." msgstr "定义时钟域中的时钟信号" @@ -95,7 +94,6 @@ msgid "``reset``" msgstr "``reset``" #: ../../SpinalHDL/Structuring/clock_domain.rst:46 -#, fuzzy msgid "" "Reset signal. If a register exists which needs a reset and the clock " "domain doesn't provide one, an error message will be displayed." @@ -112,7 +110,6 @@ msgid "``softReset``" msgstr "``softReset``" #: ../../SpinalHDL/Structuring/clock_domain.rst:50 -#, fuzzy msgid "Reset which infers an additional synchronous reset." msgstr "复位意味着额外的同步复位" @@ -132,7 +129,6 @@ msgid "``frequency``" msgstr "``frequency``" #: ../../SpinalHDL/Structuring/clock_domain.rst:57 -#, fuzzy msgid "" "Allows you to specify the frequency of the given clock domain and later " "read it in your design. This parameter does not generate a PLL or more " @@ -150,7 +146,6 @@ msgid "``config``" msgstr "``config``" #: ../../SpinalHDL/Structuring/clock_domain.rst:61 -#, fuzzy msgid "Specify the polarity of signals and the nature of the reset." msgstr "指定信号的极性和复位的性质" @@ -367,7 +362,6 @@ msgstr "" "``syncReset`` 和 ``softReset``。" #: ../../SpinalHDL/Structuring/clock_domain.rst:302 -#, fuzzy msgid "" "Please be careful that clockEnable has a higher priority than syncReset. " "If you do a sync reset when the clockEnable is disabled (especially at " @@ -385,7 +379,6 @@ msgid "It will generate VerilogHDL codes like:" msgstr "它将生成 Verilog HDL 代码，例如：" #: ../../SpinalHDL/Structuring/clock_domain.rst:326 -#, fuzzy msgid "" "If that behavior is problematic, one workaround is to use a when " "statement as a clock enable instead of using the ClockDomain.enable " @@ -606,14 +599,13 @@ msgid "BootReset" msgstr "启动复位" #: ../../SpinalHDL/Structuring/clock_domain.rst:521 -#, fuzzy msgid "" "``clockDomain.withBootReset()`` could specify register's resetKind as " "``BOOT``. ``clockDomain.withSyncReset()`` could specify register's " "resetKind as ``SYNC`` (sync-reset)." msgstr "" -"`clockDomain.withBootReset()` 可以指定寄存器的resetKind为BOOT。 " -"`clockDomain.withSyncReset()` 可以指定寄存器的resetKind为SYNC（同步复位）。" +"`clockDomain.withBootReset()` 可以指定寄存器的resetKind为 ``BOOT`` 。 " +"`clockDomain.withSyncReset()` 可以指定寄存器的resetKind为 ``SYNC`` （同步复位）。" #: ../../SpinalHDL/Structuring/clock_domain.rst:539 msgid "ResetArea" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/components_hierarchy.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/components_hierarchy.po index ad043a99a26..a0f33cfef60 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/components_hierarchy.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/components_hierarchy.po @@ -11,8 +11,8 @@ msgstr "" "Language-Team:LANGUAGE MIME-Version:1.0Content-" "Type:text/plain; charset=UTF-8\n" "POT-Creation-Date: 2025-02-12 09:08+0000\n" -"PO-Revision-Date: 2023-12-24 15:38+0000\n" -"Last-Translator: Readon \n" +"PO-Revision-Date: 2026-02-11 22:48+0800\n" +"Last-Translator: CatalpaEel\n" "Language: zh_CN\n" "Language-Team: Chinese (Simplified) \n" @@ -34,9 +34,8 @@ msgid "" msgstr "像在VHDL和Verilog中一样，可以使用组件构建设计层次结构。然而，在SpinalHDL中，不需要在实例化时绑定它们的端口：" #: ../../SpinalHDL/Structuring/components_hierarchy.rst -#, fuzzy, python-brace-format msgid "``val io = new Bundle { ... }``" -msgstr "``val io = new Bundle { ... }``" +msgstr "``val io = new Bundle { ... }``" #: ../../SpinalHDL/Structuring/components_hierarchy.rst msgid "" @@ -178,7 +177,6 @@ msgid "Pruned signals" msgstr "裁剪信号" #: ../../SpinalHDL/Structuring/components_hierarchy.rst:92 -#, fuzzy msgid "" "SpinalHDL will generate all the named signals and their dependencies, " "while all the useless anonymous / zero width ones are removed from the " diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/index.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/index.po index 3f4c259ac0b..31f7c05be72 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/index.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/index.po @@ -43,7 +43,6 @@ msgid "handling of clock/reset domains" msgstr "时钟/复位域的处理" #: ../../SpinalHDL/Structuring/index.rst:10 -#, fuzzy msgid "instantiation of existing VHDL and Verilog IP" msgstr "现有 VHDL 和 Verilog IP 的实例化" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/naming.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/naming.po index 62e3a62e66d..d43d4d89781 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/naming.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/naming.po @@ -68,7 +68,6 @@ msgid "Will generation :" msgstr "会生成：" #: ../../SpinalHDL/Structuring/naming.rst:41 -#, fuzzy msgid "" "In general, you don't really need to access that API, unless you want to " "do tricky stuff for debug reasons or for elaboration purposes." @@ -176,7 +175,6 @@ msgid "Composite in a Bundle's function" msgstr "在一个线束（Bundle）的函数中的复合区" #: ../../SpinalHDL/Structuring/naming.rst:255 -#, fuzzy msgid "" "This behavior can be very useful when implementing Bundle utilities. For " "instance in the spinal.lib.Stream class is defined the following :" @@ -187,12 +185,10 @@ msgid "Which allow nested calls while preserving the names :" msgstr "这将允许嵌套调用，同时保留名称：" #: ../../SpinalHDL/Structuring/naming.rst:363 -#, fuzzy msgid "Unnamed signal handling" msgstr "未命名信号处理" #: ../../SpinalHDL/Structuring/naming.rst:365 -#, fuzzy msgid "" "Since 1.5.0, for signal which end up without name, SpinalHDL will find a " "signal which is driven by that unnamed signal and propagate its name. " @@ -203,11 +199,10 @@ msgstr "" "将找到由该信号驱动的信号并传播其名称。只要您没有太多未命名的东西，这就可以产生有用的结果。" #: ../../SpinalHDL/Structuring/naming.rst:367 -#, fuzzy msgid "" "The name attributed to such unnamed signal is : _zz_ + " "drivenSignal.getName()" -msgstr "这种未命名信号的名称是：_zz_ +drivenSignal.getName()" +msgstr "这种未命名信号的名称是：_zz_ + drivenSignal.getName()" #: ../../SpinalHDL/Structuring/naming.rst:369 msgid "" @@ -221,7 +216,6 @@ msgid "Verilog expression splitting" msgstr "Verilog 表达式分割" #: ../../SpinalHDL/Structuring/naming.rst:374 -#, fuzzy msgid "" "There is an instance of expressions (ex : the + operator) that SpinalHDL " "need to express in dedicated signals to match the behavior with the Scala" @@ -233,7 +227,6 @@ msgid "Verilog long expression splitting" msgstr "Verilog 长表达式分割" #: ../../SpinalHDL/Structuring/naming.rst:406 -#, fuzzy msgid "" "There is a instance of how a very long expression chain will be split up " "by SpinalHDL :" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/parametrization.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/parametrization.po index c67ffe37e7e..925c9f233ba 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/parametrization.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/Structuring/parametrization.po @@ -104,7 +104,6 @@ msgid "Here are some examples and ideas of the possibilities:" msgstr "以下是一些示例和可能的想法：" #: ../../SpinalHDL/Structuring/parametrization.rst:46 -#, fuzzy msgid "" "Hardwired code and constants (not strictly parameter management at all " "but serves to highlight the most basic mechanism, a code change, not a " @@ -201,7 +200,6 @@ msgstr "" "null。" #: ../../SpinalHDL/Structuring/parametrization.rst:111 -#, fuzzy msgid "" "This may be used in cases to help parameterize the SpinalHDL hardware " "description using an elaboration-time conditional expression. Causing " @@ -213,7 +211,6 @@ msgstr "" "中存在或不存在。generate函数可以看作是 SpinalHDL 语法糖，减少语言混乱。" #: ../../SpinalHDL/Structuring/parametrization.rst:116 -#, fuzzy msgid "" "Project SpinalHDL code referencing ``mySignal`` would need to ensure it " "handles the possibility of null gracefully. This is usually not a " diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/core/core_components.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/core/core_components.po index dc3d6228b6b..915c58c3c36 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/core/core_components.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/core/core_components.po @@ -147,7 +147,6 @@ msgid "Clock configuration" msgstr "时钟配置" #: ../../SpinalHDL/miscelenea/core/core_components.rst:72 -#, fuzzy msgid "" "In addition to the constructor parameters given :ref:`here " "` , the following elements of each " @@ -216,12 +215,11 @@ msgid "External clock" msgstr "外部时钟" #: ../../SpinalHDL/miscelenea/core/core_components.rst:123 -#, fuzzy msgid "" "You can define everywhere a clock domain which is driven by the outside. " "It will then automatically add clock and reset signal from the top level " "inputs to all synchronous elements." -msgstr "您可以在任何地方定义由外部驱动的时钟域。然后，它会自动将时钟和复位线从顶层输入添加到所有同步元件。" +msgstr "您可以在任何地方定义由外部驱动的时钟域。该时钟域将自动从顶层输入引入时钟与复位信号，并连接至所有同步元件。" #: ../../SpinalHDL/miscelenea/core/core_components.rst:141 msgid "Cross Clock Domain" @@ -243,7 +241,6 @@ msgid "There are multiple assignment operator :" msgstr "有多种赋值运算符：" #: ../../SpinalHDL/miscelenea/core/core_components.rst:169 -#, fuzzy msgid "Symbol" msgstr "符号" @@ -289,7 +286,6 @@ msgid "" msgstr "2 个信号之间的自动连接。通过输入/输出设置推断信号方向" #: ../../SpinalHDL/miscelenea/core/core_components.rst -#, fuzzy msgid "Similar behavioral than :=" msgstr "与 := 类似的行为" @@ -323,12 +319,10 @@ msgid "Assign x with a resized copy of y, size is manually calculated" msgstr "将 y 改变位宽后的副本分配给 x，大小是手动计算的" #: ../../SpinalHDL/miscelenea/core/core_components.rst:212 -#, fuzzy msgid "There are 2 cases where spinal automatically resize things :" msgstr "有两种情况会导致spinal自动调整位宽：" #: ../../SpinalHDL/miscelenea/core/core_components.rst:218 -#, fuzzy msgid "Assignment" msgstr "赋值" @@ -367,7 +361,6 @@ msgid "SpinalHDL reapply the default value to bit that are missing" msgstr "SpinalHDL 将默认值重新应用于丢失的位" #: ../../SpinalHDL/miscelenea/core/core_components.rst:232 -#, fuzzy msgid "" "As VHDL and Verilog, signals and registers can be conditionally assigned " "by using when and switch syntaxes" @@ -494,11 +487,10 @@ msgid "Everything work by reference, which allow many manipulation." msgstr "一切都按参考工作，这允许许多操作。" #: ../../SpinalHDL/miscelenea/core/core_components.rst -#, fuzzy msgid "" "For example you can give to a function an bus as argument, then the " "function can internally read/write it." -msgstr "例如，您可以为函数提供总线作为参数，然后可以在该函数内部读取/写入它。" +msgstr "例如，您可以为函数提供总线作为参数，然后该函数便可在其内部对该总线进行读写操作。" #: ../../SpinalHDL/miscelenea/core/core_components.rst msgid "" diff --git a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/frequent_errors.po b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/frequent_errors.po index 274064b9409..0356ca55c9f 100644 --- a/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/frequent_errors.po +++ b/source/locale/zh_CN/LC_MESSAGES/SpinalHDL/miscelenea/frequent_errors.po @@ -58,7 +58,6 @@ msgid "**Issue explanation :**" msgstr "**问题解释：**" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:29 -#, fuzzy msgid "" "SpinalHDL is not a language, it is an Scala library, which mean, it obey " "to the same rules than the Scala general purpose programming language. " @@ -88,7 +87,6 @@ msgid "Signal X can't be assigned by Y" msgstr "Signal X can't be assigned by Y" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:87 -#, fuzzy msgid "" "You can only assign input signals of subcomponents, else there is an " "hierarchy violation. If this issue happened, you probably forgot to " @@ -100,7 +98,6 @@ msgid "Input signal X can't be assigned by Y" msgstr "Input signal X can't be assigned by Y" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:114 -#, fuzzy msgid "" "You can only assign an input signals from the parent component, else " "there is an hierarchy violation. If this issue happened, you probably " @@ -112,7 +109,6 @@ msgid "Output signal X can't be assigned by Y" msgstr "Output signal X can't be assigned by Y" #: ../../SpinalHDL/miscelenea/frequent_errors.rst:146 -#, fuzzy msgid "" "You can only assign output signals of a component from the inside of it, " "else there is an hierarchy violation. If this issue happened, you " From b35653de6ec1f97ec8512e7744f569d61f0fea32 Mon Sep 17 00:00:00 2001 From: CatalpaEel <139088727+CatalpaEel@users.noreply.github.com> Date: Wed, 11 Feb 2026 22:54:07 +0800 Subject: [PATCH 3/3] Fix some typo --- source/SpinalHDL/Data types/Int.rst | 2 +- source/SpinalHDL/Libraries/regIf.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/source/SpinalHDL/Data types/Int.rst b/source/SpinalHDL/Data types/Int.rst index 3c9c03e8cf0..82d32f963ab 100644 --- a/source/SpinalHDL/Data types/Int.rst +++ b/source/SpinalHDL/Data types/Int.rst @@ -587,7 +587,7 @@ About Rounding: https://en.wikipedia.org/wiki/Rounding The **RoundToEven** and **RoundToOdd** modes are very special, and are used in some big data statistical fields with high accuracy concerns, SpinalHDL doesn't support them yet. -You will find ``ROUNDUP``, ``ROUNDDOWN``, ``ROUNDTOZERO``, ``ROUNDTOINF``, ``ROUNDTOEVEN``, ``ROUNTOODD`` are very close in behavior, +You will find ``ROUNDUP``, ``ROUNDDOWN``, ``ROUNDTOZERO``, ``ROUNDTOINF``, ``ROUNDTOEVEN``, ``ROUNDTOODD`` are very close in behavior, ``ROUNDTOINF`` is the most common. The behavior of rounding in different programming languages may be different. ============= =================== ================================================= ==================== diff --git a/source/SpinalHDL/Libraries/regIf.rst b/source/SpinalHDL/Libraries/regIf.rst index 8f55b3017b0..78d227e8338 100644 --- a/source/SpinalHDL/Libraries/regIf.rst +++ b/source/SpinalHDL/Libraries/regIf.rst @@ -36,7 +36,7 @@ Automatic address allocation .. image:: /asset/image/regif/reg-auto-allocate.gif -Automatic filed allocation +Automatic field allocation .. code:: scala