Skip to content

fix simplification: MergeEquivalentGates reconstruction now is topological #110

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
spefk merged 3 commits into from
Jan 25, 2026
Merged

fix simplification: MergeEquivalentGates reconstruction now is topological #110

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
addaca0
fixes
spefk Dec 7, 2025
a5b62c9
formatting
spefk Dec 7, 2025
eb96b15
fix
spefk Dec 7, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
20 changes: 13 additions & 7 deletions cirbo/minimization/simplification/cleanup.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -16,21 +16,27 @@
logger = logging.getLogger(__name__)


def cleanup(circuit: Circuit) -> Circuit:
def cleanup(circuit: Circuit, *, use_heavy: bool = False) -> Circuit:
"""
Applies several simplification algorithms from this module consecutively in order to
simplify provided circuit.

:param circuit: the original circuit to be simplified
:param use_heavy: if True, then heavier cleanups (e.g. `MergeEquivalentGates`)
will also be used.
:return: new simplified version of the circuit

"""
_strategies = [
RemoveRedundantGates(),
MergeUnaryOperators(),
MergeDuplicateGates(),
]

if use_heavy:
_strategies += [MergeEquivalentGates()]

return Transformer.apply_transformers(
circuit,
[
RemoveRedundantGates(),
MergeUnaryOperators(),
MergeDuplicateGates(),
MergeEquivalentGates(),
],
_strategies,
)
34 changes: 29 additions & 5 deletions cirbo/minimization/simplification/merge_equivalent_gates.py
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
import collections
import dataclasses
import logging
import typing as tp

Expand Down Expand Up @@ -66,6 +67,25 @@ def _find_equivalent_gates_groups(circuit: Circuit) -> list[list[Label]]:
return equivalent_groups


@dataclasses.dataclass
class _Keep:
"""
A representative element for the group.

If holds None, then no elements of the group were reconstructed yet. When the first
element of the group is rebuild, It will be set as Keep.

"""

value: tp.Optional[str] = None

def set_or_get_existing(self, label: str) -> str:
if self.value is None:
self.value = label

return self.value


def _replace_equivalent_gates(
circuit: Circuit,
equivalent_groups: tp.Iterable[tp.Collection[Label]],
Expand All @@ -92,15 +112,19 @@ def _replace_equivalent_gates(
)
continue

_group_iter = iter(group)
keep = next(_group_iter)
for gate_to_replace in _group_iter:
keep = _Keep()
for gate_to_replace in group:
_old_to_new_gate[gate_to_replace] = keep

# map gate label to its new name.
# map gate label to its new name and sets Keep when needed.
def _get_gate_new_name(_label: Label):
nonlocal _old_to_new_gate
return _old_to_new_gate.get(_label, _label)

if _label not in _old_to_new_gate:
return _label

_keep = _old_to_new_gate[_label]
return _keep.set_or_get_existing(_label)

# rebuild circuit from inputs to outputs with remapping.
def _process_gate(_gate: Gate, _: tp.Mapping):
Expand Down
6 changes: 3 additions & 3 deletions tests/cirbo/minimization/simplification/merge_equivalent_gates_test.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -76,10 +76,10 @@ def test_find_equivalent_gates(original_circuit: Circuit, expected_groups):
expected_circuit_3.add_gate(Gate('input4', gate.INPUT))
expected_circuit_3.emplace_gate('AND2', gate.AND, ('input1', 'input2'))
expected_circuit_3.add_gate(Gate('OR2', gate.OR, ('AND2', 'input3')))
expected_circuit_3.add_gate(Gate('XOR2', gate.XOR, ('AND2', 'OR2')))
expected_circuit_3.add_gate(Gate('XOR1', gate.XOR, ('AND2', 'OR2')))
expected_circuit_3.mark_as_output('AND2')
expected_circuit_3.mark_as_output('XOR2')
expected_circuit_3.mark_as_output('XOR2')
expected_circuit_3.mark_as_output('XOR1')
expected_circuit_3.mark_as_output('XOR1')


@pytest.mark.parametrize(
Expand Down
2 changes: 1 addition & 1 deletion tutorial/cleaning_majority7_circuit.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7,5 +7,5 @@
*_, b2 = add_sum_n_bits(ckt, ckt.inputs)
ckt.mark_as_output(b2)
print(ckt.gates_number())
ckt = cleanup(ckt)
ckt = cleanup(ckt, use_heavy=True)
print(ckt.gates_number())
5 changes: 5 additions & 0 deletions tutorial/simple_cleanup.py
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
from cirbo.core import Circuit, Gate
from cirbo.minimization import cleanup

circ = Circuit.from_bench_file("../data/circuit.bench")
circ = cleanup(circ)