From 622d25ac274c95d9e1c53a7b2e9fd745ea716d4c Mon Sep 17 00:00:00 2001 From: tonokip Date: Sat, 28 Nov 2020 15:52:06 -0600 Subject: [PATCH 1/3] fix enable pin --- src/microstepper/microstepper_top.v | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index e2438aa..3c881dc 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -62,15 +62,15 @@ end wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l; wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; - assign s_l[0] = !(phase_a1_l | fault); - assign s_l[1] = !(phase_a2_l | fault); - assign s_l[2] = !(phase_b1_l | fault); - assign s_l[3] = !(phase_b2_l | fault); - - assign s_h[0] = !(phase_a1_h | fault); - assign s_h[1] = !(phase_a2_h | fault); - assign s_h[2] = !(phase_b1_h | fault); - assign s_h[3] = !(phase_b2_h | fault); + assign s_l[0] = !(phase_a1_l | fault | enable); + assign s_l[1] = !(phase_a2_l | fault | enable); + assign s_l[2] = !(phase_b1_l | fault | enable); + assign s_l[3] = !(phase_b2_l | fault | enable); + + assign s_h[0] = !(phase_a1_h | fault | enable); + assign s_h[1] = !(phase_a2_h | fault | enable); + assign s_h[2] = !(phase_b1_h | fault | enable); + assign s_h[3] = !(phase_b2_h | fault | enable); assign phase_a1_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s1r[1] : ~s1r[1])); assign phase_a1_l = config_invert_lowside ^ (fastDecay0 ? ~s1r[1] : (slowDecay0 ? 1'b0 : s1r[1])); From 2cd1a9bd2f317c47d7a8fffc1036d93f0d13f0e5 Mon Sep 17 00:00:00 2001 From: tonokip Date: Sat, 28 Nov 2020 16:20:50 -0600 Subject: [PATCH 2/3] make fault latching. implement enable. also gate the outputs with reset. --- src/microstepper/microstepper_top.v | 32 +++++++++++++++++++++-------- src/top.v | 2 +- 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index 3c881dc..ba5e9a1 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -56,21 +56,24 @@ end wire fault0 = (minimum_on_timer0 > 0) && overCurrent0; wire fault1 = (minimum_on_timer1 > 0) && overCurrent1; - wire fault = fault0 | fault1; + wire fault_active = fault0 | fault1; + reg fault; + reg resetn_buf; + reg enable_buf; reg [1:0] s1r, s2r, s3r, s4r; wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l; wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; - assign s_l[0] = !(phase_a1_l | fault | enable); - assign s_l[1] = !(phase_a2_l | fault | enable); - assign s_l[2] = !(phase_b1_l | fault | enable); - assign s_l[3] = !(phase_b2_l | fault | enable); + assign s_l[0] = !(phase_a1_l | fault | enable_buf) & resetn_buf; + assign s_l[1] = !(phase_a2_l | fault | enable_buf) & resetn_buf; + assign s_l[2] = !(phase_b1_l | fault | enable_buf) & resetn_buf; + assign s_l[3] = !(phase_b2_l | fault | enable_buf) & resetn_buf; - assign s_h[0] = !(phase_a1_h | fault | enable); - assign s_h[1] = !(phase_a2_h | fault | enable); - assign s_h[2] = !(phase_b1_h | fault | enable); - assign s_h[3] = !(phase_b2_h | fault | enable); + assign s_h[0] = !(phase_a1_h | fault | enable_buf) & resetn_buf; + assign s_h[1] = !(phase_a2_h | fault | enable_buf) & resetn_buf; + assign s_h[2] = !(phase_b1_h | fault | enable_buf) & resetn_buf; + assign s_h[3] = !(phase_b2_h | fault | enable_buf) & resetn_buf; assign phase_a1_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s1r[1] : ~s1r[1])); assign phase_a1_l = config_invert_lowside ^ (fastDecay0 ? ~s1r[1] : (slowDecay0 ? 1'b0 : s1r[1])); @@ -96,7 +99,18 @@ end end `endif + // Fault Conditions always @(posedge clk) begin + if (!resetn) + fault <= 0; + else if( fault_active ) + fault <= 1; + end + + // Buffers + always @(posedge clk) begin + enable_buf <= enable; + resetn_buf <= resetn; s1r <= {s1r[0], s1}; s2r <= {s2r[0], s2}; s3r <= {s3r[0], s3}; diff --git a/src/top.v b/src/top.v index f7d987b..54888ad 100644 --- a/src/top.v +++ b/src/top.v @@ -187,7 +187,7 @@ module top ( wire step; wire dir; - reg enable; + reg enable = 0; `ifdef DUAL_HBRIDGE DualHBridge s0 (.phase_a1 (PHASE_A1[1]), From fa899165a0e4d9757c19eb8fea8b51862a36a4fb Mon Sep 17 00:00:00 2001 From: tonokip Date: Sun, 29 Nov 2020 01:20:47 -0600 Subject: [PATCH 3/3] invert resetn_buf to reset_buf. move inverting config to effect all other logic. --- src/microstepper/microstepper_top.v | 36 ++++++++++++++--------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/src/microstepper/microstepper_top.v b/src/microstepper/microstepper_top.v index ba5e9a1..a493ce1 100644 --- a/src/microstepper/microstepper_top.v +++ b/src/microstepper/microstepper_top.v @@ -58,32 +58,32 @@ end wire fault1 = (minimum_on_timer1 > 0) && overCurrent1; wire fault_active = fault0 | fault1; reg fault; - reg resetn_buf; + reg reset_buf; reg enable_buf; reg [1:0] s1r, s2r, s3r, s4r; wire phase_a1_h, phase_a1_l, phase_a2_h, phase_a2_l; wire phase_b1_h, phase_b1_l, phase_b2_h, phase_b2_l; - assign s_l[0] = !(phase_a1_l | fault | enable_buf) & resetn_buf; - assign s_l[1] = !(phase_a2_l | fault | enable_buf) & resetn_buf; - assign s_l[2] = !(phase_b1_l | fault | enable_buf) & resetn_buf; - assign s_l[3] = !(phase_b2_l | fault | enable_buf) & resetn_buf; + assign s_l[0] = config_invert_lowside ^ (phase_a1_l | fault | enable_buf | reset_buf); + assign s_l[1] = config_invert_lowside ^ (phase_a2_l | fault | enable_buf | reset_buf); + assign s_l[2] = config_invert_lowside ^ (phase_b1_l | fault | enable_buf | reset_buf); + assign s_l[3] = config_invert_lowside ^ (phase_b2_l | fault | enable_buf | reset_buf); - assign s_h[0] = !(phase_a1_h | fault | enable_buf) & resetn_buf; - assign s_h[1] = !(phase_a2_h | fault | enable_buf) & resetn_buf; - assign s_h[2] = !(phase_b1_h | fault | enable_buf) & resetn_buf; - assign s_h[3] = !(phase_b2_h | fault | enable_buf) & resetn_buf; + assign s_h[0] = config_invert_highside ^ (phase_a1_h | fault | enable_buf | reset_buf); + assign s_h[1] = config_invert_highside ^ (phase_a2_h | fault | enable_buf | reset_buf); + assign s_h[2] = config_invert_highside ^ (phase_b1_h | fault | enable_buf | reset_buf); + assign s_h[3] = config_invert_highside ^ (phase_b2_h | fault | enable_buf | reset_buf); - assign phase_a1_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s1r[1] : ~s1r[1])); - assign phase_a1_l = config_invert_lowside ^ (fastDecay0 ? ~s1r[1] : (slowDecay0 ? 1'b0 : s1r[1])); - assign phase_a2_h = config_invert_highside ^ (slowDecay0 | (fastDecay0 ? s2r[1] : ~s2r[1])); - assign phase_a2_l = config_invert_lowside ^ (fastDecay0 ? ~s2r[1] : (slowDecay0 ? 1'b0 : s2r[1])); + assign phase_a1_h = (slowDecay0 | (fastDecay0 ? s1r[1] : ~s1r[1])); + assign phase_a1_l = (fastDecay0 ? ~s1r[1] : (slowDecay0 ? 1'b0 : s1r[1])); + assign phase_a2_h = (slowDecay0 | (fastDecay0 ? s2r[1] : ~s2r[1])); + assign phase_a2_l = (fastDecay0 ? ~s2r[1] : (slowDecay0 ? 1'b0 : s2r[1])); - assign phase_b1_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s3r[1] : ~s3r[1])); - assign phase_b1_l = config_invert_lowside ^ (fastDecay1 ? ~s3r[1] : (slowDecay1 ? 1'b0 : s3r[1])); - assign phase_b2_h = config_invert_highside ^ (slowDecay1 | (fastDecay1 ? s4r[1] : ~s4r[1])); - assign phase_b2_l = config_invert_lowside ^ (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1])); + assign phase_b1_h = (slowDecay1 | (fastDecay1 ? s3r[1] : ~s3r[1])); + assign phase_b1_l = (fastDecay1 ? ~s3r[1] : (slowDecay1 ? 1'b0 : s3r[1])); + assign phase_b2_h = (slowDecay1 | (fastDecay1 ? s4r[1] : ~s4r[1])); + assign phase_b2_l = (fastDecay1 ? ~s4r[1] : (slowDecay1 ? 1'b0 : s4r[1])); wire s1_starting = s1r == 2'b10; wire s2_starting = s2r == 2'b10; @@ -110,7 +110,7 @@ end // Buffers always @(posedge clk) begin enable_buf <= enable; - resetn_buf <= resetn; + reset_buf <= ~resetn; s1r <= {s1r[0], s1}; s2r <= {s2r[0], s2}; s3r <= {s3r[0], s3};