diff --git a/sim_microstepper.ys b/sim_microstepper.ys
index 4fa0635..ee2d8ba 100644
--- a/sim_microstepper.ys
+++ b/sim_microstepper.ys
@@ -8,6 +8,6 @@ read_verilog -sv testbench/microstepper_tb.v \
     src/microstepper/mytimer_8.v \
     src/microstepper/mytimer_10.v
 
-prep -top testbench
+prep -top microstepper_tb
 show microstepper_top
 sim -n 400000 -clock clk -vcd testbench/microstepper.vcd
diff --git a/src/microstepper/microstepper_control.v b/src/microstepper/microstepper_control.v
index 875a39f..be5bb6c 100644
--- a/src/microstepper/microstepper_control.v
+++ b/src/microstepper/microstepper_control.v
@@ -80,9 +80,9 @@ module microstepper_control (
   // Low side output polarity, enable, and fault shutdown
   // Outputs are active high unless config_invert_**** is set
   assign phase_a1_l_out = config_invert_lowside ^ ( phase_a1_l | !enable );
-  assign phase_a2_l_out = config_invert_lowside ^ ( phase_a2_l | !enable );
+  assign phase_a2_l_out = config_invert_lowside ^ ( phase_a2_l && faultn && enable );
   assign phase_b1_l_out = config_invert_lowside ^ ( phase_b1_l | !enable );
-  assign phase_b2_l_out = config_invert_lowside ^ ( phase_b2_l | !enable );
+  assign phase_b2_l_out = config_invert_lowside ^ ( phase_b2_l && faultn && enable );
 
   // High side
   assign phase_a1_h_out = config_invert_highside ^  ( phase_a1_h && faultn && enable );