SPI Error Correction #191
Description
After looking at some other devices I am noticing CRC is commonly used for user-space protocols.
8b/10b is also used with CRC, but it appears generally at physical layers and it high end buses like PCIe and USB3, so it may be expensive to do this in software. OTOH, 8b/10b could just be a lookup table ~1kB and may still achieve good performance for processors with sufficient cache, but I'm not sure things like microcontrollers would be able to do this well. So far I have not seen this done in userspace software, so it would be experimental and risky. We will likely want to revisit this at some point.
The issues and risks to CRC are the transfer process. Since we have "stream" modes such as coordinated moves, we need to be certain the header is ACK before proceeding with the stream payload, or we may accidentally trigger a different mode in the state machine. It is therefore likely easiest to do CRC on each 64bit word at a time. The performance implications of this in host controller software will need to be quantified some how. On the gateware sides of things this can be done non-combinatorially (see pony link below), so we should not introduce latency on the peripheral side of things. Gateware should also have no state machine changes, with CRC checks and error handling residing in the SPI bus module.
A good reference for a CRC + 8b/10b protocol with Verilog and C code: https://github.com/cliffordwolf/PonyLink