State machines in verilog

[AlexDaniel]

This one is a little bit tricky. Existing verilog files include something like this:

`define IDLE  6'b000001
`define North 6'b000010
`define East  6'b000100
`define West  6'b001000
`define South 6'b010000
`define Local 6'b100000

// … … …
reg [5:0] state = `IDLE;
reg [5:0] state_in = `IDLE; // encoded as one-hot

I've kept it similarly in my files also, but this doesn't mean that it is right.

The problem is that most synthesizers will re-encode state machines (which are detected automatically) with their own encoding, unless told otherwise. Therefore, the values that are specified in macros are actually meaningless, and you can put anything there, the actual encoding will always be the same (which one exactly depends on the synthesizer).

I think the right way to ensure one-hot encoding would be:

(* fsm_encoding = "one-hot" *) logic [5:0] state;

However, there are many aspects that affect everything, so I'll just leave it as an issue here for the next brave soul to tackle.