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This repository was archived by the owner on Dec 16, 2021. It is now read-only.
Xilinx newbie, but I ran source build_all.tcl and ended up with
Xilinx/Vivado_HLS/2016.1/include/etc/ap_int_sim.h:75:10: fatal error: 'stdio.h' file not found
#include <stdio.h>
^
1 error generated.
Failed checking during preprocessing.
while executing
"source [lindex $::argv 1] "
("uplevel" body line 1)
invoked from within
"uplevel \#0 { source [lindex $::argv 1] } "
child process exited abnormally
Is this just a C HDL thing.
Also in a new overlay build instance once I add the IP I have wrapped my HDL(verilog, ect.) code in to block design can I just throw down a ZYNQ IP block without making any modifications to the ZYNQ IP. And this is assuming that in the vivado project setup I specified the PYNQ-Z1 board files and added the PYNQ-Z1 constraint file.