diff --git a/fpga_diff/src/rtl/common/XDMA_AXI4LiteBar.sv b/fpga_diff/src/rtl/common/XDMA_AXI4LiteBar.sv
index 9dfbd33..6817740 100644
--- a/fpga_diff/src/rtl/common/XDMA_AXI4LiteBar.sv
+++ b/fpga_diff/src/rtl/common/XDMA_AXI4LiteBar.sv
@@ -31,6 +31,7 @@ module XDMA_AXI4LiteBar(
   input         io_axi_read_rready,
 
   // sideband
+  output        io_host_diff_enable,
   output        io_host_reset
 );
 
@@ -65,7 +66,7 @@ module XDMA_AXI4LiteBar(
 
   // Sideband signals
   assign io_host_reset             = regfile_0[0];
-
+  assign io_host_diff_enable       = regfile_1[0];
   // Byte-lane masked write
   function automatic [31:0] mask_write32(
     input [31:0] oldv, input [31:0] newv, input [3:0] strb
diff --git a/fpga_diff/src/rtl/common/core_def_xdma.sv b/fpga_diff/src/rtl/common/core_def_xdma.sv
index 24c18b3..5f0919f 100755
--- a/fpga_diff/src/rtl/common/core_def_xdma.sv
+++ b/fpga_diff/src/rtl/common/core_def_xdma.sv
@@ -1071,6 +1071,7 @@ assign i2c2_prdata = 0;
   wire inter_rtc_clk;
 
   wire io_host_reset;
+  wire io_host_diff_enable;
   wire clock_enable;
   wire sys_rstn_io;
   wire cpu_rstn_io;
@@ -1088,7 +1089,7 @@ assign i2c2_prdata = 0;
   wire xdma_link_up = pcie_lnk_sync[1];
 
   assign difftest_to_host_axis_ready = difftest_to_host_axis_ready_io & xdma_link_up;
-  assign difftest_to_host_axis_valid_io = difftest_to_host_axis_valid & xdma_link_up;
+  assign difftest_to_host_axis_valid_io = difftest_to_host_axis_valid & xdma_link_up & io_host_diff_enable;
 
   xdma_ep xdma_ep_i(
     .cpu_clk(sys_clk_i),
@@ -1153,18 +1154,19 @@ assign i2c2_prdata = 0;
       .io_axi_read_rvalid    (XDMA_AXI_LITE_rvalid),
       .io_axi_read_rready    (XDMA_AXI_LITE_rready),
 
+      .io_host_diff_enable   (io_host_diff_enable),
       .io_host_reset         (io_host_reset)
   );
 
   DifftestClockGate SOC_CLK_CTRL(
       .CK  (sys_clk_i),
-      .E   ((difftest_clock_enable & xdma_link_up )|| ~sys_rstn_io || ~cpu_rstn_io),
+      .E   ((difftest_clock_enable & xdma_link_up ) || ~io_host_diff_enable || ~sys_rstn_io || ~cpu_rstn_io),
       .Q   (inter_soc_clk)
   );
 
   DifftestClockGate RTC_CLK_CTRL(
       .CK  (tmclk),
-      .E   ((difftest_clock_enable & xdma_link_up) || ~sys_rstn_io || ~cpu_rstn_io ),
+      .E   ((difftest_clock_enable & xdma_link_up) || ~io_host_diff_enable || ~sys_rstn_io || ~cpu_rstn_io ),
       .Q   (inter_rtc_clk)
   );