From ce9cd0263a56fe7126b5d8e9d52b12cd08f16caf Mon Sep 17 00:00:00 2001
From: Yanqin Li <maxpicca@qq.com>
Date: Sun, 14 Dec 2025 01:30:57 +0800
Subject: [PATCH] chore: add some function for MemReqSource

---
 src/main/scala/utility/TLUtils/BusKeyField.scala | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/main/scala/utility/TLUtils/BusKeyField.scala b/src/main/scala/utility/TLUtils/BusKeyField.scala
index 22b8eab..7b4879d 100644
--- a/src/main/scala/utility/TLUtils/BusKeyField.scala
+++ b/src/main/scala/utility/TLUtils/BusKeyField.scala
@@ -47,6 +47,17 @@ object MemReqSource extends Enumeration {
 
   val reqSourceBits = log2Ceil(ReqSourceCount.id)
 
+  def isCPUReq(reqSource: UInt): Bool = {
+    reqSource === CPULoadData.id.U ||
+    reqSource === CPUStoreData.id.U ||
+    reqSource === CPUAtomicData.id.U
+  }
+
+  def isL1Prefetch(reqSource: UInt): Bool = {
+    reqSource === L1InstPrefetch.id.U ||
+    reqSource === L1DataPrefetch.id.U
+  }
+
   def isL2Prefetch(reqSource: UInt): Bool = {
     reqSource === Prefetch2L2BOP.id.U ||
     reqSource === Prefetch2L2PBOP.id.U ||