Change the DMA data bus access from 64b to 256b, to increase the bus performance

[rodmarfran]

An access width of 256b for the DMA was implemented, because it should improve the data bus performance. Need to be tested if it works properly to later check if the speed was improved.
This modification is implemented, in commit eef53d2, and synthesized as HW V21, in commit c17fe63.

Change Log:

• Changed the DMA bus width to 256b and it access type to aligned.

Remaining:

• @ericolucasm to test the HW V21 to check the modification works.

Test Procedure:

• Do a full normal test with the SimuCam and verify if all 638 packets are being transmitted per CCD [if not, a bug was introduced in the system. If all 638 packets are transmitted, the issue can be closed].

Hardware Programming File:

• SimuCam_V21_20190223_HW.sof: https://github.com/NSEE/SimuCam_Development/blob/c17fe630f9f1e0e014f4a27919609a23bf87a99c/G3U_HW_V02_2GB/Quartus_Project/output_files/SimuCam_V21_20190223_HW..sof