Port to DE0-Nano-soc?

[pfennema]

Hi all,

I have a little issue on how to change the odd_gen.cpp to emit verilog code which fits into a DE0-Nano-Soc uses a smaller FPGA and the DE10-nano generated verilog code does not fit as the number of ram blocks and combinational logic is too small. Do you have an idea what needs to be changed to resize?