verilog_code/myFIFO_tb at master · Mayank-Parasar/verilog_code · GitHub

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#! /usr/bin/vvp
:ivl_version "0.9.7 " "(v0_9_7)";
:vpi_time_precision + 0;
:vpi_module "system";
:vpi_module "v2005_math";
:vpi_module "va_math";
S_0xb84690 .scope module, "myFIFO_tb" "myFIFO_tb" 2 4;
 .timescale 0 0;
v0xbcfa30_0 .var "clock", 0 0;
v0xbcfad0_0 .var "data_in", 3 0;
v0xbcfb80_0 .net "data_out", 3 0, v0xbcf6c0_0; 1 drivers
v0xbcfc30_0 .var "reset", 0 0;
S_0xb84780 .scope module, "fifo" "myFIFO" 2 37, 3 6, S_0xb84690;
 .timescale 0 0;
v0xb84870_0 .net "clk", 0 0, v0xbcfa30_0; 1 drivers
v0xbcf620_0 .net "data_in", 3 0, v0xbcfad0_0; 1 drivers
v0xbcf6c0_0 .var "data_out", 3 0;
v0xbcf760_0 .var "first", 3 0;
v0xbcf810_0 .net "rst", 0 0, v0xbcfc30_0; 1 drivers
v0xbcf8b0_0 .var "second", 3 0;
v0xbcf990_0 .var "third", 3 0;
E_0xb96ba0 .event posedge, v0xbcf810_0, v0xb84870_0;
    .scope S_0xb84780;
T_0 ;
    %wait E_0xb96ba0;
    %load/v 8, v0xbcf810_0, 1;
    %jmp/0xz  T_0.0, 8;
    %ix/load 0, 4, 0;
    %assign/v0 v0xbcf760_0, 0, 0;
    %ix/load 0, 4, 0;
    %assign/v0 v0xbcf8b0_0, 0, 0;
    %ix/load 0, 4, 0;
    %assign/v0 v0xbcf990_0, 0, 0;
    %ix/load 0, 4, 0;
    %assign/v0 v0xbcf6c0_0, 0, 0;
    %jmp T_0.1;
T_0.0 ;
    %load/v 8, v0xbcf620_0, 4;
    %ix/load 0, 4, 0;
    %assign/v0 v0xbcf760_0, 0, 8;
    %load/v 8, v0xbcf760_0, 4;
    %ix/load 0, 4, 0;
    %assign/v0 v0xbcf8b0_0, 0, 8;
    %load/v 8, v0xbcf8b0_0, 4;
    %ix/load 0, 4, 0;
    %assign/v0 v0xbcf990_0, 0, 8;
    %load/v 8, v0xbcf990_0, 4;
    %ix/load 0, 4, 0;
    %assign/v0 v0xbcf6c0_0, 0, 8;
T_0.1 ;
    %jmp T_0;
    .thread T_0;
    .scope S_0xb84690;
T_1 ;
    %vpi_call 2 16 "$dumpfile", "myfifo.vcd";
    %vpi_call 2 17 "$dumpvars", 1'sb0, S_0xb84690;
    %ix/load 0, 1, 0;
    %assign/v0 v0xbcfc30_0, 0, 0;
    %ix/load 0, 1, 0;
    %assign/v0 v0xbcfa30_0, 0, 0;
    %ix/load 0, 4, 0;
    %assign/v0 v0xbcfad0_0, 0, 0;
    %delay 5, 0;
    %ix/load 0, 1, 0;
    %assign/v0 v0xbcfc30_0, 0, 1;
    %delay 7, 0;
    %ix/load 0, 1, 0;
    %assign/v0 v0xbcfc30_0, 0, 0;
    %delay 8, 0;
    %movi 8, 11, 4;
    %ix/load 0, 4, 0;
    %assign/v0 v0xbcfad0_0, 0, 8;
    %delay 10, 0;
    %movi 8, 10, 4;
    %ix/load 0, 4, 0;
    %assign/v0 v0xbcfad0_0, 0, 8;
    %delay 12, 0;
    %movi 8, 8, 4;
    %ix/load 0, 4, 0;
    %assign/v0 v0xbcfad0_0, 0, 8;
    %delay 15, 0;
    %vpi_call 2 27 "$finish";
    %end;
    .thread T_1;
    .scope S_0xb84690;
T_2 ;
    %delay 1, 0;
    %load/v 8, v0xbcfa30_0, 1;
    %inv 8, 1;
    %set/v v0xbcfa30_0, 8, 1;
    %vpi_call 2 32 "$display", "+---------------------------------------------+";
    %jmp T_2;
    .thread T_2;
    .scope S_0xb84690;
T_3 ;
    %vpi_call 2 46 "$display", "+--------------------------------------------------------------------------+";
    %vpi_call 2 47 "$display", "|clock|reset|data_in|first|second|third|data_out|";
    %vpi_call 2 48 "$display", "+--------------------------------------------------------------------------+";
    %vpi_call 2 49 "$monitor", "|  %h  |  %h  |  %h  |  %h  |  %h  |  %h  |  %h  |", v0xbcfa30_0, v0xbcfc30_0, v0xbcfad0_0, v0xbcf760_0, v0xbcf8b0_0, v0xbcf990_0, v0xbcf6c0_0;
    %end;
    .thread T_3;
# The file index is used to find the file name in the following table.
:file_names 4;
    "N/A";
    "<interactive>";
    "myFIFO_tb.v";
    "./myFIFO.v";