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Running: /CMC/tools/xilinx/13.3/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -o /media/0AE8-77F0/Ryerson EE Account/COE758/CacheProject/CacheControllerProject/CACHE2/TEST_isim_beh.exe -prj /media/0AE8-77F0/Ryerson EE Account/COE758/CacheProject/CacheControllerProject/CACHE2/TEST_beh.prj work.TEST
ISim O.76xd (signature 0x8ddf5b5d)
Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 16
Determining compilation order of HDL files
Parsing VHDL file "/media/0AE8-77F0/Ryerson EE Account/COE758/CacheProject/CacheControllerProject/CACHE2/ipcore_dir/SRAM.vhd" into library work
Parsing VHDL file "/media/0AE8-77F0/Ryerson EE Account/COE758/CacheProject/CacheControllerProject/CACHE2/SDRAMController.vhd" into library work
Parsing VHDL file "/media/0AE8-77F0/Ryerson EE Account/COE758/CacheProject/CacheControllerProject/CACHE2/CPU_gen.vhd" into library work
Parsing VHDL file "/media/0AE8-77F0/Ryerson EE Account/COE758/CacheProject/CacheControllerProject/CACHE2/CacheController.vhd" into library work
Parsing VHDL file "/media/0AE8-77F0/Ryerson EE Account/COE758/CacheProject/CacheControllerProject/CACHE2/TEST.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 104064 KB
Fuse CPU Usage: 1000 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package numeric_std
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling architecture behavioral of entity CPU_gen [cpu_gen_default]
Compiling architecture behavioral of entity SDRAMController [sdramcontroller_default]
Compiling package textio
Compiling package std_logic_textio
Compiling architecture output_stage_behavioral of entity BLK_MEM_GEN_V6_2_output_stage [\BLK_MEM_GEN_V6_2_output_stage("...]
Compiling architecture softecc_output_reg_stage_behavioral of entity BLK_MEM_GEN_V6_2_softecc_output_reg_stage [\BLK_MEM_GEN_V6_2_softecc_output...]
Compiling architecture mem_module_behavioral of entity BLK_MEM_GEN_V6_2_mem_module [\BLK_MEM_GEN_V6_2_mem_module("bl...]
Compiling architecture behavioral of entity BLK_MEM_GEN_V6_2 [\BLK_MEM_GEN_V6_2("blk_mem_gen_v...]
Compiling architecture sram_a of entity SRAM [sram_default]
Compiling architecture behavioral of entity CacheController [cachecontroller_default]
Compiling architecture behavior of entity test
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 24 VHDL Units
Built simulation executable /media/0AE8-77F0/Ryerson EE Account/COE758/CacheProject/CacheControllerProject/CACHE2/TEST_isim_beh.exe
Fuse Memory Usage: 1206584 KB
Fuse CPU Usage: 1260 ms
GCC CPU Usage: 3880 ms