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--------------------------------------------------------------------------------
Release 13.3 Trace (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
/CMC/tools/xilinx/13.3/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3
-s 5 -n 3 -fastpaths -xml CacheController.twx CacheController.ncd -o
CacheController.twr CacheController.pcf -ucf CacheController.ucf
Design file: CacheController.ncd
Physical constraint file: CacheController.pcf
Device,package,speed: xc3s500e,fg320,-5 (PRODUCTION 1.27 2011-10-03)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter
value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
'Phase Error' calculations, these terms will be zero in the Clock
Uncertainty calculation. Please make appropriate modification to
SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
Error.
================================================================================
Timing constraint: PATH "TS_D2_TO_T2_path" TIG;
3 paths analyzed, 3 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
--------------------------------------------------------------------------------
Paths for end point myILA/U0/I_YES_D.U_ILA/U_STAT/U_TDO (SLICE_X50Y64.G3), 1 path
--------------------------------------------------------------------------------
Delay (setup path): 5.713ns (data path - clock path skew + uncertainty)
Source: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
Destination: myILA/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
Data Path Delay: 5.713ns (Levels of Logic = 4)
Clock Path Skew: 0.000ns
Source Clock: control0<13> falling
Destination Clock: control0<0> rising
Clock Uncertainty: 0.000ns
Maximum Data Path: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC to myILA/U0/I_YES_D.U_ILA/U_STAT/U_TDO
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X50Y72.YQ Tcklo 0.646 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC
SLICE_X51Y72.F2 net (fanout=1) 0.401 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
SLICE_X51Y72.X Tilo 0.612 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_D0
myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat1
SLICE_X49Y67.G4 net (fanout=2) 0.521 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat
SLICE_X49Y67.X Tif5x 0.890 myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_F
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91
SLICE_X50Y61.G4 net (fanout=1) 0.630 myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91
SLICE_X50Y61.X Tif5x 1.000 myILA/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5
SLICE_X50Y64.G3 net (fanout=1) 0.237 myILA/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
SLICE_X50Y64.CLK Tgck 0.776 myILA/U0/I_YES_D.U_ILA/iSTAT_DOUT
myILA/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O87
myILA/U0/I_YES_D.U_ILA/U_STAT/U_TDO
------------------------------------------------- ---------------------------
Total 5.713ns (3.924ns logic, 1.789ns route)
(68.7% logic, 31.3% route)
--------------------------------------------------------------------------------
Paths for end point myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDPE (SLICE_X51Y73.BY), 1 path
--------------------------------------------------------------------------------
Delay (setup path): 2.334ns (data path - clock path skew + uncertainty)
Source: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
Destination: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDPE (FF)
Data Path Delay: 2.334ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: control0<13> falling
Destination Clock: control0<0> rising
Clock Uncertainty: 0.000ns
Maximum Data Path: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC to myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDPE
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X50Y72.YQ Tcklo 0.646 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC
SLICE_X51Y72.F2 net (fanout=1) 0.401 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
SLICE_X51Y72.X Tilo 0.612 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_D0
myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat1
SLICE_X51Y73.BY net (fanout=2) 0.361 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat
SLICE_X51Y73.CLK Tdick 0.314 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_D1
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDPE
------------------------------------------------- ---------------------------
Total 2.334ns (1.572ns logic, 0.762ns route)
(67.4% logic, 32.6% route)
--------------------------------------------------------------------------------
Paths for end point myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDCE (SLICE_X51Y72.F2), 1 path
--------------------------------------------------------------------------------
Delay (setup path): 1.775ns (data path - clock path skew + uncertainty)
Source: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
Destination: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDCE (FF)
Data Path Delay: 1.775ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: control0<13> falling
Destination Clock: control0<0> rising
Clock Uncertainty: 0.000ns
Maximum Data Path: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC to myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDCE
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X50Y72.YQ Tcklo 0.646 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC
SLICE_X51Y72.F2 net (fanout=1) 0.401 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
SLICE_X51Y72.CLK Tfck 0.728 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_D0
myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat1
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDCE
------------------------------------------------- ---------------------------
Total 1.775ns (1.374ns logic, 0.401ns route)
(77.4% logic, 22.6% route)
--------------------------------------------------------------------------------
Hold Paths: PATH "TS_D2_TO_T2_path" TIG;
--------------------------------------------------------------------------------
Paths for end point myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDCE (SLICE_X51Y72.F2), 1 path
--------------------------------------------------------------------------------
Delay (hold path): 1.286ns (datapath - clock path skew - uncertainty)
Source: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
Destination: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDCE (FF)
Data Path Delay: 1.286ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: control0<13> falling
Destination Clock: control0<0> rising
Clock Uncertainty: 0.000ns
Minimum Data Path: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC to myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDCE
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X50Y72.YQ Tcklo 0.517 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC
SLICE_X51Y72.F2 net (fanout=1) 0.321 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
SLICE_X51Y72.CLK Tckf (-Th) -0.448 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_D0
myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat1
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDCE
------------------------------------------------- ---------------------------
Total 1.286ns (0.965ns logic, 0.321ns route)
(75.0% logic, 25.0% route)
--------------------------------------------------------------------------------
Paths for end point myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDPE (SLICE_X51Y73.BY), 1 path
--------------------------------------------------------------------------------
Delay (hold path): 1.734ns (datapath - clock path skew - uncertainty)
Source: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
Destination: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDPE (FF)
Data Path Delay: 1.734ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: control0<13> falling
Destination Clock: control0<0> rising
Clock Uncertainty: 0.000ns
Minimum Data Path: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC to myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDPE
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X50Y72.YQ Tcklo 0.517 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC
SLICE_X51Y72.F2 net (fanout=1) 0.321 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
SLICE_X51Y72.X Tilo 0.490 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_D0
myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat1
SLICE_X51Y73.BY net (fanout=2) 0.289 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat
SLICE_X51Y73.CLK Tckdi (-Th) -0.117 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_D1
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_FDPE
------------------------------------------------- ---------------------------
Total 1.734ns (1.124ns logic, 0.610ns route)
(64.8% logic, 35.2% route)
--------------------------------------------------------------------------------
Paths for end point myILA/U0/I_YES_D.U_ILA/U_STAT/U_TDO (SLICE_X50Y64.G3), 1 path
--------------------------------------------------------------------------------
Delay (hold path): 4.438ns (datapath - clock path skew - uncertainty)
Source: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
Destination: myILA/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
Data Path Delay: 4.438ns (Levels of Logic = 4)
Clock Path Skew: 0.000ns
Source Clock: control0<13> falling
Destination Clock: control0<0> rising
Clock Uncertainty: 0.000ns
Minimum Data Path: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC to myILA/U0/I_YES_D.U_ILA/U_STAT/U_TDO
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X50Y72.YQ Tcklo 0.517 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC
SLICE_X51Y72.F2 net (fanout=1) 0.321 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_SEL
SLICE_X51Y72.X Tilo 0.490 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_D0
myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat1
SLICE_X49Y67.G4 net (fanout=2) 0.417 myILA/U0/I_YES_D.U_ILA/U_STAT/DIRTY_dstat
SLICE_X49Y67.X Tif5x 0.712 myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_F
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91
SLICE_X50Y61.G4 net (fanout=1) 0.504 myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91
SLICE_X50Y61.X Tif5x 0.800 myILA/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4
myILA/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5
SLICE_X50Y64.G3 net (fanout=1) 0.190 myILA/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
SLICE_X50Y64.CLK Tckg (-Th) -0.487 myILA/U0/I_YES_D.U_ILA/iSTAT_DOUT
myILA/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O87
myILA/U0/I_YES_D.U_ILA/U_STAT/U_TDO
------------------------------------------------- ---------------------------
Total 4.438ns (3.006ns logic, 1.432ns route)
(67.7% logic, 32.3% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: PATH "TS_J2_TO_D2_path" TIG;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: PATH "TS_J3_TO_D2_path" TIG;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: PATH "TS_J4_TO_D2_path" TIG;
11 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
--------------------------------------------------------------------------------
Paths for end point myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (SLICE_X50Y72.CLK), 11 paths
--------------------------------------------------------------------------------
Delay (setup path): 5.229ns (data path)
Source: myIcon/U0/U_ICON/U_CMD/G_TARGET[7].I_NE0.U_TARGET (FF)
Destination: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
Data Path Delay: 5.229ns (Levels of Logic = 2)
Source Clock: control0<0> rising
Maximum Data Path: myIcon/U0/U_ICON/U_CMD/G_TARGET[7].I_NE0.U_TARGET to myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X60Y88.XQ Tcko 0.515 myIcon/U0/U_ICON/iCOMMAND_GRP<1>
myIcon/U0/U_ICON/U_CMD/G_TARGET[7].I_NE0.U_TARGET
SLICE_X52Y80.G2 net (fanout=4) 1.443 myIcon/U0/U_ICON/iCOMMAND_GRP<1>
SLICE_X52Y80.Y Tilo 0.660 control0<4>
myIcon/U0/U_ICON/U_CTRL_OUT/U_CMDGRP0
SLICE_X55Y76.G2 net (fanout=16) 0.755 myIcon/U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL<0>
SLICE_X55Y76.Y Tilo 0.612 myILA/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/din_latched
myIcon/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE
SLICE_X50Y72.CLK net (fanout=5) 1.244 control0<13>
------------------------------------------------- ---------------------------
Total 5.229ns (1.787ns logic, 3.442ns route)
(34.2% logic, 65.8% route)
--------------------------------------------------------------------------------
Delay (setup path): 5.220ns (data path)
Source: myIcon/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET (FF)
Destination: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
Data Path Delay: 5.220ns (Levels of Logic = 2)
Source Clock: control0<0> rising
Maximum Data Path: myIcon/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET to myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X65Y88.YQ Tcko 0.511 myIcon/U0/U_ICON/U_CMD/iTARGET<11>
myIcon/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET
SLICE_X55Y79.F3 net (fanout=17) 1.938 myIcon/U0/U_ICON/U_CMD/iTARGET<10>
SLICE_X55Y79.X Tilo 0.612 myIcon/U0/U_ICON/iCOMMAND_SEL<9>
myIcon/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[9].U_LUT
SLICE_X55Y76.G4 net (fanout=1) 0.303 myIcon/U0/U_ICON/iCOMMAND_SEL<9>
SLICE_X55Y76.Y Tilo 0.612 myILA/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/din_latched
myIcon/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE
SLICE_X50Y72.CLK net (fanout=5) 1.244 control0<13>
------------------------------------------------- ---------------------------
Total 5.220ns (1.735ns logic, 3.485ns route)
(33.2% logic, 66.8% route)
--------------------------------------------------------------------------------
Delay (setup path): 5.137ns (data path)
Source: myIcon/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET (FF)
Destination: myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
Data Path Delay: 5.137ns (Levels of Logic = 2)
Source Clock: control0<0> rising
Maximum Data Path: myIcon/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET to myILA/U0/I_YES_D.U_ILA/U_STAT/U_DIRTY_LDC
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X65Y88.XQ Tcko 0.514 myIcon/U0/U_ICON/U_CMD/iTARGET<11>
myIcon/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET
SLICE_X55Y79.F1 net (fanout=17) 1.852 myIcon/U0/U_ICON/U_CMD/iTARGET<11>
SLICE_X55Y79.X Tilo 0.612 myIcon/U0/U_ICON/iCOMMAND_SEL<9>
myIcon/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[9].U_LUT
SLICE_X55Y76.G4 net (fanout=1) 0.303 myIcon/U0/U_ICON/iCOMMAND_SEL<9>
SLICE_X55Y76.Y Tilo 0.612 myILA/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/din_latched
myIcon/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE
SLICE_X50Y72.CLK net (fanout=5) 1.244 control0<13>
------------------------------------------------- ---------------------------
Total 5.137ns (1.738ns logic, 3.399ns route)
(33.8% logic, 66.2% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "U_CLK"
15 ns;
1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Maximum delay is 1.425ns.
--------------------------------------------------------------------------------
Paths for end point myIcon/U0/U_ICON/U_iDATA_CMD (SLICE_X66Y91.BY), 1 path
--------------------------------------------------------------------------------
Slack (setup paths): 13.575ns (requirement - (data path - clock path skew + uncertainty))
Source: myIcon/U0/U_ICON/U_iDATA_CMD (FF)
Destination: myIcon/U0/U_ICON/U_iDATA_CMD (FF)
Requirement: 15.000ns
Data Path Delay: 1.425ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: myIcon/U0/iUPDATE_OUT rising
Destination Clock: myIcon/U0/iUPDATE_OUT rising
Clock Uncertainty: 0.000ns
Maximum Data Path: myIcon/U0/U_ICON/U_iDATA_CMD to myIcon/U0/U_ICON/U_iDATA_CMD
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X66Y91.YQ Tcko 0.567 myIcon/U0/U_ICON/iDATA_CMD
myIcon/U0/U_ICON/U_iDATA_CMD
SLICE_X66Y91.BY net (fanout=7) 0.525 myIcon/U0/U_ICON/iDATA_CMD
SLICE_X66Y91.CLK Tdick 0.333 myIcon/U0/U_ICON/iDATA_CMD
myIcon/U0/U_ICON/U_iDATA_CMD
------------------------------------------------- ---------------------------
Total 1.425ns (0.900ns logic, 0.525ns route)
(63.2% logic, 36.8% route)
--------------------------------------------------------------------------------
Fastest Paths: TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "U_CLK" 15 ns;
--------------------------------------------------------------------------------
Paths for end point myIcon/U0/U_ICON/U_iDATA_CMD (SLICE_X66Y91.BY), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 1.006ns (requirement - (clock path skew + uncertainty - data path))
Source: myIcon/U0/U_ICON/U_iDATA_CMD (FF)
Destination: myIcon/U0/U_ICON/U_iDATA_CMD (FF)
Requirement: 0.000ns
Data Path Delay: 1.006ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: myIcon/U0/iUPDATE_OUT rising
Destination Clock: myIcon/U0/iUPDATE_OUT rising
Clock Uncertainty: 0.000ns
Minimum Data Path: myIcon/U0/U_ICON/U_iDATA_CMD to myIcon/U0/U_ICON/U_iDATA_CMD
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X66Y91.YQ Tcko 0.454 myIcon/U0/U_ICON/iDATA_CMD
myIcon/U0/U_ICON/U_iDATA_CMD
SLICE_X66Y91.BY net (fanout=7) 0.420 myIcon/U0/U_ICON/iDATA_CMD
SLICE_X66Y91.CLK Tckdi (-Th) -0.132 myIcon/U0/U_ICON/iDATA_CMD
myIcon/U0/U_ICON/U_iDATA_CMD
------------------------------------------------- ---------------------------
Total 1.006ns (0.586ns logic, 0.420ns route)
(58.3% logic, 41.7% route)
--------------------------------------------------------------------------------
All constraints were met.
Data Sheet report:
-----------------
No constraints were found to generate data for the Data Sheet Report section.
Use the Advanced Analysis (-a) option or generate global constraints for each
clock, its pad to setup and clock to pad paths, and a pad to pad constraint.
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 15 paths, 0 nets, and 22 connections
Design statistics:
Minimum period: 1.425ns{1} (Maximum frequency: 701.754MHz)
Maximum path delay from/to any node: 1.425ns
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Tue Oct 31 11:46:37 2017
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 383 MB