Support of all Verilog syntax

[LiamSkirrow]

This ticket refers to all the possible ways that a module can be declared or instantiated. I would like v0.2.0 to allow for the recognition of the following cases. (Refer to ticket #15)

ibex_ex_block #(
    .RV32M          (RV32M),
    .RV32B          (RV32B),
    .BranchTargetALU(BranchTargetALU)
  ) ex_block_i (
    .clk_i (clk_i),
    .rst_ni(rst_ni),

module ibex_core import ibex_pkg::*; #(

The above are edge cases that verilogtree currently doesn't account for. It would be nice to have verilogtree support all syntactic edge-cases for instantiating and declaring modules so that it 'just works' on pretty much any syntactically correct Verilog.