The Verilog parsing in v0.1.0 is extremely basic, and amounts to reading line by line and performing regex matching. This was ok as a starting point but became a nightmare for the more complex syntax constructs that Verilog employs. For example the weird module-in-package thing that the Ibex IP does.
Therefore it would be nice to have a small and separate project/repo that encapsulates some useful parsing stuff in C++. For example, a function/method like: bool findNext(char c), that determines whether the char c is present in the remainder of the file. This could be used to determine some useful stuff. Some slightly more specific parsing code that's more oriented towards verilogtree would be useful, but this separate repo could eventually grow into a slightly more comprehensive and general text parsing library in C++. Making it as generic (grammar/syntax wise) would be the ultimate goal.
This also means that hopefully we could cover the entirety of the Verilog/SystemVerilog languages to cover all possible valid module declarations and instantiations for the purposes of verilogtree.
The Verilog parsing in v0.1.0 is extremely basic, and amounts to reading line by line and performing regex matching. This was ok as a starting point but became a nightmare for the more complex syntax constructs that Verilog employs. For example the weird module-in-package thing that the Ibex IP does.
Therefore it would be nice to have a small and separate project/repo that encapsulates some useful parsing stuff in C++. For example, a function/method like:
bool findNext(char c), that determines whether thechar cis present in the remainder of the file. This could be used to determine some useful stuff. Some slightly more specific parsing code that's more oriented towards verilogtree would be useful, but this separate repo could eventually grow into a slightly more comprehensive and general text parsing library in C++. Making it as generic (grammar/syntax wise) would be the ultimate goal.This also means that hopefully we could cover the entirety of the Verilog/SystemVerilog languages to cover all possible valid module declarations and instantiations for the purposes of verilogtree.