Replace Verilog parsing with Verilator

[LiamSkirrow]

Verilator can generate XML output of a Verilog design (while also performing syntax checking of the Verilog itself), therefore ripping out verilogtree's existing parsing code and simply using Verilator's own parser probably makes the most sense going forward.

Also, doing this means that all the Verilog edge cases that I left out should now be covered and complete, so verilogtree should work on all syntactically correct Verilog.

Implementing this would mean that verilogtree would instead need to parse the Verilator-generated XML to figure out the hierarchy. So it's really only the parseRtl() function that would need rewriting, with everything else staying largely in tact.

[LiamSkirrow]

I'm having second thoughts on this, I shouldn't be compiling the entire source code using Verilator just to do something simple like printing out a Verilog hierarchy...

Also, Verilator seems to require only a single top level module rather than supporting arbitrarily many top levels. I think instead I'll just stick with my existing Verilog parsing, as painful as it is.