In order to implement the stalling capability necessary in order to halt the pipeline when performing a memory read/write for instance, it's possible to have the synthesis tool infer an EN pin on flip flops which can be used to halt the state of the CPU. If every single flop has an EN pin that is driven by the same HALT_N signal then the state of the CPU will be preserved for an arbitrary number of clock cycles if/when the HALT_N pin is asserted. The memories that I infer can drive the halt signal to stall the CPU's pipeline when performing a memory access (at the respective stage of the 5 stage pipeline).
In order to implement the stalling capability necessary in order to halt the pipeline when performing a memory read/write for instance, it's possible to have the synthesis tool infer an EN pin on flip flops which can be used to halt the state of the CPU. If every single flop has an EN pin that is driven by the same HALT_N signal then the state of the CPU will be preserved for an arbitrary number of clock cycles if/when the HALT_N pin is asserted. The memories that I infer can drive the halt signal to stall the CPU's pipeline when performing a memory access (at the respective stage of the 5 stage pipeline).