Possible improvements

[furrtek]

Hello,

I just finished reverse-engineering a silicon die shot of BUSTER.
There are a few discrepancies between the extracted schematics and your verilog code.
I'm not familiar with the Amiga so I can't really tell if those are from modifications needed for the CPLD to work, or consequences of guessing the logic by observing the signals ?

https://github.com/furrtek/SiliconRE/tree/master/Commodore/CSG5721

[LIV2]

Hi @furrtek!

The logic was written based off observed behaviour and based on the pal equations from the German A2000 which was pre-Buster

It's great to see the reverse engineered schematics! I will study them and correct the Bluster logic to match soon. (I recently moved countries and my Amigas are still in transit)

[LIV2]

After looking for a bit I've already noticed some small differences that will be easy for me to fix, and one expected deviation that is needed due to the faster timing of the CPLD.

1. Chipram address should go up to $1FFFFF

2. Reserved range should start at $B80000 not $A00000
   

   Bluster/RTL/Bluster.v

   Lines 76 to 77 in d5636e6

   	ADDR[23:21] == 3'b000 | // $000000-0FFFFF - Chip RAM
   	ADDR[23:21] == 3'b101 | // $A00000-BFFFFF - RESERVED

3. Collision circuit doesn't work as expected, XORing all inputs will not have the desired result (i.e an odd number of SLAVEs would not trigger a collision)
   

   Bluster/RTL/Bluster.v

   Line 84 in d5636e6

   assign nocollision = (!SLV[5] ^ !SLV[4] ^ !SLV[3] ^ !SLV[2] ^ !SLV[1] ^ mainboard) | (SLV[5] & SLV[4] & SLV[3] & SLV[2] & SLV[1] & !mainboard);

4. DOE hack - An expected deviation from original - ASn buffered as DASn to deal with different timings of CPLD
   

   Bluster/RTL/Bluster.v

   Lines 90 to 92 in d5636e6

   	// Dirty hack
   	// Add a delay to ASn so that DBOE/DOE are held a little longer into S7
   	(*KEEP = "true" *) BUF ASn_buf1 (.I(ASn),.O(DASn));