me.json

{
    "user": {
        "name": "Kevin Palani",
        "phone": "408-893-0826",
        "email": "kevinrp2@illinois.edu",
        "giturl": "https://github.com/KevinPal",
        "gitnice": "github.com/KevinPal",
        "address": "San Jose, California"
    },
    "academics": {
        "relevant_coursework": {
            "cs": ["Computer Architecture", "OS", "SOC", "FPGAs", "Robotics", "Algorithms", "Data Structures"]
        },
        "school": "University of Illinois Urbana Champaign (UIUC)",
        "degree": "Bachelor of Science in Computer Engineering",
        "year": "Senior",
        "gradyear": "May 2022"
    },
    "career": {
        "experience": [
            {
                "role": "Software Engineering Intern",
                "company": "Qualcomm",
                "date": "May 2021 - August 2021",
                "description": "Created post-linker scripts which extracted information from an embedded image and replaced them with unique hashes. Original information could be recovered by talking to a connected debugging computer. Reduced image size by about 5MB by enhancing how hashes were used and performing assembly level improvements. "
            },
            {
                "role": "Software Engineering Intern",
                "company": "Quantum Corp",
                "date": "May 2019 - June 2020",
                "description": "Worked on a set of services which allows support personnel to monitor and repair on-premise appliances from the cloud. Used transient Docker containers to facilitate secure connections between support personnel and product through the cloud, along with additions to the web UI and Postgres database to support the changes."
            },
            {
                "role": "Course Assistant",
                "company": "UIUC Staff",
                "date": "January 2020 - Present",
                "description": "Working as a course assistant for a FPGA class, where I lead office hours. I answer students questions related to SystemVerilog and digital design, ranging from understanding syntax to design trade-offs."

            },
            {
                "role": "Software Engineering Intern",
                "company": "Nebbiolo Technologies",
                "date": "June - August 2018",
                "description": "Extended the data analysis pipeline to allow for distributed analysis and computation, and upgraded the data visualizer to remotely view graphs. Also significantly reduced disk usage by optimizing Dockerfiles."

            }
        ],
        "skillsets": [
            {
                "name": "Programming Languages",
                "skills": ["SystemVerilog", "Verilog", "Python", "C/C\\verb!++!", "Java", "php", "Javascript", "Go" ]
            },
            {
                "name": "Tools/Frameworks",
                "skills": ["Vivado", "Quartus", "AWS", "Linux", "Docker", "SQL", "git", "\\LaTeX", "Jira", "Microsoft Office"]
            }
        ],
        "projects": [
            {
                "title": "RISC-V Processor",
                "date": "October - December 2020",
                "description": "Designed and implemented a pipelined processor in SystemVerilog that supported the RV32IM instruction set. Features includes pipelined set associative L1 caches, victim caches, stride based prefetching, local branch prediction, a branch target buffer, a return address stack, and a Wallace Tree multiplier."
            },
            {
                "title": "Operating System from scratch",
                "date": "March - May 2020",
                "description": "Led a team of 4 students to develop an operating system from the ground up in C. Included dynamic memory support, dynamic processes, a GUI with mouse support and multiple terminals, memory and cpu virtualisation, interrupt support, custom drivers, user programs, and multithreading."
            },
            {
                "title": "3D Renderer in SystemVerilog on an FPGA",
                "date": "November - December 2019",
                "description": "Designed and developed a GPU on a CycloneIV FPGA capable of arbitrary texured 3D rendering, and used it within an Avalon SOC along with the Intel NIOS II processor to build a game in which the user could move through and modify a 3D world. Developed with Quartus EDA tool and ModelSim simulator."
            }
        ]
    }
}