RVOS/riscv.h at master · GartonChan/RVOS · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
#ifndef __RISCV_H__
#define __RISCV_H__

#include "types.h"

/* ---------- RISC-V Architure and Assembly ---------- */

/*
 * ---------- Context ----------
 * 32 GP-Registers: x0 ~ x31
 * Append pc(epc) for preemitive
 */
struct context {
    /* ignore x0 */
    reg_t ra;
    reg_t sp;
    reg_t gp;
    reg_t tp;
    reg_t t0;
    reg_t t1;
    reg_t t2;
    reg_t s0;
    reg_t s1;
    reg_t a0;
    reg_t a1;
    reg_t a2;
    reg_t a3;
    reg_t a4;
    reg_t a5;
    reg_t a6;
    reg_t a7;
	reg_t s2;
	reg_t s3;
	reg_t s4;
	reg_t s5;
	reg_t s6;
	reg_t s7;
	reg_t s8;
	reg_t s9;
	reg_t s10;
	reg_t s11;
	reg_t t3;
	reg_t t4;
	reg_t t5;
	reg_t t6;
    /* upon is trap frame*/

    /* to store the epc in next schedule cycle before the trap */
    reg_t pc;
};

/*
 * ref: https://github.com/mit-pdos/xv6-riscv/blob/riscv/kernel/riscv.h
 */
static inline reg_t r_tp()
{
    reg_t x;
    asm volatile("mv %0, tp" : "=r" (x));
    return x;
}

/* To tell which hart is this */
static inline reg_t r_mhartid()
{
    reg_t x;
    asm volatile("csrr %0, mhartid" : "=r" (x));
    return x;
}

/* Machine Status Register, mstatus */
#define MSTATUS_MPP (3 << 11)
#define MSTATUS_SPP (1 << 8)

#define MSTATUS_MPIE (1 << 7)
#define MSTATUS_SPIE (1 << 5)
#define MSTATUS_UPIE (1 << 4)

#define MSTATUS_MIE (1 << 3)
#define MSTATUS_SIE (1 << 1)
#define MSTATUS_UIE (1 << 0)

static inline reg_t r_mstatus()
{
    reg_t x;
    asm volatile("csrr %0, mstatus" : "=r" (x));
    return x;
}

static inline void w_mstatus(reg_t x)
{
    asm volatile("csrw mstatus, %0" : : "r" (x));
}

/*
 * Machine exception program counter
 * holds the instruction address to
 * which a return from exception will go
 */
static inline void w_mepc(reg_t x)
{
    asm volatile("csrw mepc, %0" : : "r" (x));
}

static inline reg_t r_mepc()
{
    reg_t x;
    asm volatile("csrr %0, mepc" : "=r" (x));
    return x;
}

/* Machine Scratch register for early trap handler */
static inline void w_mscratch(reg_t x)
{
    asm volatile("csrw mscratch, %0" : : "r" (x));
}

/* Machine-mode Trap Vector */
static inline void w_mtvec(reg_t x)
{
    asm volatile("csrw mtvec, %0" : : "r" (x));
}

/* Machine-mode Interrupt Enable*/
#define MIE_MEIE (1 << 11) /* external */
#define MIE_MTIE (1 << 7)  /* timer */
#define MIE_MSIE (1 << 3)  /* software */

static inline reg_t r_mie()
{
    reg_t x;
    asm volatile("csrr %0, mie" : "=r" (x));
    return x;
}

static inline void w_mie(reg_t x)
{
    asm volatile("csrw mie, %0" : : "r" (x));
}

static inline reg_t r_mcause()
{
    reg_t x;
    asm volatile("csrr %0, mcause" : "=r" (x));
    return x;
}

#endif  /* __RISCV_H__ */