In synchronous processes only Clock should be in sensitivity list

[tmeissner]

Maybe it's only a copy & paste issue, but there are various VHDL units, where more than the clock signal is in the sensitivity list but the process is synchron and should only be sensitive to Clock. For example in mem_controller.vhd:

    process (I_clk, I_execute)
    begin
        if rising_edge(I_clk) then
            if I_reset = '1' then
                we <= '0';
                cmd <= '0';
                state <= 0;
            elsif state = 0 and I_execute = '1' and MEM_I_ready = '1' then
                we <= I_dataWe;
                addr <= I_address;
                indata <= I_data;
                byteEnable <= I_dataByteEn;
                cmd <= '1';
                O_dataReady <= '0';
                if I_dataWe = '0' then
                    -- read
                    state <= 1;
                else
                    state <= 2;-- write
                end if;
            elsif state = 1 then
                cmd <= '0';
                if MEM_I_dataReady = '1' then
                    O_dataReady <= '1';
                    state <= 2;
                end if;
            elsif state = 2 then
                cmd <= '0';
                state <= 0;
                O_dataReady <= '0';
            end if;
        end if;
    end process;

The line process (I_clk, I_execute) should be changed toprocess (I_clk). This makes no difference for synthesis, but for simulation, because the process is activated every time if one of the signals in the sensitivity list are active. But in case of synchronous processes it should only be activated when Clock is active (clock edges). Only when a process contains combinatorial logic, all read signals have to be in the sens. list.

BTW: Nice project and very good documentation in your blog 👍

[Domipheus]

Thanks for this - it's likely legacy leftovers from my code iterations. When I started this I was new to VHDL so there are likely many more bits like this! I'll try to go over the code and remove this kind of thing. Thanks for the comment on the project :)