diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml new file mode 100644 index 0000000..2b95718 --- /dev/null +++ b/.github/workflows/build.yml @@ -0,0 +1,129 @@ +name: Dasharo +on: + push: + branches: + - rel_* + +jobs: + build_pcengines: + runs-on: ubuntu-22.04 + container: + image: ghcr.io/dasharo/dasharo-sdk:v1.6.0-rc4 + options: --user 1001 + strategy: + matrix: + vendor: [ pcengines ] + model: [ apu2, apu3, apu4, apu6 ] + payload: [ seabios ] + steps: + - name: Checkout coreboot + run: | + echo "VERSION=$(echo ${GITHUB_REF#refs/heads/rel_} | tr '/' '_')" >> $GITHUB_ENV + VERSION=$(echo ${GITHUB_REF#refs/heads/rel_} | tr '/' '_') + CORELABEL=$(echo $VERSION | awk -F '.' '{if ($3 == "00") print $1"."$2; else print $1"."$2"."$3}') + echo "Extracted Coreboot version: $CORELABEL" + git clone https://review.coreboot.org/coreboot + cd coreboot + git checkout $CORELABEL -b patchqueue + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Fetch complete history + fetch-depth: 0 + path: coreboot/.git/patches + - name: Set Up Git + run: | + cd $GITHUB_WORKSPACE/coreboot + git config user.name "github-actions[bot]" + git config user.email "github-actions[bot]@users.noreply.github.com" + ln -s patches .git/patches/patchqueue + touch .git/patches/patchqueue/status + - name: Apply Patches Using Guilt + run: | + cd $GITHUB_WORKSPACE/coreboot + guilt push -a + - name: Checkout coreboot submodules and add annoted tag + run: | + cd $GITHUB_WORKSPACE/coreboot + git submodule update --init --recursive --checkout + # this is for verification of reproducibility in local builds + git tag -a github-actions-bot-tag -m "$GITHUB_REF_NAME" + - name: Build Dasharo + run: | + cd $GITHUB_WORKSPACE/coreboot + cp configs/config.${{ matrix.vendor }}_${{ matrix.payload }}_${{ matrix.model }} .config + make olddefconfig + make BUILD_TIMELESS=1 + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}-${{ matrix.payload }}" + path: | + coreboot/build/coreboot.rom + retention-days: 30 + build_q35: + runs-on: ubuntu-22.04 + container: + image: ghcr.io/dasharo/dasharo-sdk:v1.6.0-rc4 + options: --user 1001 + strategy: + matrix: + vendor: [ emulation_qemu ] + model: [ x86_q35 ] + payload: [ smm_tseg_seabios ] + steps: + - name: Checkout coreboot + run: | + echo "VERSION=$(echo ${GITHUB_REF#refs/heads/rel_} | tr '/' '_')" >> $GITHUB_ENV + VERSION=$(echo ${GITHUB_REF#refs/heads/rel_} | tr '/' '_') + CORELABEL=$(echo $VERSION | awk -F '.' '{if ($3 == "00") print $1"."$2; else print $1"."$2"."$3}') + echo "Extracted Coreboot version: $CORELABEL" + git clone https://review.coreboot.org/coreboot + cd coreboot + git checkout $CORELABEL -b patchqueue + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Fetch complete history + fetch-depth: 0 + path: coreboot/.git/patches + - name: Set Up Git + run: | + cd $GITHUB_WORKSPACE/coreboot + git config user.name "github-actions[bot]" + git config user.email "github-actions[bot]@users.noreply.github.com" + ln -s patches .git/patches/patchqueue + touch .git/patches/patchqueue/status + - name: Apply Patches Using Guilt + run: | + cd $GITHUB_WORKSPACE/coreboot + guilt push -a + - name: Checkout coreboot submodules and add annoted tag + run: | + cd $GITHUB_WORKSPACE/coreboot + git submodule update --init --recursive --checkout + # this is for verification of reproducibility in local builds + git tag -a github-actions-bot-tag -m "$GITHUB_REF_NAME" + - name: Build Dasharo + run: | + cd $GITHUB_WORKSPACE/coreboot + cp configs/config.${{ matrix.vendor }}_${{ matrix.model }}_${{ matrix.payload }} .config + make olddefconfig + make BUILD_TIMELESS=1 + mv build/coreboot.rom build/qemu_q35_${VERSION}.rom + sha256sum build/qemu_q35_${VERSION}.rom > build/qemu_q35_${VERSION}.rom.sha256 + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}-${{ matrix.payload }}_${{ env.VERSION }}" + path: | + coreboot/build/qemu_q35_${{ env.VERSION }}.rom + coreboot/build/qemu_q35_${{ env.VERSION }}.rom.sha256 + retention-days: 30 + diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..2a7c4a5 --- /dev/null +++ b/.gitignore @@ -0,0 +1,3 @@ +*.*~ +patches/status +patchqueue diff --git a/README.md b/README.md index a8478f5..d147c04 100644 --- a/README.md +++ b/README.md @@ -10,9 +10,9 @@ information on contributing to the Dasharo project. ## Usage -Following procedure was created while testing PC Engines v24.05.00.01. It -should be generalized after gaining better understanding of the Dasharo -Patchqueue Initiative. +Following procedure was created while testing PC Engines v24.05.00.01 and +retested while releasing v24.08.00.01. It should be generalized after gaining +better understanding of the Dasharo Patchqueue Initiative. ### Prepare code base @@ -29,7 +29,7 @@ cd coreboot Checkout branch on tag on which you would like to apply patchqueue: ```bash -git checkout 24.05 -b patchqueue +git checkout 24.08 -b patchqueue ``` Clone this repo: @@ -44,10 +44,11 @@ Go to `.git/patches` and checkout correct patchqueue version: cd .git/patches ``` -In this case we plan to build Dasahro (coreboot+SeaBIOS) v24.05.00.01 for PC Engines: +In this case re plan to build Dasharo (coreboot+SeaBIOS) v24.08.00.01 for PC +Engines: ```bash -git checkout v25.05.00.01 +git checkout 24.08.00.01 ``` Get back to coreboot main directory: @@ -114,24 +115,29 @@ Tag repository, otherwise hash of the build will not match since coreboot use tag during build process: ```sh -git tag -a v24.05.00.01 -m "Some annotation which conten really doesn't matter" +git tag -a v24.08.00.01 -m "Some annotation which conten really doesn't matter" ``` **NOTE:** It has to be annotated tag, coreboot does not pick others. -### Compile +## Release process notes -To compile created code base please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder). +After applying all patches binaries for all platforms can be build: + +```sh +export BUILD_TIMELESS=1 && ./build.sh seabios_apu2 && ./build.sh seabios_apu3\ +&& ./build.sh seabios_apu4 && ./build.sh seabios_apu6 +``` ## Development -### How to handle bug in patches ? +### How to handle bug in patches? -- pop patches using `guilt pop` until you will have broken one on top of stack, -- modify files, +- Pop patches using `guilt pop` until you will have broken one on top of stack, +- Modify files, - `guilt refresh` - this will store changes in required patch - `guilt push -a` - to make sure all patches on top apply without problems -- commit changes to this repository +- Commit changes to this repository Read `man guilt-pop` for efficient popping. @@ -159,16 +165,6 @@ application issues. After resolving issues for given patch use `git add` to stage required changes and `guilt refresh` to update patch, so it reflects cleanly applicable change. -At this point you may need to check if code still compiles at this point, that -why [pce-fw-builder update](#pce-fw-builder-update) may be useful. - -#### pce-fw-builder update - -To understood what changes may be needed to -[pce-fw-builder](https://github.com/pcengines/pce-fw-builder) when updating to -new coreboot version, please check [this -MR](https://github.com/pcengines/pce-fw-builder/pull/66). - ## Background The `dasharo-pq` repository was created as a proof of concept to address issues @@ -219,7 +215,7 @@ mentioned in [#310](https://github.com/Dasharo/dasharo-issues/issues/310). ### Why Track Patches in Git Instead of Just Using Branches? -> Follwing list of arguments was heavily influenced by discussion in +> Following list of arguments was heavily influenced by discussion in > [#5](https://github.com/Dasharo/dasharo-pq/pull/5). Kudos to: > [@krystian-hebel](https://github.com/krystian-hebel), > [@andyhhp](https://github.com/andyhhp), diff --git a/patches/0001-configs-move-apu-2-3-4-6-configs-to-seabios_apu-2-3-.patch b/patches/0001-configs-move-apu-2-3-4-6-configs-to-seabios_apu-2-3-.patch deleted file mode 100644 index 02e832d..0000000 --- a/patches/0001-configs-move-apu-2-3-4-6-configs-to-seabios_apu-2-3-.patch +++ /dev/null @@ -1,45 +0,0 @@ -From b982a2728498d22b098a2a55d4eab0eb5db8d8bf Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= -Date: Wed, 19 Jun 2024 00:14:25 +0200 -Subject: [PATCH] configs: move apu{2,3,4,6} configs to seabios_apu{2,3,4,6} -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Dasharo Release Toolkit has problems with bash patterns for subset of -configs to be build, that why given release has to have distinct name -pattern. Because Dasharo(coreboot+UEFI) for PC Engines use -pcengines_uefi_apuX, here we use pcengines_seabios_apuX, but only for -apu{2,3,4,6} which are supported in this builds. - -Signed-off-by: Piotr Król ---- - configs/{config.pcengines_apu2 => config.pcengines_seabios_apu2} | 0 - configs/{config.pcengines_apu3 => config.pcengines_seabios_apu3} | 0 - configs/{config.pcengines_apu4 => config.pcengines_seabios_apu4} | 0 - configs/{config.pcengines_apu6 => config.pcengines_seabios_apu6} | 0 - 4 files changed, 0 insertions(+), 0 deletions(-) - rename configs/{config.pcengines_apu2 => config.pcengines_seabios_apu2} (100%) - rename configs/{config.pcengines_apu3 => config.pcengines_seabios_apu3} (100%) - rename configs/{config.pcengines_apu4 => config.pcengines_seabios_apu4} (100%) - rename configs/{config.pcengines_apu6 => config.pcengines_seabios_apu6} (100%) - -diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_seabios_apu2 -similarity index 100% -rename from configs/config.pcengines_apu2 -rename to configs/config.pcengines_seabios_apu2 -diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_seabios_apu3 -similarity index 100% -rename from configs/config.pcengines_apu3 -rename to configs/config.pcengines_seabios_apu3 -diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_seabios_apu4 -similarity index 100% -rename from configs/config.pcengines_apu4 -rename to configs/config.pcengines_seabios_apu4 -diff --git a/configs/config.pcengines_apu6 b/configs/config.pcengines_seabios_apu6 -similarity index 100% -rename from configs/config.pcengines_apu6 -rename to configs/config.pcengines_seabios_apu6 --- -2.39.2 - diff --git a/patches/0001-configs-remove-apu1-and-add-apu2-4.patch b/patches/0001-configs-remove-apu1-and-add-apu2-4.patch deleted file mode 100644 index 6400018..0000000 --- a/patches/0001-configs-remove-apu1-and-add-apu2-4.patch +++ /dev/null @@ -1,107 +0,0 @@ -From 144c63dd376af81b065ce0e12439b2b59e8975f0 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=3D=3FUTF-8=3Fq=3FPiotr=3D20Kr=3DC3=3DB3l=3F=3D?= - -Date: Wed, 8 May 2024 13:32:17 +0200 -Subject: [PATCH] From 38278c77511b3312ead14b13fd11f5f588931673 Mon Sep 17 - 00:00:00 2001 [PATCH 01/80] configs: remove apu1 and add apu2/4 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Piotr Król -diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1 -deleted file mode 100644 -index a3e34b8df04d..000000000000 ---- a/configs/config.pcengines_apu1 -+++ /dev/null -@@ -1,10 +0,0 @@ --# CONFIG_COLLECT_TIMESTAMPS is not set --CONFIG_VENDOR_PCENGINES=y --CONFIG_BOARD_PCENGINES_APU1=y --CONFIG_NO_GFX_INIT=y --CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y --CONFIG_PXE=y --CONFIG_BUILD_IPXE=y --CONFIG_PXE_ROM_ID="10ec,8168" --# CONFIG_IPXE_SERIAL_CONSOLE is not set --CONFIG_MEMTEST_SECONDARY_PAYLOAD=y -diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2 -index fe0a9d7ba431..5157ec1194e5 100644 ---- a/configs/config.pcengines_apu2 -+++ b/configs/config.pcengines_apu2 -@@ -1,12 +1,24 @@ --# CONFIG_COLLECT_TIMESTAMPS is not set --CONFIG_VENDOR_PCENGINES=y --CONFIG_BOARD_PCENGINES_APU2=y --CONFIG_APU2_PINMUX_UART_C=y --CONFIG_APU2_PINMUX_UART_D=y -+# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set -+# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set -+# CONFIG_IPXE_SERIAL_CONSOLE is not set -+CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000 -+CONFIG_BOTTOMIO_POSITION=0xD0000000 -+CONFIG_BUILD_IPXE=y -+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y -+CONFIG_HUDSON_SATA_MODE=2 -+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -+CONFIG_IPXE_ADD_SCRIPT=y -+CONFIG_LOCALVERSION="v24.05.00.01" -+CONFIG_MEMTEST86PLUS_V5=y -+CONFIG_MEMTEST_SECONDARY_PAYLOAD=y - CONFIG_NO_GFX_INIT=y --CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y -+CONFIG_POST_IO_PORT=0x80 - CONFIG_PXE=y --CONFIG_BUILD_IPXE=y - CONFIG_PXE_ROM_ID="8086,157b" --# CONFIG_IPXE_SERIAL_CONSOLE is not set --CONFIG_MEMTEST_SECONDARY_PAYLOAD=y -+CONFIG_SEABIOS_DEBUG_LEVEL=0 -+CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 -+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 -+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 -+CONFIG_TPM2=y -+CONFIG_VENDOR_PCENGINES=y -diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4 -index 17db794bcf92..ae119658be3e 100644 ---- a/configs/config.pcengines_apu4 -+++ b/configs/config.pcengines_apu4 -@@ -1,12 +1,25 @@ --# CONFIG_COLLECT_TIMESTAMPS is not set --CONFIG_VENDOR_PCENGINES=y -+# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set -+# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set -+# CONFIG_IPXE_SERIAL_CONSOLE is not set -+CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000 - CONFIG_BOARD_PCENGINES_APU4=y --CONFIG_APU2_PINMUX_UART_C=y --CONFIG_APU2_PINMUX_UART_D=y -+CONFIG_BOTTOMIO_POSITION=0xD0000000 -+CONFIG_BUILD_IPXE=y -+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y -+CONFIG_HUDSON_SATA_MODE=2 -+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -+CONFIG_IPXE_ADD_SCRIPT=y -+CONFIG_LOCALVERSION="v24.05.00.01" -+CONFIG_MEMTEST86PLUS_V5=y -+CONFIG_MEMTEST_SECONDARY_PAYLOAD=y - CONFIG_NO_GFX_INIT=y --CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y -+CONFIG_POST_IO_PORT=0x80 - CONFIG_PXE=y --CONFIG_BUILD_IPXE=y - CONFIG_PXE_ROM_ID="8086,1539" --# CONFIG_IPXE_SERIAL_CONSOLE is not set --CONFIG_MEMTEST_SECONDARY_PAYLOAD=y -+CONFIG_SEABIOS_DEBUG_LEVEL=0 -+CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 -+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 -+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 -+CONFIG_TPM2=y -+CONFIG_VENDOR_PCENGINES=y diff --git a/patches/0001-configs-sort-apu3-and-apu5-configs.patch b/patches/0001-configs-sort-apu3-and-apu5-configs.patch deleted file mode 100644 index 21766df..0000000 --- a/patches/0001-configs-sort-apu3-and-apu5-configs.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 40b88570275e3323687b7381a3b8efabf1492b6e Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= -Date: Mon, 3 Jun 2024 16:01:18 +0200 -Subject: [PATCH] configs: sort apu3 and apu5 configs -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -To keep consistency across PC Engines configs all config options are -always sorted in alphabetical order. - -Signed-off-by: Piotr Król ---- - configs/config.pcengines_apu3 | 12 ++++++------ - configs/config.pcengines_apu5 | 12 ++++++------ - 2 files changed, 12 insertions(+), 12 deletions(-) - -diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3 -index bf377158dfea..e4bc9914a1c7 100644 ---- a/configs/config.pcengines_apu3 -+++ b/configs/config.pcengines_apu3 -@@ -1,12 +1,12 @@ - # CONFIG_COLLECT_TIMESTAMPS is not set --CONFIG_VENDOR_PCENGINES=y --CONFIG_BOARD_PCENGINES_APU3=y -+# CONFIG_IPXE_SERIAL_CONSOLE is not set - CONFIG_APU2_PINMUX_UART_C=y - CONFIG_APU2_PINMUX_UART_D=y -+CONFIG_BOARD_PCENGINES_APU3=y -+CONFIG_BUILD_IPXE=y -+CONFIG_MEMTEST_SECONDARY_PAYLOAD=y - CONFIG_NO_GFX_INIT=y --CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y - CONFIG_PXE=y --CONFIG_BUILD_IPXE=y - CONFIG_PXE_ROM_ID="8086,1539" --# CONFIG_IPXE_SERIAL_CONSOLE is not set --CONFIG_MEMTEST_SECONDARY_PAYLOAD=y -+CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y -+CONFIG_VENDOR_PCENGINES=y -diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5 -index b004e89c9103..7f405bc6900b 100644 ---- a/configs/config.pcengines_apu5 -+++ b/configs/config.pcengines_apu5 -@@ -1,12 +1,12 @@ - # CONFIG_COLLECT_TIMESTAMPS is not set --CONFIG_VENDOR_PCENGINES=y --CONFIG_BOARD_PCENGINES_APU5=y -+# CONFIG_IPXE_SERIAL_CONSOLE is not set - CONFIG_APU2_PINMUX_UART_C=y - CONFIG_APU2_PINMUX_UART_D=y -+CONFIG_BOARD_PCENGINES_APU5=y -+CONFIG_BUILD_IPXE=y -+CONFIG_MEMTEST_SECONDARY_PAYLOAD=y - CONFIG_NO_GFX_INIT=y --CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y - CONFIG_PXE=y --CONFIG_BUILD_IPXE=y - CONFIG_PXE_ROM_ID="8086,1539" --# CONFIG_IPXE_SERIAL_CONSOLE is not set --CONFIG_MEMTEST_SECONDARY_PAYLOAD=y -+CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y -+CONFIG_VENDOR_PCENGINES=y --- -2.39.2 - diff --git a/patches/0001-payloads-ipxe-fix-compilation-issues-with-corebood-s.patch b/patches/0001-payloads-ipxe-bump-iPXE-to-2024.08.patch similarity index 63% rename from patches/0001-payloads-ipxe-fix-compilation-issues-with-corebood-s.patch rename to patches/0001-payloads-ipxe-bump-iPXE-to-2024.08.patch index 60314fb..fc744f0 100644 --- a/patches/0001-payloads-ipxe-fix-compilation-issues-with-corebood-s.patch +++ b/patches/0001-payloads-ipxe-bump-iPXE-to-2024.08.patch @@ -1,17 +1,15 @@ -From 7084a1a8bf5d914f953da6b1ffafd96b6572061f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= +From 2b02c269362b0d0be2c533665b529fb9cacd9849 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=3D=3FUTF-8=3Fq=3FPiotr=3D20Kr=3DC3=3DB3l=3F=3D?= + Date: Mon, 3 Jun 2024 14:51:03 +0200 -Subject: [PATCH] payloads/ipxe: fix compilation issues with corebood-sdk - 2024-03-30_cccada28f7 +Subject: [PATCH 01/88] payloads/ipxe: bump iPXE to 2024.08 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit -This patch updates iPXE to last commit from May 2024 (2024.05). It -should be updated to support coreboot-sdk 2024-05-20_b4949d3de5, which -is most recent at this point, but iPXE fails with that SDK and that's -why previous SDK was used for building. +This patch updates iPXE to last commit from August 2024 (2024.08). +Upstream-Status: Pending Signed-off-by: Piotr Król --- payloads/external/iPXE/Kconfig | 2 +- @@ -19,7 +17,7 @@ Signed-off-by: Piotr Król 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig -index 2ad39a1a6b30..8cf19c3e47c4 100644 +index ff25d81957..19c7abdda9 100644 --- a/payloads/external/iPXE/Kconfig +++ b/payloads/external/iPXE/Kconfig @@ -54,7 +54,7 @@ choice @@ -27,25 +25,25 @@ index 2ad39a1a6b30..8cf19c3e47c4 100644 config IPXE_STABLE - bool "2022.1" -+ bool "2024.5" ++ bool "2024.8" help iPXE uses a rolling release with no stable version, for reproducibility, use the last commit of a given month as the diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile -index 6f5525bcd6d6..c1bd3e4474dc 100644 +index 7ec8126c97..684f7b241c 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -1,8 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only -# 2022.1 - Last commit of January 2022 -+# 2024.5 - Last commit of May 2024 ++# 2024.8 - Last commit of August 2024 # When updating, change the name both here and in payloads/external/iPXE/Kconfig -STABLE_COMMIT_ID=6ba671acd922ee046b257c5119b8a0f64d275473 -+STABLE_COMMIT_ID=e965f179e1654103eca33feed7a9cc4c51d91be6 ++STABLE_COMMIT_ID=301644ab480ab9787c617e1a94e19ca5c2774072 TAG-$(CONFIG_IPXE_MASTER)=origin/master TAG-$(CONFIG_IPXE_STABLE)=$(STABLE_COMMIT_ID) -- -2.39.2 +2.49.0 diff --git a/patches/0002-configs-add-pcengines_seabios_apu-2-4.patch b/patches/0002-configs-add-pcengines_seabios_apu-2-4.patch new file mode 100644 index 0000000..104d039 --- /dev/null +++ b/patches/0002-configs-add-pcengines_seabios_apu-2-4.patch @@ -0,0 +1,82 @@ +From 217888f5f22c4484638ed7cd48ba0cdbbd2238b3 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=3D=3FUTF-8=3Fq=3F=3D3D=3D3FUTF-8=3D3Fq=3D3FPiotr=3D3D20Kr?= + =?UTF-8?q?=3D3DC3=3D3DB3l=3D3F=3D3D=3F=3D?= <> +Date: Wed, 8 May 2024 13:32:17 +0200 +Subject: [PATCH 02/88] configs: add pcengines_seabios_apu{2,4} +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Upstream-Status: Pending +Signed-off-by: Piotr Król +--- + configs/config.pcengines_seabios_apu2 | 24 ++++++++++++++++++++++++ + configs/config.pcengines_seabios_apu4 | 25 +++++++++++++++++++++++++ + 2 files changed, 49 insertions(+) + create mode 100644 configs/config.pcengines_seabios_apu2 + create mode 100644 configs/config.pcengines_seabios_apu4 + +diff --git a/configs/config.pcengines_seabios_apu2 b/configs/config.pcengines_seabios_apu2 +new file mode 100644 +index 0000000000..7058b2c7cc +--- /dev/null ++++ b/configs/config.pcengines_seabios_apu2 +@@ -0,0 +1,24 @@ ++# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set ++# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set ++# CONFIG_IPXE_SERIAL_CONSOLE is not set ++CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000 ++CONFIG_BOTTOMIO_POSITION=0xD0000000 ++CONFIG_BUILD_IPXE=y ++CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 ++CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y ++CONFIG_HUDSON_SATA_MODE=2 ++CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 ++CONFIG_IPXE_ADD_SCRIPT=y ++CONFIG_LOCALVERSION="v24.08.00.01" ++CONFIG_MEMTEST86PLUS_V5=y ++CONFIG_MEMTEST_SECONDARY_PAYLOAD=y ++CONFIG_NO_GFX_INIT=y ++CONFIG_POST_IO_PORT=0x80 ++CONFIG_PXE=y ++CONFIG_PXE_ROM_ID="8086,157b" ++CONFIG_SEABIOS_DEBUG_LEVEL=0 ++CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 ++CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 ++CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 ++CONFIG_TPM2=y ++CONFIG_VENDOR_PCENGINES=y +diff --git a/configs/config.pcengines_seabios_apu4 b/configs/config.pcengines_seabios_apu4 +new file mode 100644 +index 0000000000..c1ad2636f1 +--- /dev/null ++++ b/configs/config.pcengines_seabios_apu4 +@@ -0,0 +1,25 @@ ++# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set ++# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set ++# CONFIG_IPXE_SERIAL_CONSOLE is not set ++CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000 ++CONFIG_BOARD_PCENGINES_APU4=y ++CONFIG_BOTTOMIO_POSITION=0xD0000000 ++CONFIG_BUILD_IPXE=y ++CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 ++CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y ++CONFIG_HUDSON_SATA_MODE=2 ++CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 ++CONFIG_IPXE_ADD_SCRIPT=y ++CONFIG_LOCALVERSION="v24.08.00.01" ++CONFIG_MEMTEST86PLUS_V5=y ++CONFIG_MEMTEST_SECONDARY_PAYLOAD=y ++CONFIG_NO_GFX_INIT=y ++CONFIG_POST_IO_PORT=0x80 ++CONFIG_PXE=y ++CONFIG_PXE_ROM_ID="8086,1539" ++CONFIG_SEABIOS_DEBUG_LEVEL=0 ++CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 ++CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 ++CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 ++CONFIG_TPM2=y ++CONFIG_VENDOR_PCENGINES=y +-- +2.49.0 + diff --git a/patches/0002-payloads-seabios-use-PC-Engines-repository.patch b/patches/0002-payloads-seabios-use-PC-Engines-repository.patch deleted file mode 100644 index 8ea42bc..0000000 --- a/patches/0002-payloads-seabios-use-PC-Engines-repository.patch +++ /dev/null @@ -1,70 +0,0 @@ -From b46b7135e525bdf2f0e7cb641bc75c2a931cb11d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= -Date: Wed, 8 May 2024 13:40:23 +0200 -Subject: [PATCH 02/80] payloads/seabios: use PC Engines repository -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Piotr Król -diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2 -index 5157ec1194e5..f8e362fa5e34 100644 ---- a/configs/config.pcengines_apu2 -+++ b/configs/config.pcengines_apu2 -@@ -17,6 +17,8 @@ CONFIG_POST_IO_PORT=0x80 - CONFIG_PXE=y - CONFIG_PXE_ROM_ID="8086,157b" - CONFIG_SEABIOS_DEBUG_LEVEL=0 -+CONFIG_SEABIOS_REVISION=y -+CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" - CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 - CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 - CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 -diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3 -index 89e4d995bd71..0604bb39f83a 100644 ---- a/configs/config.pcengines_apu3 -+++ b/configs/config.pcengines_apu3 -@@ -10,4 +10,6 @@ CONFIG_NO_GFX_INIT=y - CONFIG_PXE=y - CONFIG_PXE_ROM_ID="8086,1539" - CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y -+CONFIG_SEABIOS_REVISION=y -+CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" - CONFIG_VENDOR_PCENGINES=y -diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4 -index ae119658be3e..7548f07e5573 100644 ---- a/configs/config.pcengines_apu4 -+++ b/configs/config.pcengines_apu4 -@@ -18,6 +18,8 @@ CONFIG_POST_IO_PORT=0x80 - CONFIG_PXE=y - CONFIG_PXE_ROM_ID="8086,1539" - CONFIG_SEABIOS_DEBUG_LEVEL=0 -+CONFIG_SEABIOS_REVISION=y -+CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" - CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 - CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 - CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 -diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5 -index 7e7f6558f643..3ad06d2cfbd5 100644 ---- a/configs/config.pcengines_apu5 -+++ b/configs/config.pcengines_apu5 -@@ -10,4 +10,6 @@ CONFIG_NO_GFX_INIT=y - CONFIG_PXE=y - CONFIG_PXE_ROM_ID="8086,1539" - CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y -+CONFIG_SEABIOS_REVISION=y -+CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" - CONFIG_VENDOR_PCENGINES=y -diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile -index 7926f3fb90ad..5bdd526296ae 100644 ---- a/payloads/external/SeaBIOS/Makefile -+++ b/payloads/external/SeaBIOS/Makefile -@@ -2,7 +2,7 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master - TAG-$(CONFIG_SEABIOS_STABLE)=a6ed6b701f0a57db0569ab98b0661c12a6ec3ff8 - TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID) - --project_git_repo=https://review.coreboot.org/seabios.git -+project_git_repo=https://github.com/pcengines/seabios.git - project_dir=seabios - - unexport KCONFIG_AUTOHEADER diff --git a/patches/0003-configs-add-pcengines_seabios_apu3.patch b/patches/0003-configs-add-pcengines_seabios_apu3.patch new file mode 100644 index 0000000..5540bad --- /dev/null +++ b/patches/0003-configs-add-pcengines_seabios_apu3.patch @@ -0,0 +1,50 @@ +From e8232cd5161eae53b50eb3d60a4055658c9f58b4 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=3D=3FUTF-8=3Fq=3F=3D3D=3D3FUTF-8=3D3Fq=3D3FPiotr=3D3D20Kr?= + =?UTF-8?q?=3D3DC3=3D3DB3l=3D3F=3D3D=3F=3D?= <> +Date: Mon, 3 Jun 2024 16:01:18 +0200 +Subject: [PATCH 03/88] configs: add pcengines_seabios_apu3 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Upstream-Status: Pending +Signed-off-by: Piotr Król +--- + configs/config.pcengines_seabios_apu3 | 25 +++++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + create mode 100644 configs/config.pcengines_seabios_apu3 + +diff --git a/configs/config.pcengines_seabios_apu3 b/configs/config.pcengines_seabios_apu3 +new file mode 100644 +index 0000000000..91758066ac +--- /dev/null ++++ b/configs/config.pcengines_seabios_apu3 +@@ -0,0 +1,25 @@ ++# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set ++# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set ++# CONFIG_IPXE_SERIAL_CONSOLE is not set ++CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000 ++CONFIG_BOARD_PCENGINES_APU3=y ++CONFIG_BOTTOMIO_POSITION=0xD0000000 ++CONFIG_BUILD_IPXE=y ++CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 ++CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y ++CONFIG_HUDSON_SATA_MODE=2 ++CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 ++CONFIG_IPXE_ADD_SCRIPT=y ++CONFIG_LOCALVERSION="v24.08.00.01" ++CONFIG_MEMTEST86PLUS_V5=y ++CONFIG_MEMTEST_SECONDARY_PAYLOAD=y ++CONFIG_NO_GFX_INIT=y ++CONFIG_POST_IO_PORT=0x80 ++CONFIG_PXE=y ++CONFIG_PXE_ROM_ID="8086,1539" ++CONFIG_SEABIOS_DEBUG_LEVEL=0 ++CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 ++CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 ++CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 ++CONFIG_TPM2=y ++CONFIG_VENDOR_PCENGINES=y +-- +2.49.0 + diff --git a/patches/0004-build.sh-dummy-patch-from-26ab7d99e984e662f6ed8ba2c0.patch b/patches/0004-build.sh-dummy-patch-from-26ab7d99e984e662f6ed8ba2c0.patch new file mode 100644 index 0000000..93952f5 --- /dev/null +++ b/patches/0004-build.sh-dummy-patch-from-26ab7d99e984e662f6ed8ba2c0.patch @@ -0,0 +1,415 @@ +From 2f2369310edd4119000c1a76f4aaa6c7e8355011 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= +Date: Mon, 4 Nov 2024 23:17:41 +0100 +Subject: [PATCH 04/88] build.sh: dummy patch from + 26ab7d99e984e662f6ed8ba2c0e2725c43639a45 dasharo/coreboot +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Upstream-Status: Inappropriate [The script should be placed elsewhere] +Signed-off-by: Piotr Król +diff --git a/build.sh b/build.sh +new file mode 100644 +index 0000000000..2027f6aaf3 +--- /dev/null ++++ b/build.sh +@@ -0,0 +1,398 @@ ++#!/bin/bash ++ ++set -euo pipefail ++ ++usage() { ++ echo "${0} CMD" ++ echo "Available CMDs:" ++ echo -e "\tz690a_ddr4 - build Dasharo image compatible with MSI PRO Z690-A (WIFI) DDR4" ++ echo -e "\tz690a_ddr5 - build Dasharo image compatible with MSI PRO Z690-A (WIFI)" ++ echo -e "\tz790p_ddr4 - build Dasharo image compatible with MSI PRO Z790-P (WIFI) DDR4" ++ echo -e "\tz790p_ddr5 - build Dasharo image compatible with MSI PRO Z790-P (WIFI)" ++ echo -e "\tvp66xx - build Dasharo for Protectli VP66xx" ++ echo -e "\tvp46xx - build Dasharo for Protectli VP46xx" ++ echo -e "\tvp32xx - build Dasharo for Protectli VP32xx" ++ echo -e "\tvp2430 - build Dasharo for Protectli VP2430" ++ echo -e "\tvp2420 - build Dasharo for Protectli VP2420" ++ echo -e "\tvp2410 - build Dasharo for Protectli VP2410" ++ echo -e "\tV1210 - build Dasharo for Protectli V1210" ++ echo -e "\tV1410 - build Dasharo for Protectli V1410" ++ echo -e "\tV1610 - build Dasharo for Protectli V1610" ++ echo -e "\tapu2 - build Dasharo for PC Engines APU2" ++ echo -e "\tapu3 - build Dasharo for PC Engines APU3" ++ echo -e "\tapu4 - build Dasharo for PC Engines APU4" ++ echo -e "\tapu6 - build Dasharo for PC Engines APU6" ++ echo -e "\toptiplex_9010_uefi - build Dasharo compatible with Dell OptiPlex 7010/9010 (UEFI)" ++ echo -e "\toptiplex_9010_seabios - build Dasharo compatible with Dell OptiPlex 7010/9010 (SeaBIOS)" ++ echo -e "\tqemu - build Dasharo for QEMU Q35" ++ echo -e "\tqemu_full - build Dasharo for QEMU Q35 with all menus available" ++ echo -e "\todroid_h4 - build Dasharo compatible with Hardkernel ODROID H4" ++} ++ ++SDKVER="2024-02-18_732134932b" ++DASHARO_SDK=${DASHARO_SDK:-"ghcr.io/dasharo/dasharo-sdk:v1.6.0"} ++ ++function build_optiplex_9010 { ++ DEFCONFIG=$1 ++ # Determine FW flavor first (uefi or seabios) ++ if [[ ${DEFCONFIG} == *"uefi"* ]]; then ++ FW_FLAVOR="uefi" ++ else ++ FW_FLAVOR="seabios" ++ fi ++ ++ # Get FW version ++ FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') ++ ++ # Combine FW flavor with version ++ FW_VERSION="${FW_FLAVOR}_${FW_VERSION}" ++ ++ docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ ++ -v $HOME/.ssh:/home/coreboot/.ssh \ ++ -w /home/coreboot/coreboot ${DASHARO_SDK} \ ++ /bin/bash -c "make distclean" ++ ++ cp "${DEFCONFIG}" .config ++ ++ git submodule update --init --checkout ++ ++ echo "Building Dasharo compatible with Dell OptiPlex 7010/9010 (version $FW_VERSION)" ++ ++ docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ ++ -v $HOME/.ssh:/home/coreboot/.ssh \ ++ -w /home/coreboot/coreboot ${DASHARO_SDK} \ ++ /bin/bash -c "make olddefconfig && make -j$(nproc)" ++ ++ cp build/coreboot.rom ${BOARD}_${FW_VERSION}.rom ++ if [ $? -eq 0 ]; then ++ echo "Result binary placed in $PWD/${BOARD}_${FW_VERSION}.rom" ++ sha256sum ${BOARD}_${FW_VERSION}.rom > ${BOARD}_${FW_VERSION}.rom.sha256 ++ else ++ echo "Build failed!" ++ exit 1 ++ fi ++} ++ ++function build_msi { ++ DEFCONFIG="configs/config.${BOARD}_$1" ++ FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') ++ ++ docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ ++ -v $HOME/.ssh:/home/coreboot/.ssh \ ++ -w /home/coreboot/coreboot ${DASHARO_SDK} \ ++ /bin/bash -c "make distclean" ++ ++ cp "${DEFCONFIG}" .config ++ ++ git submodule update --init --checkout ++ ++ echo "Building Dasharo compatible with MSI PRO $2(WIFI) (version $FW_VERSION)" ++ ++ docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ ++ -v $HOME/.ssh:/home/coreboot/.ssh \ ++ -w /home/coreboot/coreboot ${DASHARO_SDK} \ ++ /bin/bash -c "make olddefconfig && make -j$(nproc)" ++ ++ cp build/coreboot.rom ${BOARD}_${FW_VERSION}_$1.rom ++ if [ $? -eq 0 ]; then ++ echo "Result binary placed in $PWD/${BOARD}_${FW_VERSION}_$1.rom" ++ sha256sum ${BOARD}_${FW_VERSION}_$1.rom > ${BOARD}_${FW_VERSION}_$1.rom.sha256 ++ else ++ echo "Build failed!" ++ exit 1 ++ fi ++} ++ ++function build_protectli_vault { ++ DEFCONFIG="configs/config.protectli_${BOARD}" ++ FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') ++ ++ if [ ! -d 3rdparty/dasharo-blobs/protectli ]; then ++ git submodule update --init --checkout ++ fi ++ ++ docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ ++ -v $HOME/.ssh:/home/coreboot/.ssh \ ++ -w /home/coreboot/coreboot coreboot/coreboot-sdk:2021-09-23_b0d87f753c \ ++ /bin/bash -c "make distclean" ++ ++ cp $DEFCONFIG .config ++ ++ echo "Building Dasharo for Protectli $BOARD (version $FW_VERSION)" ++ ++ docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ ++ -v $HOME/.ssh:/home/coreboot/.ssh \ ++ -w /home/coreboot/coreboot ${DASHARO_SDK} \ ++ /bin/bash -c "make olddefconfig && make -j$(nproc)" ++ ++ cp build/coreboot.rom protectli_${BOARD}_${FW_VERSION}.rom ++ if [ $? -eq 0 ]; then ++ echo "Result binary placed in $PWD/protectli_${BOARD}_${FW_VERSION}.rom" ++ sha256sum protectli_${BOARD}_${FW_VERSION}.rom > protectli_${BOARD}_${FW_VERSION}.rom.sha256 ++ else ++ echo "Build failed!" ++ exit 1 ++ fi ++} ++ ++function build_v1x10 { ++ DEFCONFIG="configs/config.protectli_vault_jsl_$1" ++ FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') ++ ++ if [ ! -d 3rdparty/dasharo-blobs/protectli ]; then ++ git submodule update --init --checkout ++ fi ++ ++ docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ ++ -v $HOME/.ssh:/home/coreboot/.ssh \ ++ -w /home/coreboot/coreboot ${DASHARO_SDK} \ ++ /bin/bash -c "make distclean" ++ ++ cp $DEFCONFIG .config ++ ++ echo "Building Dasharo for Protectli $1 (version $FW_VERSION)" ++ ++ docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ ++ -v $HOME/.ssh:/home/coreboot/.ssh \ ++ -w /home/coreboot/coreboot ${DASHARO_SDK} \ ++ /bin/bash -c "make olddefconfig && make -j$(nproc)" ++ ++ cp build/coreboot.rom protectli_$1_${FW_VERSION}.rom ++ if [ $? -eq 0 ]; then ++ echo "Result binary placed in $PWD/protectli_$1_${FW_VERSION}.rom" ++ sha256sum protectli_$1_${FW_VERSION}.rom > protectli_$1_${FW_VERSION}.rom.sha256 ++ else ++ echo "Build failed!" ++ exit 1 ++ fi ++} ++ ++function build_pcengines { ++ VARIANT=$1 ++ DEFCONFIG="configs/config.pcengines_${VARIANT}" ++ FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') ++ ++ # checkout several submodules needed by these boards (some others are checked ++ # out by coreboot's Makefile) ++ git submodule update --init --force --checkout \ ++ 3rdparty/dasharo-blobs \ ++ 3rdparty/vboot ++ ++ docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ ++ -v $HOME/.ssh:/home/coreboot/.ssh \ ++ -w /home/coreboot/coreboot ${DASHARO_SDK} \ ++ /bin/bash -c "make distclean" ++ ++ cp $DEFCONFIG .config ++ ++ echo "Building Dasharo for PC Engines ${VARIANT^^*} (version $FW_VERSION)" ++ ++ docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ ++ -v $HOME/.ssh:/home/coreboot/.ssh \ ++ -w /home/coreboot/coreboot ${DASHARO_SDK} \ ++ /bin/bash -c "make olddefconfig && make -j$(nproc)" ++ ++ cp build/coreboot.rom pcengines_${VARIANT}_${FW_VERSION}.rom ++ if [ $? -eq 0 ]; then ++ echo "Result binary placed in $PWD/pcengines_${VARIANT}_${FW_VERSION}.rom" ++ sha256sum pcengines_${VARIANT}_${FW_VERSION}.rom > pcengines_${VARIANT}_${FW_VERSION}.rom.sha256 ++ else ++ echo "Build failed!" ++ exit 1 ++ fi ++} ++ ++function build_qemu { ++ DEFCONFIG="configs/config.emulation_qemu_x86_q35_uefi${1:-}" ++ FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') ++ ++ # checkout several submodules needed by these boards (some others are checked ++ # out by coreboot's Makefile) ++ git submodule update --init --force --checkout \ ++ 3rdparty/dasharo-blobs ++ ++ docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ ++ -v $HOME/.ssh:/home/coreboot/.ssh \ ++ -w /home/coreboot/coreboot ${DASHARO_SDK} \ ++ /bin/bash -c "make distclean" ++ ++ cp $DEFCONFIG .config ++ ++ echo "Building Dasharo for QEMU Q35 (version $FW_VERSION)" ++ ++ docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ ++ -v $HOME/.ssh:/home/coreboot/.ssh \ ++ -e BUILD_TIMELESS=${BUILD_TIMELESS} \ ++ -w /home/coreboot/coreboot ${DASHARO_SDK} \ ++ /bin/bash -c "make olddefconfig && make -j$(nproc)" ++ ++ cp build/coreboot.rom qemu_q35_${FW_VERSION}.rom ++ if [ $? -eq 0 ]; then ++ echo "Result binary placed in $PWD/qemu_q35_${FW_VERSION}.rom" ++ sha256sum qemu_q35_${FW_VERSION}.rom > qemu_q35_${FW_VERSION}.rom.sha256 ++ else ++ echo "Build failed!" ++ exit 1 ++ fi ++} ++ ++function build_odroid_h4 { ++ DEFCONFIG=$1 ++ FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') ++ ++ # checkout several submodules needed by these boards (some others are checked ++ # out by coreboot's Makefile) ++ git submodule update --init --force --checkout \ ++ 3rdparty/dasharo-blobs ++ ++ if [ "${AIRGAP}" -eq 1 ]; then ++ docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ ++ -v $HOME/.ssh:/home/coreboot/.ssh \ ++ -w /home/coreboot/coreboot ${DASHARO_SDK} \ ++ /bin/bash -c "make clean" ++ else ++ docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ ++ -v $HOME/.ssh:/home/coreboot/.ssh \ ++ -w /home/coreboot/coreboot ${DASHARO_SDK} \ ++ /bin/bash -c "make distclean" ++ fi ++ ++ cp $DEFCONFIG .config ++ ++ echo "Building Dasharo compatbile with Hardkernel ODROID H4 (version $FW_VERSION)" ++ ++ if [ "${AIRGAP}" -eq 1 ]; then ++ ++ # In this situation we assume that provided repository is ready to be used ++ # and nothing should be downloaded during build process. ++ ++ if [ -d "${EDK2_REPO_PATH}" ]; then ++ # Without following sequence workspce would be created by docker with root ++ # privilidges and build will fail. ++ # Target directory ++ TARGET_DIR="payloads/external/edk2/workspace/Dasharo" ++ mkdir -p "$TARGET_DIR" ++ chown -R $(id -u):$(id -g) "$TARGET_DIR" ++ chmod -R 755 "$TARGET_DIR" ++ docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ ++ -v $HOME/.ssh:/home/coreboot/.ssh \ ++ --network none \ ++ ${EDK2_REPO_PATH:+-v $EDK2_REPO_PATH:/home/coreboot/coreboot/payloads/external/edk2/workspace/Dasharo} \ ++ -e BUILD_TIMELESS=${BUILD_TIMELESS} \ ++ -w /home/coreboot/coreboot ${DASHARO_SDK} \ ++ /bin/bash -c "make olddefconfig && make -j$(nproc)" ++ else ++ echo "EDK2_REPO_PATH is not defined in AIRGAP!" ++ exit 1 ++ fi ++ else ++ docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ ++ -v $HOME/.ssh:/home/coreboot/.ssh \ ++ -w /home/coreboot/coreboot ${DASHARO_SDK} \ ++ /bin/bash -c "make olddefconfig && make -j$(nproc)" ++ fi ++ ++ cp build/coreboot.rom hardkernel_odroid_h4_${FW_VERSION}.rom ++ if [ $? -eq 0 ]; then ++ echo "Result binary placed in $PWD/hardkernel_odroid_h4_${FW_VERSION}.rom" ++ sha256sum hardkernel_odroid_h4_${FW_VERSION}.rom > hardkernel_odroid_h4_${FW_VERSION}.rom.sha256 ++ else ++ echo "Build failed!" ++ exit 1 ++ fi ++} ++ ++CMD="$1" ++ ++case "$CMD" in ++ "ddr4" | "z690a_ddr4") ++ BOARD="msi_ms7d25" ++ build_msi ddr4 "Z690-A DDR4 " ++ ;; ++ "ddr5" | "z690a_ddr5") ++ BOARD="msi_ms7d25" ++ build_msi ddr5 "Z690-A DDR5 " ++ ;; ++ "z790p_ddr4") ++ BOARD="msi_ms7e06" ++ build_msi ddr4 "Z790-P DDR4 " ++ ;; ++ "z790p_ddr5") ++ BOARD="msi_ms7e06" ++ build_msi ddr5 "Z790-P DDR5 " ++ ;; ++ "vp66xx" | "VP66XX") ++ BOARD="vp66xx" ++ build_protectli_vault ++ ;; ++ "vp46xx" | "VP46XX") ++ BOARD="vp46xx" ++ build_protectli_vault ++ ;; ++ "vp32xx" | "VP32XX") ++ BOARD="vp32xx" ++ build_protectli_vault ++ ;; ++ "vp2410" | "VP2410") ++ BOARD="vp2410" ++ build_protectli_vault ++ ;; ++ "vp2420" | "VP2420") ++ BOARD="vp2420" ++ build_protectli_vault ++ ;; ++ "vp2430" | "VP2430") ++ BOARD="vp2430" ++ build_protectli_vault ++ ;; ++ "v1210" | "V1210" ) ++ build_v1x10 "v1210" ++ ;; ++ "v1211" | "V1211" ) ++ build_v1x10 "v1211" ++ ;; ++ "v1410" | "V1410" ) ++ build_v1x10 "v1410" ++ ;; ++ "v1610" | "V1610" ) ++ build_v1x10 "v1610" ++ ;; ++ "apu2" | "APU2" ) ++ build_pcengines "apu2" ++ ;; ++ "apu3" | "APU3" ) ++ build_pcengines "apu3" ++ ;; ++ "apu4" | "APU4" ) ++ build_pcengines "apu4" ++ ;; ++ "apu6" | "APU6" ) ++ build_pcengines "apu6" ++ ;; ++ "optiplex_9010_uefi") ++ BOARD="optiplex_9010" ++ build_optiplex_9010 "configs/config.dell_optiplex_9010_sff_uefi_txt" ++ ;; ++ "optiplex_9010_seabios") ++ BOARD="optiplex_9010" ++ build_optiplex_9010 "configs/config.dell_optiplex_9010_sff_txt" ++ ;; ++ "qemu" | "QEMU" | "q35" | "Q35" ) ++ build_qemu ++ ;; ++ "qemu_full" | "QEMU_full" | "q35_full" | "Q35_full" ) ++ build_qemu "_all_menus" ++ ;; ++ "odroid_h4" | "odroid_H4" | "ODROID_H4" ) ++ BOARD="odroid_h4" ++ build_odroid_h4 "configs/config.hardkernel_odroid_h4" ++ ;; ++ "odroid_h4_btg" ) ++ BOARD="odroid_h4" ++ build_odroid_h4 "configs/config.hardkernel_odroid_h4_btg" ++ ;; ++ *) ++ echo "Invalid command: \"$CMD\"" ++ usage ++ ;; ++esac diff --git a/patches/0005-build.sh-add-support-for-uefi-seabios-_apuX-builds.patch b/patches/0005-build.sh-add-support-for-uefi-seabios-_apuX-builds.patch new file mode 100644 index 0000000..1c7c57e --- /dev/null +++ b/patches/0005-build.sh-add-support-for-uefi-seabios-_apuX-builds.patch @@ -0,0 +1,57 @@ +From 26151d5a2a5c58164ca3cdb7d6a3495106becb2e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= +Date: Mon, 4 Nov 2024 23:38:57 +0100 +Subject: [PATCH 05/88] build.sh: add support for {uefi,seabios}_apuX builds +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Upstream-Status: Inappropriate [The script should be placed elsewhere] +Signed-off-by: Piotr Król +--- + build.sh | 20 ++++++++++++++++---- + 1 file changed, 16 insertions(+), 4 deletions(-) + mode change 100644 => 100755 build.sh + +diff --git a/build.sh b/build.sh +old mode 100644 +new mode 100755 +index 1115d4751b..bb9f7acfc6 +--- a/build.sh ++++ b/build.sh +@@ -357,16 +357,28 @@ case "$CMD" in + build_v1x10 "v1610" + ;; + "apu2" | "APU2" ) +- build_pcengines "apu2" ++ build_pcengines "uefi_apu2" + ;; + "apu3" | "APU3" ) +- build_pcengines "apu3" ++ build_pcengines "uefi_apu3" + ;; + "apu4" | "APU4" ) +- build_pcengines "apu4" ++ build_pcengines "uefi_apu4" + ;; + "apu6" | "APU6" ) +- build_pcengines "apu6" ++ build_pcengines "uefi_apu6" ++ ;; ++ "seabios_apu2" ) ++ build_pcengines "seabios_apu2" ++ ;; ++ "seabios_apu3" ) ++ build_pcengines "seabios_apu3" ++ ;; ++ "seabios_apu4" ) ++ build_pcengines "seabios_apu4" ++ ;; ++ "seabios_apu6" | "APU6" ) ++ build_pcengines "seabios_apu6" + ;; + "optiplex_9010_uefi") + BOARD="optiplex_9010" +-- +2.49.0 + diff --git a/patches/0005-configs-add-support-for-bootorder-files-for-PC-Engin.patch b/patches/0005-configs-add-support-for-bootorder-files-for-PC-Engin.patch deleted file mode 100644 index bae51c8..0000000 --- a/patches/0005-configs-add-support-for-bootorder-files-for-PC-Engin.patch +++ /dev/null @@ -1,41 +0,0 @@ -From f9e09922ac5cd58758e84683161c1cda0bbcb704 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= -Date: Mon, 6 May 2024 01:36:08 +0200 -Subject: [PATCH 05/80] configs: add support for bootorder files for PC Engines -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Piotr Król ---- - configs/config.pcengines_apu2 | 1 + - configs/config.pcengines_apu4 | 1 + - 2 files changed, 2 insertions(+) - -diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2 -index 9ab14bfb7b60..9befb0718c62 100644 ---- a/configs/config.pcengines_apu2 -+++ b/configs/config.pcengines_apu2 -@@ -14,6 +14,7 @@ CONFIG_POST_IO_PORT=0x80 - CONFIG_PXE=y - CONFIG_PXE_CUSTOM_BUILD_ID="12345678" - CONFIG_PXE_ROM_ID="8086,157b" -+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" - CONFIG_SEABIOS_DEBUG_LEVEL=0 - CONFIG_SEABIOS_REVISION=y - CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" -diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4 -index 4711a7e0bd32..d32ecaaf1314 100644 ---- a/configs/config.pcengines_apu4 -+++ b/configs/config.pcengines_apu4 -@@ -15,6 +15,7 @@ CONFIG_POST_IO_PORT=0x80 - CONFIG_PXE=y - CONFIG_PXE_CUSTOM_BUILD_ID="12345678" - CONFIG_PXE_ROM_ID="8086,1539" -+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" - CONFIG_SEABIOS_DEBUG_LEVEL=0 - CONFIG_SEABIOS_REVISION=y - CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" --- -2.39.2 - diff --git a/patches/0006-payloads-seabios-use-PC-Engines-repository.patch b/patches/0006-payloads-seabios-use-PC-Engines-repository.patch new file mode 100644 index 0000000..506f06f --- /dev/null +++ b/patches/0006-payloads-seabios-use-PC-Engines-repository.patch @@ -0,0 +1,72 @@ +From f492e2d7156612d3766b1f9d8921a3a55f218ef5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= +Date: Wed, 8 May 2024 13:40:23 +0200 +Subject: [PATCH 06/88] payloads/seabios: use PC Engines repository +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Upstream-Status: Pending +Signed-off-by: Piotr Król +--- + configs/config.pcengines_seabios_apu2 | 2 ++ + configs/config.pcengines_seabios_apu3 | 2 ++ + configs/config.pcengines_seabios_apu4 | 2 ++ + payloads/external/SeaBIOS/Makefile | 2 +- + 4 files changed, 7 insertions(+), 1 deletion(-) + +diff --git a/configs/config.pcengines_seabios_apu2 b/configs/config.pcengines_seabios_apu2 +index 7058b2c7cc..27614f10dc 100644 +--- a/configs/config.pcengines_seabios_apu2 ++++ b/configs/config.pcengines_seabios_apu2 +@@ -17,6 +17,8 @@ CONFIG_POST_IO_PORT=0x80 + CONFIG_PXE=y + CONFIG_PXE_ROM_ID="8086,157b" + CONFIG_SEABIOS_DEBUG_LEVEL=0 ++CONFIG_SEABIOS_REVISION=y ++CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" + CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 + CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 + CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +diff --git a/configs/config.pcengines_seabios_apu3 b/configs/config.pcengines_seabios_apu3 +index 91758066ac..fc513d5c43 100644 +--- a/configs/config.pcengines_seabios_apu3 ++++ b/configs/config.pcengines_seabios_apu3 +@@ -18,6 +18,8 @@ CONFIG_POST_IO_PORT=0x80 + CONFIG_PXE=y + CONFIG_PXE_ROM_ID="8086,1539" + CONFIG_SEABIOS_DEBUG_LEVEL=0 ++CONFIG_SEABIOS_REVISION=y ++CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" + CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 + CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 + CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +diff --git a/configs/config.pcengines_seabios_apu4 b/configs/config.pcengines_seabios_apu4 +index c1ad2636f1..b4610152ef 100644 +--- a/configs/config.pcengines_seabios_apu4 ++++ b/configs/config.pcengines_seabios_apu4 +@@ -18,6 +18,8 @@ CONFIG_POST_IO_PORT=0x80 + CONFIG_PXE=y + CONFIG_PXE_ROM_ID="8086,1539" + CONFIG_SEABIOS_DEBUG_LEVEL=0 ++CONFIG_SEABIOS_REVISION=y ++CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" + CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 + CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 + CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile +index 7926f3fb90..5bdd526296 100644 +--- a/payloads/external/SeaBIOS/Makefile ++++ b/payloads/external/SeaBIOS/Makefile +@@ -2,7 +2,7 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master + TAG-$(CONFIG_SEABIOS_STABLE)=a6ed6b701f0a57db0569ab98b0661c12a6ec3ff8 + TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID) + +-project_git_repo=https://review.coreboot.org/seabios.git ++project_git_repo=https://github.com/pcengines/seabios.git + project_dir=seabios + + unexport KCONFIG_AUTOHEADER +-- +2.49.0 + diff --git a/patches/0003-payloads-add-support-for-sortbootorder.patch b/patches/0007-payloads-add-support-for-sortbootorder.patch similarity index 72% rename from patches/0003-payloads-add-support-for-sortbootorder.patch rename to patches/0007-payloads-add-support-for-sortbootorder.patch index 7d7e41a..e61362f 100644 --- a/patches/0003-payloads-add-support-for-sortbootorder.patch +++ b/patches/0007-payloads-add-support-for-sortbootorder.patch @@ -1,66 +1,70 @@ -From db841ed5ba62eca838b4d4e5230747d7bf0c72af Mon Sep 17 00:00:00 2001 +From b415a04cd5baae441ee74ac07fbdaec4811b2678 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Mon, 6 May 2024 01:27:38 +0200 -Subject: [PATCH 03/80] payloads: add support for sortbootorder +Subject: [PATCH 07/88] payloads: add support for sortbootorder MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Custom payload] Signed-off-by: Piotr Król -diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2 -index f8e362fa5e34..430e97e9b24a 100644 ---- a/configs/config.pcengines_apu2 -+++ b/configs/config.pcengines_apu2 +--- + configs/config.pcengines_seabios_apu2 | 3 ++ + configs/config.pcengines_seabios_apu3 | 3 ++ + configs/config.pcengines_seabios_apu4 | 3 ++ + payloads/Kconfig | 8 +++ + payloads/Makefile.mk | 1 + + payloads/external/Makefile.mk | 16 ++++++ + .../external/sortbootorder/Kconfig.secondary | 36 +++++++++++++ + payloads/external/sortbootorder/Makefile | 53 +++++++++++++++++++ + 8 files changed, 123 insertions(+) + create mode 100644 payloads/external/sortbootorder/Kconfig.secondary + create mode 100644 payloads/external/sortbootorder/Makefile + +diff --git a/configs/config.pcengines_seabios_apu2 b/configs/config.pcengines_seabios_apu2 +index 27614f10dc..e407412979 100644 +--- a/configs/config.pcengines_seabios_apu2 ++++ b/configs/config.pcengines_seabios_apu2 @@ -20,6 +20,9 @@ CONFIG_SEABIOS_DEBUG_LEVEL=0 CONFIG_SEABIOS_REVISION=y - CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" + CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 +CONFIG_SORTBOOTORDER_REVISION=y -+CONFIG_SORTBOOTORDER_REVISION_ID="v24.05.00.01" ++CONFIG_SORTBOOTORDER_REVISION_ID="v24.08.00.01" +CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_TPM2=y -diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3 -index 0604bb39f83a..6892148d226b 100644 ---- a/configs/config.pcengines_apu3 -+++ b/configs/config.pcengines_apu3 -@@ -12,4 +12,7 @@ CONFIG_PXE_ROM_ID="8086,1539" - CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y +diff --git a/configs/config.pcengines_seabios_apu3 b/configs/config.pcengines_seabios_apu3 +index fc513d5c43..f0ea77b8a7 100644 +--- a/configs/config.pcengines_seabios_apu3 ++++ b/configs/config.pcengines_seabios_apu3 +@@ -20,6 +20,9 @@ CONFIG_PXE_ROM_ID="8086,1539" + CONFIG_SEABIOS_DEBUG_LEVEL=0 CONFIG_SEABIOS_REVISION=y - CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" + CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" +CONFIG_SORTBOOTORDER_REVISION=y -+CONFIG_SORTBOOTORDER_REVISION_ID="v24.05.00.01" ++CONFIG_SORTBOOTORDER_REVISION_ID="v24.08.00.01" +CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y - CONFIG_VENDOR_PCENGINES=y -diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4 -index 7548f07e5573..29e39103854d 100644 ---- a/configs/config.pcengines_apu4 -+++ b/configs/config.pcengines_apu4 + CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 + CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 + CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +diff --git a/configs/config.pcengines_seabios_apu4 b/configs/config.pcengines_seabios_apu4 +index b4610152ef..3a8b61cca6 100644 +--- a/configs/config.pcengines_seabios_apu4 ++++ b/configs/config.pcengines_seabios_apu4 @@ -21,6 +21,9 @@ CONFIG_SEABIOS_DEBUG_LEVEL=0 CONFIG_SEABIOS_REVISION=y - CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" + CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 +CONFIG_SORTBOOTORDER_REVISION=y -+CONFIG_SORTBOOTORDER_REVISION_ID="v24.05.00.01" ++CONFIG_SORTBOOTORDER_REVISION_ID="v24.08.00.01" +CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_TPM2=y -diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5 -index 3ad06d2cfbd5..e2d8f4420c83 100644 ---- a/configs/config.pcengines_apu5 -+++ b/configs/config.pcengines_apu5 -@@ -12,4 +12,7 @@ CONFIG_PXE_ROM_ID="8086,1539" - CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y - CONFIG_SEABIOS_REVISION=y - CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" -+CONFIG_SORTBOOTORDER_REVISION=y -+CONFIG_SORTBOOTORDER_REVISION_ID="v24.05.00.01" -+CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y - CONFIG_VENDOR_PCENGINES=y diff --git a/payloads/Kconfig b/payloads/Kconfig -index ec1d40c99207..65e5e894dc30 100644 +index ec1d40c992..65e5e894dc 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -175,6 +175,14 @@ config TINT_SECONDARY_PAYLOAD @@ -79,7 +83,7 @@ index ec1d40c99207..65e5e894dc30 100644 bool "Load coreDOOM as a secondary payload" default n diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk -index a2336aa876a7..d31283957624 100644 +index 5f988dac1b..537eaf5cd4 100644 --- a/payloads/Makefile.mk +++ b/payloads/Makefile.mk @@ -24,6 +24,7 @@ payloads/external/U-Boot \ @@ -91,7 +95,7 @@ index a2336aa876a7..d31283957624 100644 payloads/external/GRUB2 \ payloads/external/LinuxBoot \ diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk -index c227402ee5db..56be9b598c8e 100644 +index 53693f5917..e5fad06845 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -341,6 +341,22 @@ payloads/external/Memtest86Plus/$(memtest_dir)/memtest: $(DOTCONFIG) @@ -119,7 +123,7 @@ index c227402ee5db..56be9b598c8e 100644 PXE_ROM_PCI_ID:=$(subst $(comma),,$(CONFIG_PXE_ROM_ID)) diff --git a/payloads/external/sortbootorder/Kconfig.secondary b/payloads/external/sortbootorder/Kconfig.secondary new file mode 100644 -index 000000000000..5d70dbb1c086 +index 0000000000..5d70dbb1c0 --- /dev/null +++ b/payloads/external/sortbootorder/Kconfig.secondary @@ -0,0 +1,36 @@ @@ -161,7 +165,7 @@ index 000000000000..5d70dbb1c086 +endif diff --git a/payloads/external/sortbootorder/Makefile b/payloads/external/sortbootorder/Makefile new file mode 100644 -index 000000000000..dd922d7020e6 +index 0000000000..dd922d7020 --- /dev/null +++ b/payloads/external/sortbootorder/Makefile @@ -0,0 +1,53 @@ @@ -218,3 +222,6 @@ index 000000000000..dd922d7020e6 + echo "$(project_git_repo) $(project_dir)" + +.PHONY: checkout build clean distclean fetch sortbootorder print-repo-info +-- +2.49.0 + diff --git a/patches/0004-mainboard-pcengines-Add-support-for-bootorder-files-.patch b/patches/0008-mainboard-pcengines-Add-support-for-bootorder-files-.patch similarity index 72% rename from patches/0004-mainboard-pcengines-Add-support-for-bootorder-files-.patch rename to patches/0008-mainboard-pcengines-Add-support-for-bootorder-files-.patch index e21c8a2..35a9311 100644 --- a/patches/0004-mainboard-pcengines-Add-support-for-bootorder-files-.patch +++ b/patches/0008-mainboard-pcengines-Add-support-for-bootorder-files-.patch @@ -1,15 +1,35 @@ -From 3e8611d43a58c5994c8dcb2b5aabadf654507f4d Mon Sep 17 00:00:00 2001 +From a9203c93c00a8baeb13a37a3c85376d61de91be0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Mon, 6 May 2024 01:35:25 +0200 -Subject: [PATCH 04/80] mainboard/pcengines: Add support for bootorder files to +Subject: [PATCH 08/88] mainboard/pcengines: Add support for bootorder files to SeaBIOS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Pending Signed-off-by: Piotr Król +--- + payloads/external/Makefile.mk | 36 ++++++++++++++++++ + payloads/external/SeaBIOS/Kconfig | 30 +++++++++++++++ + src/mainboard/pcengines/apu2/boot-menu-key | Bin 0 -> 8 bytes + .../pcengines/apu2/boot-menu-message | 1 + + src/mainboard/pcengines/apu2/boot-menu-wait | Bin 0 -> 8 bytes + src/mainboard/pcengines/apu2/bootorder_def | 10 +++++ + src/mainboard/pcengines/apu2/bootorder_map | 10 +++++ + .../pcengines/apu2/variants/apu2/bootorder | Bin 0 -> 4096 bytes + .../pcengines/apu2/variants/apu4/bootorder | Bin 0 -> 4096 bytes + 9 files changed, 87 insertions(+) + create mode 100644 src/mainboard/pcengines/apu2/boot-menu-key + create mode 100644 src/mainboard/pcengines/apu2/boot-menu-message + create mode 100644 src/mainboard/pcengines/apu2/boot-menu-wait + create mode 100644 src/mainboard/pcengines/apu2/bootorder_def + create mode 100644 src/mainboard/pcengines/apu2/bootorder_map + create mode 100644 src/mainboard/pcengines/apu2/variants/apu2/bootorder + create mode 100644 src/mainboard/pcengines/apu2/variants/apu4/bootorder + diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk -index 56be9b598c8e..66b140334a41 100644 +index e5fad06845..f6529366fe 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -103,6 +103,42 @@ ifneq ($(strip $(CONFIG_SEABIOS_BOOTORDER_FILE)),) @@ -56,7 +76,7 @@ index 56be9b598c8e..66b140334a41 100644 ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig -index b12af46a14a3..d676934dbaae 100644 +index b12af46a14..d676934dba 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -109,6 +109,36 @@ config SEABIOS_BOOTORDER_FILE @@ -108,7 +128,7 @@ HcmV?d00001 diff --git a/src/mainboard/pcengines/apu2/boot-menu-message b/src/mainboard/pcengines/apu2/boot-menu-message new file mode 100644 -index 000000000000..2b61487904a4 +index 0000000000..2b61487904 --- /dev/null +++ b/src/mainboard/pcengines/apu2/boot-menu-message @@ -0,0 +1 @@ @@ -125,7 +145,7 @@ HcmV?d00001 diff --git a/src/mainboard/pcengines/apu2/bootorder_def b/src/mainboard/pcengines/apu2/bootorder_def new file mode 100644 -index 000000000000..bc27c4834981 +index 0000000000..bc27c48349 --- /dev/null +++ b/src/mainboard/pcengines/apu2/bootorder_def @@ -0,0 +1,10 @@ @@ -141,7 +161,7 @@ index 000000000000..bc27c4834981 +/rom@genroms/pxe.rom diff --git a/src/mainboard/pcengines/apu2/bootorder_map b/src/mainboard/pcengines/apu2/bootorder_map new file mode 100644 -index 000000000000..e3e7551e6496 +index 0000000000..e3e7551e64 --- /dev/null +++ b/src/mainboard/pcengines/apu2/bootorder_map @@ -0,0 +1,10 @@ @@ -160,11 +180,11 @@ new file mode 100644 index 0000000000000000000000000000000000000000..51b0fea1741238d986b4b47ac678fb344312d04b GIT binary patch literal 4096 -zcmeH@OK!s;5Qek1h +zcmeIqL2kn!5J1tak+{RGt)zhKrtOZKR5pz5QEae)RLSitXVq3ky}-Q92tJJ399hzC +zd{fsvSflrGYOIk$RZ?3|&-K*(NR2h!@%8tWQ9jWpTCF_gi`BJm{_2~f(~!tdXxrn9 +zYW6MlZPnM`cBi=72}6o&R@)7qQe36jZWy!_*~MU_xaI*LvronC=ROs0q`=wH07cIqsF~%5Uj4{R-`&XGM!$=E4K=c_(gaM(`?`Ih91v4x$Oh5r*@|gCFp-{r* +VzW-XlK;8((rOz{DbS0*P6kkeli1z>h literal 0 HcmV?d00001 @@ -174,12 +194,15 @@ new file mode 100644 index 0000000000000000000000000000000000000000..2d8efc15d84d9efb9751835a7b3e64a20de2412b GIT binary patch literal 4096 -zcmeH@OK!v<42EYNDR=OCG*gl^eeJkOm4K62!$1VI>fFAj-Si=DU^c(a@0UKc8`9L7 -z -zP7mr>rqriZtAEUn;i^~kEJ^Jjc*jB8aNzl{WP)c#X`QerL;Kb#W>a!j%Zi(!ulg%5 -z#NpMr3pXF+2>~G>1cZPP5CTF#2nYcoAOwVf5U3K!8zorCA$UZaAP1Nc#_r`2=3B-D -jF8CG5Lx>h*vC(IW=x(LUK@VvsSlpC0NN941hqn0yO>~P* +zcmeIqOK!s;5P;#Vk+{RGt)zgPzINQCvSDnGVuJ;wN^W1#ZrZBcV7|==ei*eovZUSg +zs;+soM%QubtdT-BQr}LG?R5T?I&03ym%mp=`9vRRweplNR=2wOukVgdV +Date: Mon, 6 May 2024 01:36:08 +0200 +Subject: [PATCH 09/88] configs: add support for bootorder files for PC Engines +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Upstream-Status: Pending +Signed-off-by: Piotr Król +--- + configs/config.pcengines_seabios_apu2 | 1 + + configs/config.pcengines_seabios_apu3 | 1 + + configs/config.pcengines_seabios_apu4 | 1 + + .../pcengines/apu2/variants/apu3/bootorder | Bin 0 -> 4096 bytes + 4 files changed, 3 insertions(+) + create mode 100644 src/mainboard/pcengines/apu2/variants/apu3/bootorder + +diff --git a/configs/config.pcengines_seabios_apu2 b/configs/config.pcengines_seabios_apu2 +index e407412979..e967f28613 100644 +--- a/configs/config.pcengines_seabios_apu2 ++++ b/configs/config.pcengines_seabios_apu2 +@@ -16,6 +16,7 @@ CONFIG_NO_GFX_INIT=y + CONFIG_POST_IO_PORT=0x80 + CONFIG_PXE=y + CONFIG_PXE_ROM_ID="8086,157b" ++CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" + CONFIG_SEABIOS_DEBUG_LEVEL=0 + CONFIG_SEABIOS_REVISION=y + CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" +diff --git a/configs/config.pcengines_seabios_apu3 b/configs/config.pcengines_seabios_apu3 +index f0ea77b8a7..2aa97943af 100644 +--- a/configs/config.pcengines_seabios_apu3 ++++ b/configs/config.pcengines_seabios_apu3 +@@ -17,6 +17,7 @@ CONFIG_NO_GFX_INIT=y + CONFIG_POST_IO_PORT=0x80 + CONFIG_PXE=y + CONFIG_PXE_ROM_ID="8086,1539" ++CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" + CONFIG_SEABIOS_DEBUG_LEVEL=0 + CONFIG_SEABIOS_REVISION=y + CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" +diff --git a/configs/config.pcengines_seabios_apu4 b/configs/config.pcengines_seabios_apu4 +index 3a8b61cca6..28bc2bb00d 100644 +--- a/configs/config.pcengines_seabios_apu4 ++++ b/configs/config.pcengines_seabios_apu4 +@@ -17,6 +17,7 @@ CONFIG_NO_GFX_INIT=y + CONFIG_POST_IO_PORT=0x80 + CONFIG_PXE=y + CONFIG_PXE_ROM_ID="8086,1539" ++CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" + CONFIG_SEABIOS_DEBUG_LEVEL=0 + CONFIG_SEABIOS_REVISION=y + CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" +diff --git a/src/mainboard/pcengines/apu2/variants/apu3/bootorder b/src/mainboard/pcengines/apu2/variants/apu3/bootorder +new file mode 100644 +index 0000000000000000000000000000000000000000..51b0fea1741238d986b4b47ac678fb344312d04b +GIT binary patch +literal 4096 +zcmeIqL2kn!5J1tak+{RGt)zhKrtOZKR5pz5QEae)RLSitXVq3ky}-Q92tJJ399hzC +zd{fsvSflrGYOIk$RZ?3|&-K*(NR2h!@%8tWQ9jWpTCF_gi`BJm{_2~f(~!tdXxrn9 +zYW6MlZPnM`cBi=72}6o&R@)7qQe36jZWy!_*~MU_xaI*LvronC=ROs0q`=wH07cIqsF~%5Uj4{R-`&XGM!$=E4K=c_(gaM(`?`Ih91v4x$Oh5r*@|gCFp-{r* +VzW-XlK;8((rOz{DbS0*P6kkeli1z>h + +literal 0 +HcmV?d00001 + +-- +2.49.0 + diff --git a/patches/0006-mainboard-pcengines-add-support-for-bios-knobs.patch b/patches/0010-mainboard-pcengines-add-support-for-bios-knobs.patch similarity index 93% rename from patches/0006-mainboard-pcengines-add-support-for-bios-knobs.patch rename to patches/0010-mainboard-pcengines-add-support-for-bios-knobs.patch index 8f7635d..286e52b 100644 --- a/patches/0006-mainboard-pcengines-add-support-for-bios-knobs.patch +++ b/patches/0010-mainboard-pcengines-add-support-for-bios-knobs.patch @@ -1,14 +1,23 @@ -From 4e4f6771056115d36b0c2ca9c8a537015b6d9471 Mon Sep 17 00:00:00 2001 +From 60638ee0557dcc546f32838051bb89e343c28b90 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Mon, 6 May 2024 11:55:14 +0200 -Subject: [PATCH 06/80] mainboard/pcengines: add support for bios knobs +Subject: [PATCH 10/88] mainboard/pcengines: add support for bios knobs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Piotr Król +--- + src/mainboard/pcengines/apu2/Makefile.mk | 4 + + src/mainboard/pcengines/apu2/bios_knobs.c | 360 ++++++++++++++++++++++ + src/mainboard/pcengines/apu2/bios_knobs.h | 34 ++ + 3 files changed, 398 insertions(+) + create mode 100644 src/mainboard/pcengines/apu2/bios_knobs.c + create mode 100644 src/mainboard/pcengines/apu2/bios_knobs.h + diff --git a/src/mainboard/pcengines/apu2/Makefile.mk b/src/mainboard/pcengines/apu2/Makefile.mk -index 93df43d17dd8..37ac356e332a 100644 +index 93df43d17d..37ac356e33 100644 --- a/src/mainboard/pcengines/apu2/Makefile.mk +++ b/src/mainboard/pcengines/apu2/Makefile.mk @@ -2,10 +2,14 @@ @@ -28,7 +37,7 @@ index 93df43d17dd8..37ac356e332a 100644 ramstage-y += gpio_ftns.c diff --git a/src/mainboard/pcengines/apu2/bios_knobs.c b/src/mainboard/pcengines/apu2/bios_knobs.c new file mode 100644 -index 000000000000..2dfbaccaab9c +index 0000000000..2dfbaccaab --- /dev/null +++ b/src/mainboard/pcengines/apu2/bios_knobs.c @@ -0,0 +1,360 @@ @@ -394,7 +403,7 @@ index 000000000000..2dfbaccaab9c +} diff --git a/src/mainboard/pcengines/apu2/bios_knobs.h b/src/mainboard/pcengines/apu2/bios_knobs.h new file mode 100644 -index 000000000000..b61167553605 +index 0000000000..b611675536 --- /dev/null +++ b/src/mainboard/pcengines/apu2/bios_knobs.h @@ -0,0 +1,34 @@ @@ -432,3 +441,6 @@ index 000000000000..b61167553605 +char *get_bootorder(void); + +#endif +-- +2.49.0 + diff --git a/patches/0007-drivers-spi-add-secure-registers-support-for-winbond.patch b/patches/0011-drivers-spi-add-secure-registers-support-for-winbond.patch similarity index 87% rename from patches/0007-drivers-spi-add-secure-registers-support-for-winbond.patch rename to patches/0011-drivers-spi-add-secure-registers-support-for-winbond.patch index efe7fe7..b82d2ec 100644 --- a/patches/0007-drivers-spi-add-secure-registers-support-for-winbond.patch +++ b/patches/0011-drivers-spi-add-secure-registers-support-for-winbond.patch @@ -1,9 +1,10 @@ -From 56e076b250d2301a6f9c50dfcfc02c44b3b85d45 Mon Sep 17 00:00:00 2001 +From 0625e390b88c8eca4cf9dd4667bbb4cfb3f5d37f Mon Sep 17 00:00:00 2001 From: Kamil Wcislo Date: Wed, 22 Nov 2017 15:27:41 +0100 -Subject: [PATCH 07/80] drivers/spi: add secure registers support for winbond +Subject: [PATCH 11/88] drivers/spi: add secure registers support for winbond chips +Upstream-Status: Pending Signed-off-by: Kamil Wcislo --- src/drivers/spi/spi_flash.c | 6 +++ @@ -13,10 +14,10 @@ Signed-off-by: Kamil Wcislo 4 files changed, 91 insertions(+), 1 deletion(-) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c -index 5d78b6124baf..107d1be8451d 100644 +index 11597c6c1d..bde0a45e7c 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c -@@ -573,6 +573,12 @@ int spi_flash_status(const struct spi_flash *flash, u8 *reg) +@@ -607,6 +607,12 @@ int spi_flash_status(const struct spi_flash *flash, u8 *reg) return -1; } @@ -30,7 +31,7 @@ index 5d78b6124baf..107d1be8451d 100644 const struct region *region) { diff --git a/src/drivers/spi/spi_winbond.h b/src/drivers/spi/spi_winbond.h -index bdf669430681..44f98c389de7 100644 +index bdf6694306..44f98c389d 100644 --- a/src/drivers/spi/spi_winbond.h +++ b/src/drivers/spi/spi_winbond.h @@ -18,6 +18,11 @@ @@ -46,10 +47,10 @@ index bdf669430681..44f98c389de7 100644 /* tw: Maximum time to write a flash cell in milliseconds */ #define WINBOND_FLASH_TIMEOUT 30 diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c -index 32bcc791277c..791857820fe0 100644 +index db93ff616c..d3a6f75284 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c -@@ -240,6 +240,66 @@ static const struct spi_flash_part_id flash_table[] = { +@@ -249,6 +249,66 @@ static const struct spi_flash_part_id flash_table[] = { }, }; @@ -116,7 +117,7 @@ index 32bcc791277c..791857820fe0 100644 /* * Convert BPx, TB and CMP to a region. * SEC (if available) must be zero. -@@ -563,6 +623,20 @@ static const struct spi_flash_protection_ops spi_flash_protection_ops = { +@@ -610,6 +670,20 @@ static const struct spi_flash_protection_ops spi_flash_protection_ops = { .set_write = winbond_set_write_protection, }; @@ -137,7 +138,7 @@ index 32bcc791277c..791857820fe0 100644 const struct spi_flash_vendor_info spi_flash_winbond_vi = { .id = VENDOR_ID_WINBOND, .page_size_shift = 8, -@@ -570,6 +644,6 @@ const struct spi_flash_vendor_info spi_flash_winbond_vi = { +@@ -617,6 +691,6 @@ const struct spi_flash_vendor_info spi_flash_winbond_vi = { .match_id_mask[0] = 0xffff, .ids = flash_table, .nr_part_ids = ARRAY_SIZE(flash_table), @@ -146,7 +147,7 @@ index 32bcc791277c..791857820fe0 100644 .prot_ops = &spi_flash_protection_ops, }; diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h -index fe77e3ef794c..7104bfda1860 100644 +index d5471a4406..40db17fece 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -47,6 +47,8 @@ struct spi_flash_ops { @@ -157,8 +158,8 @@ index fe77e3ef794c..7104bfda1860 100644 + void *buf); }; - /* Current code assumes all callbacks are supplied in this object. */ -@@ -145,6 +147,8 @@ int spi_flash_write(const struct spi_flash *flash, u32 offset, size_t len, + struct spi_flash_bpbits { +@@ -156,6 +158,8 @@ int spi_flash_write(const struct spi_flash *flash, u32 offset, size_t len, const void *buf); int spi_flash_erase(const struct spi_flash *flash, u32 offset, size_t len); int spi_flash_status(const struct spi_flash *flash, u8 *reg); @@ -167,7 +168,7 @@ index fe77e3ef794c..7104bfda1860 100644 /* * Return the vendor dependent SPI flash write protection state. -@@ -160,6 +164,7 @@ int spi_flash_status(const struct spi_flash *flash, u8 *reg); +@@ -171,6 +175,7 @@ int spi_flash_status(const struct spi_flash *flash, u8 *reg); */ int spi_flash_is_write_protected(const struct spi_flash *flash, const struct region *region); @@ -176,5 +177,5 @@ index fe77e3ef794c..7104bfda1860 100644 * Enable the vendor dependent SPI flash write protection. The region not * covered by write-protection will be set to write-able state. -- -2.39.2 +2.49.0 diff --git a/patches/0008-src-southbridge-amd-pi-hudson-add-necessary-files-an.patch b/patches/0012-src-southbridge-amd-pi-hudson-add-necessary-files-an.patch similarity index 91% rename from patches/0008-src-southbridge-amd-pi-hudson-add-necessary-files-an.patch rename to patches/0012-src-southbridge-amd-pi-hudson-add-necessary-files-an.patch index b66f305..7311742 100644 --- a/patches/0008-src-southbridge-amd-pi-hudson-add-necessary-files-an.patch +++ b/patches/0012-src-southbridge-amd-pi-hudson-add-necessary-files-an.patch @@ -1,12 +1,13 @@ -From 84566ee7eac21b1d37250145c883ce15d9d8fef3 Mon Sep 17 00:00:00 2001 +From fba5c432ce32c5bc745d8868e4c7404eb1f09c10 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 25 May 2021 12:05:11 +0200 -Subject: [PATCH 08/80] src/southbridge/amd/pi/hudson: add necessary files and +Subject: [PATCH 12/88] src/southbridge/amd/pi/hudson: add necessary files and functions to use AMD SPI block MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Pending Signed-off-by: Michał Żygowski --- src/southbridge/amd/pi/hudson/early_setup.c | 6 ++++++ @@ -20,7 +21,7 @@ Signed-off-by: Michał Żygowski create mode 100644 src/southbridge/amd/pi/hudson/soc/pci_devs.h diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c -index 1e1a2f44aec6..7df11f7f0a01 100644 +index 1e1a2f44ae..7df11f7f0a 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -6,6 +6,7 @@ @@ -44,7 +45,7 @@ index 1e1a2f44aec6..7df11f7f0a01 100644 { uintptr_t base = hudson_spibase(); diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c -index ccca1138e7f7..aa6971a19dec 100644 +index 66ec82414f..c7c56e0a01 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -1,6 +1,7 @@ @@ -55,7 +56,7 @@ index ccca1138e7f7..aa6971a19dec 100644 #include #include #include -@@ -318,6 +319,18 @@ static void hudson_lpc_enable_resources(struct device *dev) +@@ -314,6 +315,18 @@ static void hudson_lpc_enable_resources(struct device *dev) hudson_lpc_enable_childrens_resources(dev); } @@ -76,7 +77,7 @@ index ccca1138e7f7..aa6971a19dec 100644 if (dev->path.type != DEVICE_PATH_PCI) diff --git a/src/southbridge/amd/pi/hudson/soc/iomap.h b/src/southbridge/amd/pi/hudson/soc/iomap.h new file mode 100644 -index 000000000000..df40f0fe7148 +index 0000000000..df40f0fe71 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/soc/iomap.h @@ -0,0 +1,6 @@ @@ -88,7 +89,7 @@ index 000000000000..df40f0fe7148 +#endif /* SOC_IOMAP_H */ diff --git a/src/southbridge/amd/pi/hudson/soc/lpc.h b/src/southbridge/amd/pi/hudson/soc/lpc.h new file mode 100644 -index 000000000000..0c966e938382 +index 0000000000..0c966e9383 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/soc/lpc.h @@ -0,0 +1,13 @@ @@ -107,7 +108,7 @@ index 000000000000..0c966e938382 +#endif /* SOC_LPC_H */ diff --git a/src/southbridge/amd/pi/hudson/soc/pci_devs.h b/src/southbridge/amd/pi/hudson/soc/pci_devs.h new file mode 100644 -index 000000000000..747ccfc0884b +index 0000000000..747ccfc088 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/soc/pci_devs.h @@ -0,0 +1,21 @@ @@ -133,5 +134,5 @@ index 000000000000..747ccfc0884b + +#endif /* SOC_PCI_DEVS_H */ -- -2.39.2 +2.49.0 diff --git a/patches/0009-src-southbridge-amd-pi-hudson-use-AMD-common-SPI-blo.patch b/patches/0013-src-southbridge-amd-pi-hudson-use-AMD-common-SPI-blo.patch similarity index 76% rename from patches/0009-src-southbridge-amd-pi-hudson-use-AMD-common-SPI-blo.patch rename to patches/0013-src-southbridge-amd-pi-hudson-use-AMD-common-SPI-blo.patch index 86a41cb..485c574 100644 --- a/patches/0009-src-southbridge-amd-pi-hudson-use-AMD-common-SPI-blo.patch +++ b/patches/0013-src-southbridge-amd-pi-hudson-use-AMD-common-SPI-blo.patch @@ -1,15 +1,20 @@ -From 54d910aea93e3c4138d88962f3bd73272887091e Mon Sep 17 00:00:00 2001 +From f0772ada5c92d91922abc01787cc2a7085df7d8b Mon Sep 17 00:00:00 2001 From: Kamil Wcislo Date: Wed, 22 Nov 2017 15:26:10 +0100 -Subject: [PATCH 09/80] src/southbridge/amd/pi/hudson: use AMD common SPI block +Subject: [PATCH 13/88] src/southbridge/amd/pi/hudson: use AMD common SPI block MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Pending Signed-off-by: Kamil Wcislo Signed-off-by: Michał Żygowski +--- + src/southbridge/amd/pi/hudson/Kconfig | 3 +++ + 1 file changed, 3 insertions(+) + diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig -index 134b57546d21..cd80868127af 100644 +index 134b57546d..cd80868127 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -24,6 +24,9 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS @@ -22,3 +27,6 @@ index 134b57546d21..cd80868127af 100644 select USE_AMDFWTOOL config EHCI_BAR +-- +2.49.0 + diff --git a/patches/0010-mainboard-pcengines-add-support-for-getting-sku-and-.patch b/patches/0014-mainboard-pcengines-add-support-for-getting-sku-and-.patch similarity index 87% rename from patches/0010-mainboard-pcengines-add-support-for-getting-sku-and-.patch rename to patches/0014-mainboard-pcengines-add-support-for-getting-sku-and-.patch index 3ab6d29..4509cbd 100644 --- a/patches/0010-mainboard-pcengines-add-support-for-getting-sku-and-.patch +++ b/patches/0014-mainboard-pcengines-add-support-for-getting-sku-and-.patch @@ -1,7 +1,7 @@ -From 5579e630cdc463ad25d3b7165d772ab72f7dc341 Mon Sep 17 00:00:00 2001 +From adc21b16034b61d6c93d8b0286e038d4bb1e2f8c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Mon, 21 Nov 2016 23:45:47 +0100 -Subject: [PATCH 10/80] mainboard/pcengines: add support for getting sku and +Subject: [PATCH 14/88] mainboard/pcengines: add support for getting sku and serial number MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -20,10 +20,15 @@ serial number in the NIC is not set. The commit also includes necessary includes and defines for the new functionality. The obtained information is exposed in SMBIOS tables. +Upstream-Status: Pending Signed-off-by: Maciej Pijanowski Signed-off-by: Piotr Król +--- + src/mainboard/pcengines/apu2/mainboard.c | 63 ++++++++++++++++++++---- + 1 file changed, 53 insertions(+), 10 deletions(-) + diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c -index ac5c92871f88..586f697a80d5 100644 +index 242ad9d932..1c3f80acb8 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -1,5 +1,9 @@ @@ -36,14 +41,12 @@ index ac5c92871f88..586f697a80d5 100644 #include #include #include -@@ -17,12 +21,17 @@ +@@ -17,12 +21,15 @@ #include #include - #include + #include -#include -+ +#include -+ #include "gpio_ftns.h" +#include "bios_knobs.h" @@ -55,7 +58,7 @@ index ac5c92871f88..586f697a80d5 100644 /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. -@@ -263,23 +272,21 @@ static void mainboard_final(void *chip_info) +@@ -263,23 +270,21 @@ static void mainboard_final(void *chip_info) * We will stuff a modified version of the first NICs (BDF 1:0.0) MAC address * into the smbios serial number location. */ @@ -85,7 +88,7 @@ index ac5c92871f88..586f697a80d5 100644 /* Read in the last 3 bytes of NIC's MAC address. */ bar10 = pci_read_config32(dev, PCI_BASE_ADDRESS_0); -@@ -293,7 +300,45 @@ const char *smbios_mainboard_serial_number(void) +@@ -293,7 +298,45 @@ const char *smbios_mainboard_serial_number(void) mac_addr /= 4; mac_addr -= 64; @@ -132,3 +135,6 @@ index ac5c92871f88..586f697a80d5 100644 return serial; } +-- +2.49.0 + diff --git a/patches/0011-mainboard-pcengines-add-function-to-check-whether-CO.patch b/patches/0015-mainboard-pcengines-add-function-to-check-whether-CO.patch similarity index 89% rename from patches/0011-mainboard-pcengines-add-function-to-check-whether-CO.patch rename to patches/0015-mainboard-pcengines-add-function-to-check-whether-CO.patch index f2a47c4..e5131ed 100644 --- a/patches/0011-mainboard-pcengines-add-function-to-check-whether-CO.patch +++ b/patches/0015-mainboard-pcengines-add-function-to-check-whether-CO.patch @@ -1,12 +1,13 @@ -From d898c3e4c9b996355152611f83e0609d87b07907 Mon Sep 17 00:00:00 2001 +From 2e3ee8e81bd6c77fa2744dd866e325d6422c9453 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Mon, 6 May 2024 13:32:03 +0200 -Subject: [PATCH 11/80] mainboard/pcengines: add function to check whether COM2 +Subject: [PATCH 15/88] mainboard/pcengines: add function to check whether COM2 redirection enabled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Piotr Król --- src/mainboard/pcengines/apu2/bios_knobs.c | 76 ++++++++++++++++++++++- @@ -14,7 +15,7 @@ Signed-off-by: Piotr Król 2 files changed, 76 insertions(+), 1 deletion(-) diff --git a/src/mainboard/pcengines/apu2/bios_knobs.c b/src/mainboard/pcengines/apu2/bios_knobs.c -index 2dfbaccaab9c..1f237fc4d63a 100644 +index 2dfbaccaab..1f237fc4d6 100644 --- a/src/mainboard/pcengines/apu2/bios_knobs.c +++ b/src/mainboard/pcengines/apu2/bios_knobs.c @@ -96,6 +96,79 @@ static u8 check_knob_value(const char *s) @@ -108,7 +109,7 @@ index 2dfbaccaab9c..1f237fc4d63a 100644 } diff --git a/src/mainboard/pcengines/apu2/bios_knobs.h b/src/mainboard/pcengines/apu2/bios_knobs.h -index b61167553605..1e3560b20755 100644 +index b611675536..1e3560b207 100644 --- a/src/mainboard/pcengines/apu2/bios_knobs.h +++ b/src/mainboard/pcengines/apu2/bios_knobs.h @@ -19,6 +19,7 @@ @@ -120,5 +121,5 @@ index b61167553605..1e3560b20755 100644 u8 check_uartd(void); u8 check_ehci0(void); -- -2.39.2 +2.49.0 diff --git a/patches/0012-mainboard-pcengines-add-memory-configuration-and-sta.patch b/patches/0016-mainboard-pcengines-add-memory-configuration-and-sta.patch similarity index 76% rename from patches/0012-mainboard-pcengines-add-memory-configuration-and-sta.patch rename to patches/0016-mainboard-pcengines-add-memory-configuration-and-sta.patch index 7274f9d..9fcfc3a 100644 --- a/patches/0012-mainboard-pcengines-add-memory-configuration-and-sta.patch +++ b/patches/0016-mainboard-pcengines-add-memory-configuration-and-sta.patch @@ -1,7 +1,7 @@ -From 2be4672add7851c728ed70397a2ede59df9fbda2 Mon Sep 17 00:00:00 2001 +From de0e6e427776fef5142443271ea287c4f3590c15 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Wed, 30 Nov 2016 17:55:46 +0100 -Subject: [PATCH 12/80] mainboard/pcengines: add memory configuration and +Subject: [PATCH 16/88] mainboard/pcengines: add memory configuration and status logging MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -15,12 +15,18 @@ as well. This additional logging will assist in debugging and system analysis, and ensure that the boot process is compatible with legacy systems and meets customer expectations. +Upstream-Status: Inappropriate [Custom prints that are not necessary] Signed-off-by: Piotr Król +--- + src/lib/Makefile.mk | 1 + + src/mainboard/pcengines/apu2/mainboard.c | 32 +++++++++++++++++++++++- + 2 files changed, 32 insertions(+), 1 deletion(-) + diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk -index e22fd087238f..bb466820beb5 100644 +index 56d8b1afd5..a983390b4e 100644 --- a/src/lib/Makefile.mk +++ b/src/lib/Makefile.mk -@@ -360,6 +360,7 @@ $(foreach stage,$(libhwbase-stages), \ +@@ -359,6 +359,7 @@ $(foreach stage,$(libhwbase-stages), \ endif # CONFIG_ROMSTAGE_LIBHWBASE || CONFIG_RAMSTAGE_LIBHWBASE romstage-y += spd_bin.c @@ -29,19 +35,19 @@ index e22fd087238f..bb466820beb5 100644 ifeq ($(CONFIG_HAVE_SPD_IN_CBFS),y) LIB_SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c -index 586f697a80d5..92a0c7b72ba1 100644 +index 1c3f80acb8..9f5f53c263 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c -@@ -22,6 +22,8 @@ +@@ -21,6 +21,8 @@ + #include #include - #include - + #include +#include +#include #include - #include "gpio_ftns.h" -@@ -238,10 +240,34 @@ static int mainboard_smbios_data(struct device *dev, int *handle, + #include "bios_knobs.h" +@@ -236,10 +238,34 @@ static int mainboard_smbios_data(struct device *dev, int *handle, static void mainboard_enable(struct device *dev) { /* Maintain this text unchanged for manufacture process. */ @@ -77,7 +83,7 @@ index 586f697a80d5..92a0c7b72ba1 100644 // // Enable the RTC output // -@@ -252,6 +278,10 @@ static void mainboard_enable(struct device *dev) +@@ -250,6 +276,10 @@ static void mainboard_enable(struct device *dev) // pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); @@ -88,3 +94,6 @@ index 586f697a80d5..92a0c7b72ba1 100644 /* Initialize the PIRQ data structures for consumption */ pirq_setup(); #if CONFIG(GENERATE_SMBIOS_TABLES) +-- +2.49.0 + diff --git a/patches/0013-mainboard-pcengines-enable-power-on-after-power-fail.patch b/patches/0017-mainboard-pcengines-enable-power-on-after-power-fail.patch similarity index 83% rename from patches/0013-mainboard-pcengines-enable-power-on-after-power-fail.patch rename to patches/0017-mainboard-pcengines-enable-power-on-after-power-fail.patch index 4a9316d..d8db20d 100644 --- a/patches/0013-mainboard-pcengines-enable-power-on-after-power-fail.patch +++ b/patches/0017-mainboard-pcengines-enable-power-on-after-power-fail.patch @@ -1,7 +1,7 @@ -From b58cadc0f107075e51c0512c4664fa08e4c5d990 Mon Sep 17 00:00:00 2001 +From 47f26f4eba473c9eac3d33869345ccf91eaacf48 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Mon, 13 May 2024 15:20:19 +0200 -Subject: [PATCH 13/80] mainboard/pcengines: enable power on after power +Subject: [PATCH 17/88] mainboard/pcengines: enable power on after power failure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -13,16 +13,17 @@ been added and a bit manipulation operation has been included to set the necessary bit for this feature. This change improves the robustness of the system in case of unexpected power outages. +Upstream-Status: Pending Signed-off-by: Piotr Król --- src/mainboard/pcengines/apu2/mainboard.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c -index c7617cf564d6..725375de1be0 100644 +index 9f5f53c263..09a6605d0a 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c -@@ -35,8 +35,10 @@ +@@ -28,8 +28,10 @@ #include "bios_knobs.h" #define SPD_SIZE 128 @@ -35,7 +36,7 @@ index c7617cf564d6..725375de1be0 100644 #define SEC_REG_SERIAL_ADDR 0x1000 #define MAX_SERIAL_LEN 10 -@@ -282,6 +284,8 @@ static void mainboard_enable(struct device *dev) +@@ -276,6 +278,8 @@ static void mainboard_enable(struct device *dev) // pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); @@ -45,5 +46,5 @@ index c7617cf564d6..725375de1be0 100644 -- -2.39.2 +2.49.0 diff --git a/patches/0014-mainboard-pcengines-Enable-GENINTx-as-GPIO.patch b/patches/0018-mainboard-pcengines-Enable-GENINTx-as-GPIO.patch similarity index 78% rename from patches/0014-mainboard-pcengines-Enable-GENINTx-as-GPIO.patch rename to patches/0018-mainboard-pcengines-Enable-GENINTx-as-GPIO.patch index 745413a..3fcf9c6 100644 --- a/patches/0014-mainboard-pcengines-Enable-GENINTx-as-GPIO.patch +++ b/patches/0018-mainboard-pcengines-Enable-GENINTx-as-GPIO.patch @@ -1,21 +1,22 @@ -From 098596d69bb4411bc0e3fc559f50dd5f59555889 Mon Sep 17 00:00:00 2001 +From 4a641872c09db7b154a7b7a8f9d1037b27bb66f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Mon, 6 May 2024 17:29:04 +0200 -Subject: [PATCH 14/80] mainboard/pcengines: Enable GENINTx as GPIO +Subject: [PATCH 18/88] mainboard/pcengines: Enable GENINTx as GPIO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Pending Signed-off-by: Piotr Król --- src/mainboard/pcengines/apu2/mainboard.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c -index 725375de1be0..c18d5c0f5fe1 100644 +index 09a6605d0a..8cff46bb0c 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c -@@ -38,6 +38,7 @@ +@@ -31,6 +31,7 @@ #define PM_RTC_CONTROL 0x56 #define PM_RTC_SHADOW 0x5B #define PM_S_STATE_CONTROL 0xBA @@ -23,7 +24,7 @@ index 725375de1be0..c18d5c0f5fe1 100644 #define SEC_REG_SERIAL_ADDR 0x1000 #define MAX_SERIAL_LEN 10 -@@ -287,8 +288,8 @@ static void mainboard_enable(struct device *dev) +@@ -281,8 +282,8 @@ static void mainboard_enable(struct device *dev) /* Enable power on after power fail */ pm_write8(PM_RTC_SHADOW, pm_read8(PM_RTC_SHADOW) | (1 << 0)); @@ -35,5 +36,5 @@ index 725375de1be0..c18d5c0f5fe1 100644 /* Initialize the PIRQ data structures for consumption */ pirq_setup(); -- -2.39.2 +2.49.0 diff --git a/patches/0018-mainboard-pcengines-add-apu3-and-apu5-variants.patch b/patches/0018-mainboard-pcengines-add-apu3-and-apu5-variants.patch deleted file mode 100644 index eb65ae1..0000000 --- a/patches/0018-mainboard-pcengines-add-apu3-and-apu5-variants.patch +++ /dev/null @@ -1,253 +0,0 @@ -From aa66769361a226929a7c33469748e082013e1b5d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= -Date: Thu, 2 May 2024 23:09:19 +0200 -Subject: [PATCH 18/80] mainboard/pcengines: add apu3 and apu5 variants -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Piotr Król -diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3 -index 6892148d226b..41d4551fa470 100644 ---- a/configs/config.pcengines_apu3 -+++ b/configs/config.pcengines_apu3 -@@ -1,18 +1,31 @@ --# CONFIG_COLLECT_TIMESTAMPS is not set -+# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set -+# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set - # CONFIG_IPXE_SERIAL_CONSOLE is not set --CONFIG_APU2_PINMUX_UART_C=y --CONFIG_APU2_PINMUX_UART_D=y -+CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000 - CONFIG_BOARD_PCENGINES_APU3=y -+CONFIG_BOTTOMIO_POSITION=0xD0000000 - CONFIG_BUILD_IPXE=y -+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y -+CONFIG_HUDSON_SATA_MODE=2 -+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -+CONFIG_IPXE_ADD_SCRIPT=y -+CONFIG_LOCALVERSION="v24.05.00.01" - CONFIG_MEMTEST86PLUS_V5=y - CONFIG_MEMTEST_SECONDARY_PAYLOAD=y - CONFIG_NO_GFX_INIT=y -+CONFIG_POST_IO_PORT=0x80 - CONFIG_PXE=y - CONFIG_PXE_ROM_ID="8086,1539" --CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y -+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" -+CONFIG_SEABIOS_DEBUG_LEVEL=0 - CONFIG_SEABIOS_REVISION=y - CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" -+CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 - CONFIG_SORTBOOTORDER_REVISION=y - CONFIG_SORTBOOTORDER_REVISION_ID="v24.05.00.01" - CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y -+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 -+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 -+CONFIG_TPM2=y - CONFIG_VENDOR_PCENGINES=y -diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5 -index e2d8f4420c83..dd3047f0a3a0 100644 ---- a/configs/config.pcengines_apu5 -+++ b/configs/config.pcengines_apu5 -@@ -1,18 +1,31 @@ --# CONFIG_COLLECT_TIMESTAMPS is not set -+# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set -+# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set - # CONFIG_IPXE_SERIAL_CONSOLE is not set --CONFIG_APU2_PINMUX_UART_C=y --CONFIG_APU2_PINMUX_UART_D=y -+CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000 - CONFIG_BOARD_PCENGINES_APU5=y -+CONFIG_BOTTOMIO_POSITION=0xD0000000 - CONFIG_BUILD_IPXE=y -+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y -+CONFIG_HUDSON_SATA_MODE=2 -+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -+CONFIG_IPXE_ADD_SCRIPT=y -+CONFIG_LOCALVERSION="v24.05.00.01" - CONFIG_MEMTEST86PLUS_V5=y - CONFIG_MEMTEST_SECONDARY_PAYLOAD=y - CONFIG_NO_GFX_INIT=y -+CONFIG_POST_IO_PORT=0x80 - CONFIG_PXE=y - CONFIG_PXE_ROM_ID="8086,1539" --CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y -+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" -+CONFIG_SEABIOS_DEBUG_LEVEL=0 - CONFIG_SEABIOS_REVISION=y - CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" -+CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 - CONFIG_SORTBOOTORDER_REVISION=y - CONFIG_SORTBOOTORDER_REVISION_ID="v24.05.00.01" - CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y -+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 -+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 -+CONFIG_TPM2=y - CONFIG_VENDOR_PCENGINES=y -diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig -index d676934dbaae..3a343fefab92 100644 ---- a/payloads/external/SeaBIOS/Kconfig -+++ b/payloads/external/SeaBIOS/Kconfig -@@ -111,12 +111,14 @@ config SEABIOS_BOOTORDER_FILE - - config SEABIOS_BOOTORDER_MAP_FILE - string "SeaBIOS bootorder_map file" -+ default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/bootorder_map_apu5" if BOARD_PCENGINES_APU5 - default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/bootorder_map" - help - TBD - - config SEABIOS_BOOTORDER_DEF_FILE - string "SeaBIOS bootorder_def file" -+ default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/bootorder_def_apu5" if BOARD_PCENGINES_APU5 - default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/bootorder_def" - help - TBD -diff --git a/src/mainboard/pcengines/apu2/bootorder_def_apu5 b/src/mainboard/pcengines/apu2/bootorder_def_apu5 -new file mode 100644 -index 000000000000..5f562f2468ab ---- /dev/null -+++ b/src/mainboard/pcengines/apu2/bootorder_def_apu5 -@@ -0,0 +1,30 @@ -+/pci@i0cf8/usb@10/usb-*@1 -+/pci@i0cf8/usb@10/usb-*@2 -+/pci@i0cf8/usb@10/usb-*@3 -+/pci@i0cf8/usb@10/usb-*@4 -+/pci@i0cf8/usb@12/usb-*@1 -+/pci@i0cf8/usb@12/usb-*@2 -+/pci@i0cf8/usb@12/usb-*@3 -+/pci@i0cf8/usb@12/usb-*@4 -+/pci@i0cf8/usb@13/usb-*@1 -+/pci@i0cf8/usb@13/usb-*@2 -+/pci@i0cf8/usb@13/usb-*@3 -+/pci@i0cf8/usb@13/usb-*@4 -+/pci@i0cf8/usb@12/hub@1/usb-*@1 -+/pci@i0cf8/*@11/drive@0/disk@0 -+/pci@i0cf8/*@11/drive@1/disk@0 -+/pci@i0cf8/pci-bridge@2,5/*@0/drive@0/disk@0 -+/pci@i0cf8/pci-bridge@2,5/*@0/drive@1/disk@0 -+/rom@genroms/pxe.rom -+pxen0 -+scon1 -+usben1 -+uartc1 -+uartd1 -+ehcien0 -+mpcie2_clk0 -+com2_en0 -+boosten1 -+sd3mode0 -+iommu0 -+watchdog0000 -diff --git a/src/mainboard/pcengines/apu2/bootorder_map_apu5 b/src/mainboard/pcengines/apu2/bootorder_map_apu5 -new file mode 100644 -index 000000000000..f5d47e4ee46c ---- /dev/null -+++ b/src/mainboard/pcengines/apu2/bootorder_map_apu5 -@@ -0,0 +1,18 @@ -+a USB -+a USB -+a USB -+a USB -+a USB -+a USB -+a USB -+a USB -+a USB -+a USB -+a USB -+a USB -+b SDCARD -+c mSATA -+d SATA -+e mPCIe1 SATA1 and SATA2 -+e mPCIe1 SATA1 and SATA2 -+f iPXE -diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c -index 79bbf8c3d9da..dc1ab76eeeeb 100644 ---- a/src/mainboard/pcengines/apu2/mainboard.c -+++ b/src/mainboard/pcengines/apu2/mainboard.c -@@ -28,6 +28,7 @@ - - #include "gpio_ftns.h" - #include "bios_knobs.h" -+#include "s1_button.h" - - #define SPD_SIZE 128 - #define PM_RTC_CONTROL 0x56 -@@ -301,6 +302,18 @@ static void mainboard_final(void *chip_info) - // - gpio_set(GPIO_58, 1); - gpio_set(GPIO_59, 1); -+ -+ if (!check_console()) { -+ /*The console is disabled, check if S1 is pressed and enable if so */ -+#if CONFIG(BOARD_PCENGINES_APU5) -+ if (!gpio_get(GPIO_22)) { -+#else -+ if (!gpio_get(GPIO_32)) { -+#endif -+ printk(BIOS_INFO, "S1 PRESSED\n"); -+ enable_console(); -+ } -+ } - } - - /* -diff --git a/src/mainboard/pcengines/apu2/variants/apu3/bootorder b/src/mainboard/pcengines/apu2/variants/apu3/bootorder -new file mode 100644 -index 0000000000000000000000000000000000000000..51b0fea1741238d986b4b47ac678fb344312d04b -GIT binary patch -literal 4096 -zcmeH@OK!s;5Qek1h - -literal 0 -HcmV?d00001 - -diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb -index 5c169208b9cf..eb0777b489ce 100644 ---- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb -+++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb -@@ -3,7 +3,7 @@ - chip northbridge/amd/pi/00730F01 - device domain 0 on - subsystemid 0x1022 0x1410 inherit -- device ref iommu on end -+ device ref iommu off end - device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) - device ref gpp_bridge_1 on end # LAN3 - device ref gpp_bridge_2 on end # LAN2 -diff --git a/src/mainboard/pcengines/apu2/variants/apu5/bootorder b/src/mainboard/pcengines/apu2/variants/apu5/bootorder -new file mode 100644 -index 0000000000000000000000000000000000000000..29c163d69ebbf7f0ac2a8c7bf2c7edcb2293dbc0 -GIT binary patch -literal 4096 -zcmeH@O>V;=5Jt1M(GZi4VMK8{P!|Shg{+BbJ5tJf~u}GpFOk#nK&Ic@Xw* -z)?c`2Crb>70Wly3#DEwO17bi7hygJm2E@R>2FgMiCh`aY(PbzRMub7Xo?yHc%-~~~ -hfda(jFl`t^p@janRe9(juLP4n=LIs_64S12z5rPii1+{i - -literal 0 -HcmV?d00001 - -diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb -index 75cc446e463f..85dcf4a343a8 100644 ---- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb -+++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb -@@ -41,7 +41,7 @@ chip northbridge/amd/pi/00730F01 - device pnp 2e.108 off end - device pnp 2e.f off end - device pnp 2e.007 off end -- device pnp 2e.107 off end -+ device pnp 2e.107 on end - device pnp 2e.607 off end - end # SIO NCT5104D - chip drivers/pc80/tpm diff --git a/patches/0019-gitmodules-fix-the-URLs-for-stand-alone-build.patch b/patches/0019-gitmodules-fix-the-URLs-for-stand-alone-build.patch deleted file mode 100644 index 5ac1577..0000000 --- a/patches/0019-gitmodules-fix-the-URLs-for-stand-alone-build.patch +++ /dev/null @@ -1,102 +0,0 @@ -From e93cbaac68bc0701c9fcbb707324885b79ab6538 Mon Sep 17 00:00:00 2001 -From: Kamil Wcislo -Date: Tue, 25 Apr 2017 11:14:13 +0200 -Subject: [PATCH 19/80] gitmodules: fix the URLs for stand-alone build - -Signed-off-by: Kamil Wcislo ---- - .gitmodules | 34 +++++++++++++++++----------------- - 1 file changed, 17 insertions(+), 17 deletions(-) - -diff --git a/.gitmodules b/.gitmodules -index 6f62952f4351..0b066e82cbda 100644 ---- a/.gitmodules -+++ b/.gitmodules -@@ -1,67 +1,67 @@ - [submodule "3rdparty/blobs"] - path = 3rdparty/blobs -- url = ../blobs.git -+ url = https://review.coreboot.org/blobs.git - update = none - ignore = dirty - [submodule "util/nvidia-cbootimage"] - path = util/nvidia/cbootimage -- url = ../nvidia-cbootimage.git -+ url = https://review.coreboot.org/nvidia-cbootimage.git - [submodule "vboot"] - path = 3rdparty/vboot -- url = ../vboot.git -+ url = https://review.coreboot.org/vboot.git - branch = main - [submodule "arm-trusted-firmware"] - path = 3rdparty/arm-trusted-firmware -- url = ../arm-trusted-firmware.git -+ url = https://review.coreboot.org/arm-trusted-firmware.git - [submodule "3rdparty/chromeec"] - path = 3rdparty/chromeec -- url = ../chrome-ec.git -+ url = https://review.coreboot.org/chrome-ec.git - [submodule "libhwbase"] - path = 3rdparty/libhwbase -- url = ../libhwbase.git -+ url = https://review.coreboot.org/libhwbase.git - [submodule "libgfxinit"] - path = 3rdparty/libgfxinit -- url = ../libgfxinit.git -+ url = https://review.coreboot.org/libgfxinit.git - [submodule "3rdparty/fsp"] - path = 3rdparty/fsp -- url = ../fsp.git -+ url = https://review.coreboot.org/fsp.git - update = none - ignore = dirty - [submodule "opensbi"] - path = 3rdparty/opensbi -- url = ../opensbi.git -+ url = https://review.coreboot.org/opensbi.git - [submodule "intel-microcode"] - path = 3rdparty/intel-microcode -- url = ../intel-microcode.git -+ url = https://review.coreboot.org/intel-microcode.git - update = none - ignore = dirty - branch = main - [submodule "3rdparty/ffs"] - path = 3rdparty/ffs -- url = ../ffs.git -+ url = https://review.coreboot.org/ffs.git - [submodule "3rdparty/amd_blobs"] - path = 3rdparty/amd_blobs -- url = ../amd_blobs -+ url = https://review.coreboot.org/amd_blobs.git - update = none - ignore = dirty - [submodule "3rdparty/cmocka"] - path = 3rdparty/cmocka -- url = ../cmocka.git -+ url = https://review.coreboot.org/cmocka.git - update = none - branch = stable-1.1 - [submodule "3rdparty/qc_blobs"] - path = 3rdparty/qc_blobs -- url = ../qc_blobs.git -+ url = https://review.coreboot.org/qc_blobs.git - update = none - ignore = dirty - [submodule "3rdparty/intel-sec-tools"] - path = 3rdparty/intel-sec-tools -- url = ../9esec-security-tooling.git -+ url = https://review.coreboot.org/9esec-security-tooling.git - [submodule "3rdparty/stm"] - path = 3rdparty/stm -- url = ../STM -+ url = https://review.coreboot.org/STM - branch = stmpe - [submodule "util/goswid"] - path = util/goswid -- url = ../goswid -+ url = https://review.coreboot.org/goswid - branch = trunk --- -2.39.2 - diff --git a/patches/0015-payloads-iPXE-add-support-for-custom-iPXE-general.h-.patch b/patches/0019-payloads-iPXE-add-support-for-custom-iPXE-general.h-.patch similarity index 92% rename from patches/0015-payloads-iPXE-add-support-for-custom-iPXE-general.h-.patch rename to patches/0019-payloads-iPXE-add-support-for-custom-iPXE-general.h-.patch index aaa2ddc..def9f9b 100644 --- a/patches/0015-payloads-iPXE-add-support-for-custom-iPXE-general.h-.patch +++ b/patches/0019-payloads-iPXE-add-support-for-custom-iPXE-general.h-.patch @@ -1,7 +1,7 @@ -From da110d62fad966bf7a35200a1b7255948161f4c1 Mon Sep 17 00:00:00 2001 +From 5ba136d29a60d29d715b6ca30ec6df5c8a6973aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 5 Jul 2019 13:42:39 +0200 -Subject: [PATCH 15/80] payloads/iPXE: add support for custom iPXE general.h +Subject: [PATCH 19/88] payloads/iPXE: add support for custom iPXE general.h and bootmenu file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -17,10 +17,19 @@ and will fail the build process if the specified files do not exist. Additionally, several environment variables related to Kconfig have been unexported to prevent potential conflicts with the iPXE build process. +Upstream-Status: Inappropriate [Use sed for fine-grained feature control] Signed-off-by: Kamil Wcislo Signed-off-by: Michał Żygowski +--- + payloads/external/Makefile.mk | 2 + + payloads/external/iPXE/Kconfig | 6 ++ + payloads/external/iPXE/Makefile | 17 ++- + payloads/external/iPXE/general.h | 178 +++++++++++++++++++++++++++++++ + 4 files changed, 202 insertions(+), 1 deletion(-) + create mode 100644 payloads/external/iPXE/general.h + diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk -index 66b140334a41..46a62d2b2b26 100644 +index f6529366fe..149d35732e 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -429,6 +429,8 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(IPXE_CONFIG_SCRIPT) @@ -33,7 +42,7 @@ index 66b140334a41..46a62d2b2b26 100644 CONFIG_HAS_SCRIPT=$(CONFIG_IPXE_ADD_SCRIPT) \ CONFIG_IPXE_NO_PROMPT=$(CONFIG_IPXE_NO_PROMPT) \ diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig -index 8cf19c3e47c4..23171630f058 100644 +index 19c7abdda9..3f01073743 100644 --- a/payloads/external/iPXE/Kconfig +++ b/payloads/external/iPXE/Kconfig @@ -68,6 +68,12 @@ config IPXE_MASTER @@ -50,7 +59,7 @@ index 8cf19c3e47c4..23171630f058 100644 bool "Enable iPXE serial console" def_bool y diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile -index c1bd3e4474dc..dc28d87662f4 100644 +index 684f7b241c..83fa6b911b 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -11,6 +11,13 @@ project_name=iPXE @@ -82,7 +91,7 @@ index c1bd3e4474dc..dc28d87662f4 100644 ifneq ($(filter y,$(CONFIG_HAS_SCRIPT) $(CONFIG_IPXE_NO_PROMPT)),) cp "$(project_dir)/src/config/general.h" "$(project_dir)/src/config/general.h.cb" endif -@@ -59,7 +74,7 @@ ifeq ($(CONFIG_HAS_SCRIPT),y) +@@ -62,7 +77,7 @@ ifeq ($(CONFIG_HAS_SCRIPT),y) $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom EMBED=$(CONFIG_SCRIPT) else echo " MAKE $(project_name) $(TAG-y)" @@ -93,7 +102,7 @@ index c1bd3e4474dc..dc28d87662f4 100644 ifeq ($(CONSOLE_SERIAL),yy) diff --git a/payloads/external/iPXE/general.h b/payloads/external/iPXE/general.h new file mode 100644 -index 000000000000..1025247a1450 +index 0000000000..1025247a14 --- /dev/null +++ b/payloads/external/iPXE/general.h @@ -0,0 +1,178 @@ @@ -275,3 +284,6 @@ index 000000000000..1025247a1450 +#include LOCAL_NAMED_CONFIG(general.h) + +#endif /* CONFIG_GENERAL_H */ +-- +2.49.0 + diff --git a/patches/0016-payloads-iPXE-Update-Makefile.inc-to-change-PXE-ROM-.patch b/patches/0020-payloads-iPXE-Update-Makefile.inc-to-change-PXE-ROM-.patch similarity index 77% rename from patches/0016-payloads-iPXE-Update-Makefile.inc-to-change-PXE-ROM-.patch rename to patches/0020-payloads-iPXE-Update-Makefile.inc-to-change-PXE-ROM-.patch index 28ef331..7c78673 100644 --- a/patches/0016-payloads-iPXE-Update-Makefile.inc-to-change-PXE-ROM-.patch +++ b/patches/0020-payloads-iPXE-Update-Makefile.inc-to-change-PXE-ROM-.patch @@ -1,14 +1,19 @@ -From 4fae77e23a8ffb1560bf990781d46402481943ca Mon Sep 17 00:00:00 2001 +From f6b5b7253a8710505063865ce58a41b51a19952e Mon Sep 17 00:00:00 2001 From: Kamil Wcislo Date: Mon, 23 Jan 2017 17:29:36 +0100 -Subject: [PATCH 16/80] payloads/iPXE: Update Makefile.inc to change PXE ROM +Subject: [PATCH 20/88] payloads/iPXE: Update Makefile.inc to change PXE ROM path Include iPXE ROM as genroms/pxe.rom instead of a device-specific one. +Upstream-Status: Inappropriate [Custom workaround for PXE ROMs in SeaBIOS] Signed-off-by: Kamil Wcislo +--- + payloads/external/Makefile.mk | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk -index 46a62d2b2b26..b4e9567321ad 100644 +index 149d35732e..d2961e0fec 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -410,16 +410,16 @@ ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy) @@ -32,3 +37,6 @@ index 46a62d2b2b26..b4e9567321ad 100644 payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(IPXE_CONFIG_SCRIPT) $(MAKE) -C payloads/external/iPXE all \ CROSS_COMPILE="$(CROSS_COMPILE_$(ARCH-ramstage-y))" \ +-- +2.49.0 + diff --git a/patches/0017-mainboard-pcengines-add-support-for-s1-button.patch b/patches/0021-mainboard-pcengines-add-support-for-s1-button.patch similarity index 88% rename from patches/0017-mainboard-pcengines-add-support-for-s1-button.patch rename to patches/0021-mainboard-pcengines-add-support-for-s1-button.patch index dca72c6..713ffa3 100644 --- a/patches/0017-mainboard-pcengines-add-support-for-s1-button.patch +++ b/patches/0021-mainboard-pcengines-add-support-for-s1-button.patch @@ -1,7 +1,7 @@ -From de2365240911620a38d740815456b9bdb20fe082 Mon Sep 17 00:00:00 2001 +From 1b03955025fd9a3007526e35138398dd952f95af Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Mon, 6 May 2024 18:23:46 +0200 -Subject: [PATCH 17/80] mainboard/pcengines: add support for s1 button +Subject: [PATCH 21/88] mainboard/pcengines: add support for s1 button MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -9,9 +9,18 @@ Content-Transfer-Encoding: 8bit On apu5 the S1 button is not present. Its GPIO is used as a SIMSWAP. +Upstream-Status: Inappropriate [Should be payload's feature] Signed-off-by: Michał Żygowski +--- + src/mainboard/pcengines/apu2/Makefile.mk | 3 + + src/mainboard/pcengines/apu2/s1_button.c | 115 +++++++++++++++++++++++ + src/mainboard/pcengines/apu2/s1_button.h | 16 ++++ + 3 files changed, 134 insertions(+) + create mode 100644 src/mainboard/pcengines/apu2/s1_button.c + create mode 100644 src/mainboard/pcengines/apu2/s1_button.h + diff --git a/src/mainboard/pcengines/apu2/Makefile.mk b/src/mainboard/pcengines/apu2/Makefile.mk -index 37ac356e332a..423726ae10ee 100644 +index 37ac356e33..423726ae10 100644 --- a/src/mainboard/pcengines/apu2/Makefile.mk +++ b/src/mainboard/pcengines/apu2/Makefile.mk @@ -6,13 +6,16 @@ romstage-y += bios_knobs.c @@ -33,7 +42,7 @@ index 37ac356e332a..423726ae10ee 100644 SPD_SOURCES = HYNIX-2G-1333 diff --git a/src/mainboard/pcengines/apu2/s1_button.c b/src/mainboard/pcengines/apu2/s1_button.c new file mode 100644 -index 000000000000..d9e52fa856f4 +index 0000000000..d9e52fa856 --- /dev/null +++ b/src/mainboard/pcengines/apu2/s1_button.c @@ -0,0 +1,115 @@ @@ -154,7 +163,7 @@ index 000000000000..d9e52fa856f4 +} diff --git a/src/mainboard/pcengines/apu2/s1_button.h b/src/mainboard/pcengines/apu2/s1_button.h new file mode 100644 -index 000000000000..8ab399416cb5 +index 0000000000..8ab399416c --- /dev/null +++ b/src/mainboard/pcengines/apu2/s1_button.h @@ -0,0 +1,16 @@ @@ -174,3 +183,6 @@ index 000000000000..8ab399416cb5 + */ + + void enable_console(void); +-- +2.49.0 + diff --git a/patches/0022-mainboard-pcengines-add-apu3-variant.patch b/patches/0022-mainboard-pcengines-add-apu3-variant.patch new file mode 100644 index 0000000..06aa770 --- /dev/null +++ b/patches/0022-mainboard-pcengines-add-apu3-variant.patch @@ -0,0 +1,59 @@ +From a3166ab1edf6f81b83498206e2d18ee2ebeffb5c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=3D=3FUTF-8=3Fq=3FPiotr=3D20Kr=3DC3=3DB3l=3F=3D?= + +Date: Thu, 2 May 2024 23:09:19 +0200 +Subject: [PATCH 22/88] mainboard/pcengines: add apu3 variant +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Upstream-Status: Inappropriate [Should be payload's feature] +Signed-off-by: Piotr Król +--- + src/mainboard/pcengines/apu2/mainboard.c | 9 +++++++++ + src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb | 2 +- + 2 files changed, 10 insertions(+), 1 deletion(-) + +diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c +index 8cff46bb0c..4f8d76539c 100644 +--- a/src/mainboard/pcengines/apu2/mainboard.c ++++ b/src/mainboard/pcengines/apu2/mainboard.c +@@ -26,6 +26,7 @@ + #include + #include "gpio_ftns.h" + #include "bios_knobs.h" ++#include "s1_button.h" + + #define SPD_SIZE 128 + #define PM_RTC_CONTROL 0x56 +@@ -299,6 +300,14 @@ static void mainboard_final(void *chip_info) + // + gpio_set(GPIO_58, 1); + gpio_set(GPIO_59, 1); ++ ++ if (!check_console()) { ++ /*The console is disabled, check if S1 is pressed and enable if so */ ++ if (!gpio_get(GPIO_32)) { ++ printk(BIOS_INFO, "S1 PRESSED\n"); ++ enable_console(); ++ } ++ } + } + + /* +diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +index 5c169208b9..eb0777b489 100644 +--- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb ++++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +@@ -3,7 +3,7 @@ + chip northbridge/amd/pi/00730F01 + device domain 0 on + subsystemid 0x1022 0x1410 inherit +- device ref iommu on end ++ device ref iommu off end + device ref gpp_bridge_0 on end # mPCIe slot 2 (on GFX lane) + device ref gpp_bridge_1 on end # LAN3 + device ref gpp_bridge_2 on end # LAN2 +-- +2.49.0 + diff --git a/patches/0020-mainboard-pcengines-force-GPP3-PCIe-CLK-based-on-Kon.patch b/patches/0023-mainboard-pcengines-force-GPP3-PCIe-CLK-based-on-Kon.patch similarity index 78% rename from patches/0020-mainboard-pcengines-force-GPP3-PCIe-CLK-based-on-Kon.patch rename to patches/0023-mainboard-pcengines-force-GPP3-PCIe-CLK-based-on-Kon.patch index 3e6472a..1aead2a 100644 --- a/patches/0020-mainboard-pcengines-force-GPP3-PCIe-CLK-based-on-Kon.patch +++ b/patches/0023-mainboard-pcengines-force-GPP3-PCIe-CLK-based-on-Kon.patch @@ -1,22 +1,23 @@ -From 959b241ca8a25b3585eae94bfb298e5e63f68f94 Mon Sep 17 00:00:00 2001 +From c4f539da0c547365883dd00a3764391b55fc667e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Tue, 30 Apr 2024 15:36:21 +0200 -Subject: [PATCH 20/80] mainboard/pcengines: force GPP3 PCIe CLK based on +Subject: [PATCH 23/88] mainboard/pcengines: force GPP3 PCIe CLK based on Konfig option for apu2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Pending Signed-off-by: Piotr Król --- src/mainboard/pcengines/apu2/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig -index dd6536c9234d..f98fa1451d04 100644 +index 381bfcbd80..a0100209bf 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig -@@ -96,6 +96,12 @@ endchoice +@@ -93,6 +93,12 @@ endchoice config DIMM_SPD_SIZE default 128 @@ -30,5 +31,5 @@ index dd6536c9234d..f98fa1451d04 100644 bool default y -- -2.39.2 +2.49.0 diff --git a/patches/0021-mainboard-pcengines-use-check_ehci0-in-BiosCallOut.patch b/patches/0024-mainboard-pcengines-use-check_ehci0-in-BiosCallOut.patch similarity index 81% rename from patches/0021-mainboard-pcengines-use-check_ehci0-in-BiosCallOut.patch rename to patches/0024-mainboard-pcengines-use-check_ehci0-in-BiosCallOut.patch index c6f9a69..a1e9fd3 100644 --- a/patches/0021-mainboard-pcengines-use-check_ehci0-in-BiosCallOut.patch +++ b/patches/0024-mainboard-pcengines-use-check_ehci0-in-BiosCallOut.patch @@ -1,18 +1,19 @@ -From 2b744103e99f558a9c73dd76553d52b5feb8bdff Mon Sep 17 00:00:00 2001 +From 4b5ac03708787e34637f575fa957903c7ef37f81 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Mon, 13 May 2024 16:07:36 +0200 -Subject: [PATCH 21/80] mainboard/pcengines: use check_ehci0 in BiosCallOut +Subject: [PATCH 24/88] mainboard/pcengines: use check_ehci0 in BiosCallOut MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Piotr Król --- src/mainboard/pcengines/apu2/BiosCallOuts.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c -index efd88d8c127c..5962392dc3eb 100644 +index c78dda6ecb..9b8518cdb0 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -10,6 +10,7 @@ @@ -33,5 +34,5 @@ index efd88d8c127c..5962392dc3eb 100644 // Enable EHCI 1 (port 4 to 7) -- -2.39.2 +2.49.0 diff --git a/patches/0024-mb-apu2-locate-the-bootorder-in-CBFS-and-read-it-fro.patch b/patches/0024-mb-apu2-locate-the-bootorder-in-CBFS-and-read-it-fro.patch deleted file mode 100644 index 601d9e4..0000000 --- a/patches/0024-mb-apu2-locate-the-bootorder-in-CBFS-and-read-it-fro.patch +++ /dev/null @@ -1,30 +0,0 @@ -From d4b0bb1b971906e489d394ce243b2e05b4842595 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= -Date: Mon, 26 Mar 2018 10:34:48 +0200 -Subject: [PATCH 24/80] mb/apu2: locate the bootorder in CBFS and read it from - flash -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Michał Żygowski ---- - src/mainboard/pcengines/apu2/mainboard.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c -index 066e2ac98c33..1771dbb4ae3e 100644 ---- a/src/mainboard/pcengines/apu2/mainboard.c -+++ b/src/mainboard/pcengines/apu2/mainboard.c -@@ -44,6 +44,8 @@ - #define SEC_REG_SERIAL_ADDR 0x1000 - #define MAX_SERIAL_LEN 10 - -+#define BOOTORDER_FILE "bootorder" -+ - /*********************************************************** - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and --- -2.39.2 - diff --git a/patches/0022-mainboard-pcengines-use-bios-knobs.patch b/patches/0025-mainboard-pcengines-use-bios-knobs.patch similarity index 78% rename from patches/0022-mainboard-pcengines-use-bios-knobs.patch rename to patches/0025-mainboard-pcengines-use-bios-knobs.patch index 6cbab5d..33b673a 100644 --- a/patches/0022-mainboard-pcengines-use-bios-knobs.patch +++ b/patches/0025-mainboard-pcengines-use-bios-knobs.patch @@ -1,21 +1,22 @@ -From f1716651577218da0d6bf3de7e8d6c34c79ec3a9 Mon Sep 17 00:00:00 2001 +From d637847eb86af8ad2d4fce1adb75b4541f29731c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Mon, 6 May 2024 11:55:33 +0200 -Subject: [PATCH 22/80] mainboard/pcengines: use bios knobs +Subject: [PATCH 25/88] mainboard/pcengines: use bios knobs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Piotr Król --- - src/mainboard/pcengines/apu2/mainboard.c | 57 ++++++++++++++++++------ - 1 file changed, 43 insertions(+), 14 deletions(-) + src/mainboard/pcengines/apu2/mainboard.c | 56 ++++++++++++++++++------ + 1 file changed, 43 insertions(+), 13 deletions(-) diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c -index ed5c2b2f90c9..066e2ac98c33 100644 +index 4f8d76539c..45c83bcf90 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c -@@ -149,19 +149,49 @@ static void config_gpio_mux(void) +@@ -144,19 +144,49 @@ static void config_gpio_mux(void) { struct device *uart, *gpio; @@ -78,14 +79,6 @@ index ed5c2b2f90c9..066e2ac98c33 100644 } /********************************************** -@@ -259,7 +289,6 @@ static void mainboard_enable(struct device *dev) - if(scon) { - printk(BIOS_ALERT, "%d MB", total_mem); - } -- - // - // Read memory configuration from GPIO 49 and 50 - // -- -2.39.2 +2.49.0 diff --git a/patches/0025-mb-pcengines-apu2-mainboard.c-do-not-proceed-with-en.patch b/patches/0025-mb-pcengines-apu2-mainboard.c-do-not-proceed-with-en.patch deleted file mode 100644 index e087581..0000000 --- a/patches/0025-mb-pcengines-apu2-mainboard.c-do-not-proceed-with-en.patch +++ /dev/null @@ -1,146 +0,0 @@ -From 5994f494e34aa38ec48cf30836ba64b6d6c2e78d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= -Date: Tue, 3 Apr 2018 17:19:49 +0200 -Subject: [PATCH 25/80] mb/pcengines/apu2/mainboard.c: do not proceed with - enabling serial when offset invalid -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Michał Żygowski -Signed-off-by: Piotr Król -diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c -index ce55634db902..249614870fd5 100644 ---- a/src/mainboard/pcengines/apu2/mainboard.c -+++ b/src/mainboard/pcengines/apu2/mainboard.c -@@ -22,6 +22,8 @@ - #include - #include - -+#include -+#include - #include - #include - #include -@@ -39,8 +41,6 @@ - #define SEC_REG_SERIAL_ADDR 0x1000 - #define MAX_SERIAL_LEN 10 - --#define BOOTORDER_FILE "bootorder" -- - /*********************************************************** - * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. - * This table is responsible for physically routing the PIC and -@@ -72,7 +72,7 @@ static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { - [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - [0x50] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -- [0x60] = 0x00,0x00,0x1F -+ [0x60] = 0x00,0x00,0x07 - }; - - static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { -@@ -95,7 +95,7 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { - [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - [0x50] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -- [0x60] = 0x00,0x00,0x1F -+ [0x60] = 0x00,0x00,0x07 - }; - - /* -@@ -193,6 +193,19 @@ static void config_gpio_mux(void) - } - } - -+static void measure_amd_blobs(void) -+{ -+ struct region_device rdev; -+ -+ printk(BIOS_DEBUG, "Measuring AMD blobs.\n"); -+ -+ if(fmap_locate_area_as_rdev("PSPDIR", &rdev)) { -+ printk(BIOS_ERR, "Error: Couldn't find PSPDIR region."); -+ return; -+ } -+ tpm_measure_region(&rdev, CONFIG_PCR_RUNTIME_DATA,"PSPDIR"); -+} -+ - /********************************************** - * enable the dedicated function in mainboard. - **********************************************/ -@@ -217,6 +230,24 @@ static int mainboard_smbios_type16(DMI_INFO *agesa_dmi, int *handle, - return len; - } - -+static int ddr_speed_from_bus_speed(int bus) -+{ -+ switch(bus) -+ { -+ case 166: -+ case 216: -+ case 266: -+ case 333: -+ case 1066: -+ case 1666: return bus*2+1; -+ case 556: -+ case 667: -+ case 688: -+ case 813: return bus*2-1; -+ default: return bus*2; -+ } -+} -+ - static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, - unsigned long *current) - { -@@ -236,7 +267,7 @@ static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, - agesa_dmi->T17[0][0][0].BankLocator); - t->memory_type = agesa_dmi->T17[0][0][0].MemoryType; - t->type_detail = *(u16 *)&agesa_dmi->T17[0][0][0].TypeDetail; -- t->speed = agesa_dmi->T17[0][0][0].Speed; -+ t->speed = ddr_speed_from_bus_speed(agesa_dmi->T17[0][0][0].Speed); - t->manufacturer = agesa_dmi->T17[0][0][0].ManufacturerIdCode; - t->serial_number = smbios_add_string(t->eos, - agesa_dmi->T17[0][0][0].SerialNumber); -@@ -244,7 +275,8 @@ static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, - agesa_dmi->T17[0][0][0].PartNumber); - t->attributes = agesa_dmi->T17[0][0][0].Attributes; - t->extended_size = agesa_dmi->T17[0][0][0].ExtSize; -- t->clock_speed = agesa_dmi->T17[0][0][0].ConfigSpeed; -+ t->clock_speed = ddr_speed_from_bus_speed( -+ agesa_dmi->T17[0][0][0].ConfigSpeed); - t->minimum_voltage = 1500; /* From SPD: 1.5V */ - t->maximum_voltage = 1500; - -@@ -308,6 +340,12 @@ static void mainboard_enable(struct device *dev) - // - pm_write16(PM_RTC_CONTROL, pm_read16(PM_RTC_CONTROL) | (1 << 11)); - -+ if (CONFIG(VBOOT_MEASURED_BOOT)) { -+ /* Measure AGESA and PSPDIR */ -+ measure_amd_blobs(); -+ } -+ -+ - // - // Enable power on from WAKE# - // -@@ -321,6 +359,17 @@ static void mainboard_enable(struct device *dev) - - /* Initialize the PIRQ data structures for consumption */ - pirq_setup(); -+ -+ /* Enable IOMMU if activated in config file */ -+ struct device* iommu_dev; -+ iommu_dev = pcidev_on_root(0, 2); -+ -+ if (iommu_dev) { -+ if (check_iommu()) -+ iommu_dev->enabled = 1; -+ else -+ iommu_dev->enabled = 0; -+ } - #if CONFIG(GENERATE_SMBIOS_TABLES) - dev->ops->get_smbios_data = mainboard_smbios_data; - #endif diff --git a/patches/0023-payloads-SeaBIOS-provide-help-for-added-SeaBIOS-opti.patch b/patches/0026-payloads-SeaBIOS-provide-help-for-added-SeaBIOS-opti.patch similarity index 86% rename from patches/0023-payloads-SeaBIOS-provide-help-for-added-SeaBIOS-opti.patch rename to patches/0026-payloads-SeaBIOS-provide-help-for-added-SeaBIOS-opti.patch index a22706a..4c67984 100644 --- a/patches/0023-payloads-SeaBIOS-provide-help-for-added-SeaBIOS-opti.patch +++ b/patches/0026-payloads-SeaBIOS-provide-help-for-added-SeaBIOS-opti.patch @@ -1,12 +1,13 @@ -From c1933a959689c9cae1ae86633db69c8f44c501f8 Mon Sep 17 00:00:00 2001 +From 755bba1c1047f4267afc49fd15bde397f1e0e914 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 22 Dec 2017 17:01:34 +0100 -Subject: [PATCH 23/80] payloads/SeaBIOS: provide help for added SeaBIOS +Subject: [PATCH 26/88] payloads/SeaBIOS: provide help for added SeaBIOS options MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Pending Signed-off-by: Piotr Król --- payloads/external/SeaBIOS/Kconfig | 27 ++++++++++++++++++---- @@ -14,11 +15,11 @@ Signed-off-by: Piotr Król 2 files changed, 29 insertions(+), 5 deletions(-) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig -index 37f01e92e929..5ffb01a747bd 100644 +index d676934dba..990923858e 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig -@@ -112,32 +112,49 @@ config SEABIOS_BOOTORDER_MAP_FILE - default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/bootorder_map_apu5" if BOARD_PCENGINES_APU5 +@@ -113,31 +113,48 @@ config SEABIOS_BOOTORDER_MAP_FILE + string "SeaBIOS bootorder_map file" default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/bootorder_map" help - TBD @@ -26,7 +27,6 @@ index 37f01e92e929..5ffb01a747bd 100644 config SEABIOS_BOOTORDER_DEF_FILE string "SeaBIOS bootorder_def file" - default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/bootorder_def_apu5" if BOARD_PCENGINES_APU5 default "\$(top)/src/mainboard/\$(MAINBOARDDIR)/bootorder_def" help - TBD @@ -73,7 +73,7 @@ index 37f01e92e929..5ffb01a747bd 100644 config SEABIOS_ADD_SERCON_PORT_FILE prompt "Add SeaBIOS sercon-port file to CBFS" diff --git a/src/mainboard/pcengines/apu2/bootorder_def b/src/mainboard/pcengines/apu2/bootorder_def -index bc27c4834981..a27bc92a0e8c 100644 +index bc27c48349..a27bc92a0e 100644 --- a/src/mainboard/pcengines/apu2/bootorder_def +++ b/src/mainboard/pcengines/apu2/bootorder_def @@ -8,3 +8,10 @@ @@ -88,5 +88,5 @@ index bc27c4834981..a27bc92a0e8c 100644 +ehcien0 +mpcie2_clk0 -- -2.39.2 +2.49.0 diff --git a/patches/0027-mb-pcengines-apu2-Measure-PSP-blobs-if-measured-boot.patch b/patches/0027-mb-pcengines-apu2-Measure-PSP-blobs-if-measured-boot.patch new file mode 100644 index 0000000..6ba1597 --- /dev/null +++ b/patches/0027-mb-pcengines-apu2-Measure-PSP-blobs-if-measured-boot.patch @@ -0,0 +1,64 @@ +From efc59cc0d0fbcc48a4314c4cb4d0e2d64af25c00 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= +Date: Fri, 30 May 2025 12:17:40 +0200 +Subject: [PATCH 27/88] mb/pcengines/apu2: Measure PSP blobs if measured boot + enabled +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Upstream-Status: Pending +Signed-off-by: Michał Żygowski +--- + src/mainboard/pcengines/apu2/mainboard.c | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c +index 45c83bcf90..5d25eb3839 100644 +--- a/src/mainboard/pcengines/apu2/mainboard.c ++++ b/src/mainboard/pcengines/apu2/mainboard.c +@@ -21,6 +21,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include +@@ -189,6 +191,19 @@ static void config_gpio_mux(void) + } + } + ++static void measure_amd_blobs(void) ++{ ++ struct region_device rdev; ++ ++ printk(BIOS_DEBUG, "Measuring AMD blobs.\n"); ++ ++ if(fmap_locate_area_as_rdev("PSPDIR", &rdev)) { ++ printk(BIOS_ERR, "Error: Couldn't find PSPDIR region."); ++ return; ++ } ++ tpm_measure_region(&rdev, CONFIG_PCR_RUNTIME_DATA,"PSPDIR"); ++} ++ + /********************************************** + * enable the dedicated function in mainboard. + **********************************************/ +@@ -305,6 +320,12 @@ static void mainboard_enable(struct device *dev) + // + pm_write16(PM_RTC_CONTROL, pm_read16(PM_RTC_CONTROL) | (1 << 11)); + ++ if (CONFIG(TPM_MEASURED_BOOT)) { ++ /* Measure AGESA and PSPDIR */ ++ measure_amd_blobs(); ++ } ++ ++ + // + // Enable power on from WAKE# + // +-- +2.49.0 + diff --git a/patches/0028-mainboard-pcengines-apu2-mainboard.c-Fix-reporting-m.patch b/patches/0028-mainboard-pcengines-apu2-mainboard.c-Fix-reporting-m.patch new file mode 100644 index 0000000..8b468ab --- /dev/null +++ b/patches/0028-mainboard-pcengines-apu2-mainboard.c-Fix-reporting-m.patch @@ -0,0 +1,66 @@ +From 4981beb5e0f05d2ed44f7e8ce98960354ebe2f62 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= +Date: Fri, 30 May 2025 12:18:41 +0200 +Subject: [PATCH 28/88] mainboard/pcengines/apu2/mainboard.c: Fix reporting + memory speed +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Upstream-Status: Pending +Signed-off-by: Michał Żygowski +--- + src/mainboard/pcengines/apu2/mainboard.c | 23 +++++++++++++++++++++-- + 1 file changed, 21 insertions(+), 2 deletions(-) + +diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c +index 5d25eb3839..6b4efe956f 100644 +--- a/src/mainboard/pcengines/apu2/mainboard.c ++++ b/src/mainboard/pcengines/apu2/mainboard.c +@@ -228,6 +228,24 @@ static int mainboard_smbios_type16(DMI_INFO *agesa_dmi, int *handle, + return len; + } + ++static int ddr_speed_from_bus_speed(int bus) ++{ ++ switch(bus) ++ { ++ case 166: ++ case 216: ++ case 266: ++ case 333: ++ case 1066: ++ case 1666: return bus*2+1; ++ case 556: ++ case 667: ++ case 688: ++ case 813: return bus*2-1; ++ default: return bus*2; ++ } ++} ++ + static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, + unsigned long *current) + { +@@ -247,7 +265,7 @@ static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, + agesa_dmi->T17[0][0][0].BankLocator); + t->memory_type = agesa_dmi->T17[0][0][0].MemoryType; + t->type_detail = *(u16 *)&agesa_dmi->T17[0][0][0].TypeDetail; +- t->speed = agesa_dmi->T17[0][0][0].Speed; ++ t->speed = ddr_speed_from_bus_speed(agesa_dmi->T17[0][0][0].Speed); + t->manufacturer = agesa_dmi->T17[0][0][0].ManufacturerIdCode; + t->serial_number = smbios_add_string(t->eos, + agesa_dmi->T17[0][0][0].SerialNumber); +@@ -255,7 +273,8 @@ static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, + agesa_dmi->T17[0][0][0].PartNumber); + t->attributes = agesa_dmi->T17[0][0][0].Attributes; + t->extended_size = agesa_dmi->T17[0][0][0].ExtSize; +- t->clock_speed = agesa_dmi->T17[0][0][0].ConfigSpeed; ++ t->clock_speed = ddr_speed_from_bus_speed( ++ agesa_dmi->T17[0][0][0].ConfigSpeed); + t->minimum_voltage = 1500; /* From SPD: 1.5V */ + t->maximum_voltage = 1500; + +-- +2.49.0 + diff --git a/patches/0028-src-mb-pcengines-apu-add-custom-SeaBIOS-config.patch b/patches/0028-src-mb-pcengines-apu-add-custom-SeaBIOS-config.patch deleted file mode 100644 index 7a9deeb..0000000 --- a/patches/0028-src-mb-pcengines-apu-add-custom-SeaBIOS-config.patch +++ /dev/null @@ -1,100 +0,0 @@ -From 2be8089f2f3a9065a302a1703da895719c34933d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= -Date: Fri, 1 Jun 2018 17:53:28 +0200 -Subject: [PATCH 28/80] src/mb/pcengines/apu: add custom SeaBIOS config -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Michał Żygowski ---- - configs/config.pcengines_apu2 | 1 + - configs/config.pcengines_apu3 | 1 + - configs/config.pcengines_apu4 | 1 + - configs/config.pcengines_apu5 | 1 + - src/mainboard/pcengines/apu2/Kconfig | 4 ++++ - src/mainboard/pcengines/apu2/seabios_config | 9 +++++++++ - 6 files changed, 17 insertions(+) - create mode 100644 src/mainboard/pcengines/apu2/seabios_config - -diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2 -index 9befb0718c62..0608270dd7e1 100644 ---- a/configs/config.pcengines_apu2 -+++ b/configs/config.pcengines_apu2 -@@ -10,6 +10,7 @@ CONFIG_MEMTEST_REVISION=y - CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2" - CONFIG_MEMTEST_SECONDARY_PAYLOAD=y - CONFIG_NO_GFX_INIT=y -+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config" - CONFIG_POST_IO_PORT=0x80 - CONFIG_PXE=y - CONFIG_PXE_CUSTOM_BUILD_ID="12345678" -diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3 -index c892ac090160..8e73c961ec72 100644 ---- a/configs/config.pcengines_apu3 -+++ b/configs/config.pcengines_apu3 -@@ -11,6 +11,7 @@ CONFIG_MEMTEST_REVISION=y - CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2" - CONFIG_MEMTEST_SECONDARY_PAYLOAD=y - CONFIG_NO_GFX_INIT=y -+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config" - CONFIG_POST_IO_PORT=0x80 - CONFIG_PXE=y - CONFIG_PXE_CUSTOM_BUILD_ID="12345678" -diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4 -index d32ecaaf1314..58675eb6139a 100644 ---- a/configs/config.pcengines_apu4 -+++ b/configs/config.pcengines_apu4 -@@ -11,6 +11,7 @@ CONFIG_MEMTEST_REVISION=y - CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2" - CONFIG_MEMTEST_SECONDARY_PAYLOAD=y - CONFIG_NO_GFX_INIT=y -+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config" - CONFIG_POST_IO_PORT=0x80 - CONFIG_PXE=y - CONFIG_PXE_CUSTOM_BUILD_ID="12345678" -diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5 -index 343729c73fc2..687ba8c8bd6c 100644 ---- a/configs/config.pcengines_apu5 -+++ b/configs/config.pcengines_apu5 -@@ -11,6 +11,7 @@ CONFIG_MEMTEST_REVISION=y - CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2" - CONFIG_MEMTEST_SECONDARY_PAYLOAD=y - CONFIG_NO_GFX_INIT=y -+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config" - CONFIG_POST_IO_PORT=0x80 - CONFIG_PXE=y - CONFIG_PXE_CUSTOM_BUILD_ID="12345678" -diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig -index f98fa1451d04..d375f45e1417 100644 ---- a/src/mainboard/pcengines/apu2/Kconfig -+++ b/src/mainboard/pcengines/apu2/Kconfig -@@ -39,6 +39,10 @@ config MAINBOARD_PART_NUMBER - default "apu4" if BOARD_PCENGINES_APU4 - default "apu5" if BOARD_PCENGINES_APU5 - -+config DEFAULT_CONSOLE_LOGLEVEL -+ int -+ default 1 -+ - config MAX_CPUS - int - default 4 -diff --git a/src/mainboard/pcengines/apu2/seabios_config b/src/mainboard/pcengines/apu2/seabios_config -new file mode 100644 -index 000000000000..42b3c6bf0389 ---- /dev/null -+++ b/src/mainboard/pcengines/apu2/seabios_config -@@ -0,0 +1,9 @@ -+CONFIG_ATA_DMA=y -+CONFIG_ATA_PIO32=y -+# CONFIG_BOOTSPLASH is not set -+# CONFIG_MEGASAS is not set -+# CONFIG_FLOPPY is not set -+# CONFIG_PS2PORT is not set -+# CONFIG_USB_UHCI is not set -+# CONFIG_USB_OHCI is not set -+# CONFIG_LPT is not set --- -2.39.2 - diff --git a/patches/0029-mainboard-pcengines-apu2-mainboard.c-Handle-IOMMU-st.patch b/patches/0029-mainboard-pcengines-apu2-mainboard.c-Handle-IOMMU-st.patch new file mode 100644 index 0000000..b9c6733 --- /dev/null +++ b/patches/0029-mainboard-pcengines-apu2-mainboard.c-Handle-IOMMU-st.patch @@ -0,0 +1,40 @@ +From 024c75ac3a92fe7dd4c9ca0c9e89a2b7ec53b43d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= +Date: Fri, 30 May 2025 12:19:19 +0200 +Subject: [PATCH 29/88] mainboard/pcengines/apu2/mainboard.c: Handle IOMMU + state via devicetree +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Upstream-Status: Inappropriate [Should utilize existing option backend] +Signed-off-by: Michał Żygowski +--- + src/mainboard/pcengines/apu2/mainboard.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c +index 6b4efe956f..d4d751ee6d 100644 +--- a/src/mainboard/pcengines/apu2/mainboard.c ++++ b/src/mainboard/pcengines/apu2/mainboard.c +@@ -358,6 +358,17 @@ static void mainboard_enable(struct device *dev) + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); ++ ++ /* Enable IOMMU if activated in config file */ ++ struct device* iommu_dev; ++ iommu_dev = pcidev_on_root(0, 2); ++ ++ if (iommu_dev) { ++ if (check_iommu()) ++ iommu_dev->enabled = 1; ++ else ++ iommu_dev->enabled = 0; ++ } + #if CONFIG(GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_data = mainboard_smbios_data; + #endif +-- +2.49.0 + diff --git a/patches/0030-mb-pcengines-apu2-mainboard.c-Configure-IRQ7-for-GPI.patch b/patches/0030-mb-pcengines-apu2-mainboard.c-Configure-IRQ7-for-GPI.patch new file mode 100644 index 0000000..e80382d --- /dev/null +++ b/patches/0030-mb-pcengines-apu2-mainboard.c-Configure-IRQ7-for-GPI.patch @@ -0,0 +1,40 @@ +From d5d36dcc82bfc41a9400fe64b9f769a175b17c07 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= +Date: Fri, 30 May 2025 12:22:01 +0200 +Subject: [PATCH 30/88] mb/pcengines/apu2/mainboard.c: Configure IRQ7 for GPIO + controller +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Upstream-Status: Pending +Signed-off-by: Michał Żygowski +--- + src/mainboard/pcengines/apu2/mainboard.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c +index d4d751ee6d..e9548f19a4 100644 +--- a/src/mainboard/pcengines/apu2/mainboard.c ++++ b/src/mainboard/pcengines/apu2/mainboard.c +@@ -70,7 +70,7 @@ static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x50] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +- [0x60] = 0x00,0x00,0x1F ++ [0x60] = 0x00,0x00,0x07 + }; + + static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { +@@ -93,7 +93,7 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x50] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +- [0x60] = 0x00,0x00,0x1F ++ [0x60] = 0x00,0x00,0x07 + }; + + /* +-- +2.49.0 + diff --git a/patches/0026-mainboard-pcengines-Fix-ECC-exclusion-range-and-enab.patch b/patches/0031-mainboard-pcengines-Fix-ECC-exclusion-range-and-enab.patch similarity index 90% rename from patches/0026-mainboard-pcengines-Fix-ECC-exclusion-range-and-enab.patch rename to patches/0031-mainboard-pcengines-Fix-ECC-exclusion-range-and-enab.patch index bc4ef13..0e0b318 100644 --- a/patches/0026-mainboard-pcengines-Fix-ECC-exclusion-range-and-enab.patch +++ b/patches/0031-mainboard-pcengines-Fix-ECC-exclusion-range-and-enab.patch @@ -1,7 +1,7 @@ -From cef8b521e98e6ee98db088c2d62b9597ff36a66a Mon Sep 17 00:00:00 2001 +From f9d1a7ffe15691591a0052908595185efc5aca70 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Mon, 13 May 2024 23:18:13 +0200 -Subject: [PATCH 26/80] mainboard/pcengines: Fix ECC exclusion range and enable +Subject: [PATCH 31/88] mainboard/pcengines: Fix ECC exclusion range and enable ECC scrubbing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -17,16 +17,17 @@ reserved bits in register D18F3xB8, disabling the ECC exclusion range, and then re-enabling DRAM ECC scrubbing. This ensures that ECC functions as expected and improves system stability. +Upstream-Status: Submitted [CB:79612] Signed-off-by: Piotr Król --- src/mainboard/pcengines/apu2/mainboard.c | 40 ++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c -index 28023190ca8c..0cfbc697111c 100644 +index 3d909037b1..86e8409acb 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c -@@ -381,6 +381,46 @@ static void mainboard_enable(struct device *dev) +@@ -376,6 +376,46 @@ static void mainboard_enable(struct device *dev) static void mainboard_final(void *chip_info) { @@ -74,5 +75,5 @@ index 28023190ca8c..0cfbc697111c 100644 // Turn off LED 2 and LED 3 // -- -2.39.2 +2.49.0 diff --git a/patches/0027-src-cpu-add-option-to-include-raw-microcode-binary-t.patch b/patches/0032-src-cpu-add-option-to-include-raw-microcode-binary-t.patch similarity index 75% rename from patches/0027-src-cpu-add-option-to-include-raw-microcode-binary-t.patch rename to patches/0032-src-cpu-add-option-to-include-raw-microcode-binary-t.patch index fabc6a4..40b3a8c 100644 --- a/patches/0027-src-cpu-add-option-to-include-raw-microcode-binary-t.patch +++ b/patches/0032-src-cpu-add-option-to-include-raw-microcode-binary-t.patch @@ -1,22 +1,23 @@ -From 78150d393fa10866e749ccc9c328f09991b75041 Mon Sep 17 00:00:00 2001 +From ee47e35e030328fc88fd1eedc6a9211d46c0bbee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 10 May 2018 23:57:21 +0200 -Subject: [PATCH 27/80] src/cpu: add option to include raw microcode binary to +Subject: [PATCH 32/88] src/cpu: add option to include raw microcode binary to CBFS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Microcode is not official, custom workaround] Signed-off-by: Michał Żygowski --- src/cpu/Kconfig | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig -index 297b1a125e60..22605f96ded2 100644 +index 2770f648b4..fd2bf0b5e9 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig -@@ -175,6 +175,11 @@ config CPU_MICROCODE_CBFS_NONE +@@ -171,6 +171,11 @@ config CPU_MICROCODE_CBFS_NONE Make sure you have a way of flashing the ROM externally before selecting this option. @@ -28,7 +29,7 @@ index 297b1a125e60..22605f96ded2 100644 endchoice config CPU_MICROCODE_HEADER_FILES -@@ -186,7 +191,7 @@ config CPU_MICROCODE_HEADER_FILES +@@ -182,7 +187,7 @@ config CPU_MICROCODE_HEADER_FILES config CPU_UCODE_BINARIES string "Microcode binary path and filename" @@ -38,5 +39,5 @@ index 297b1a125e60..22605f96ded2 100644 help Some platforms have microcode in the blobs directory, and these can -- -2.39.2 +2.49.0 diff --git a/patches/0033-src-mb-pcengines-apu-add-custom-SeaBIOS-config.patch b/patches/0033-src-mb-pcengines-apu-add-custom-SeaBIOS-config.patch new file mode 100644 index 0000000..e191453 --- /dev/null +++ b/patches/0033-src-mb-pcengines-apu-add-custom-SeaBIOS-config.patch @@ -0,0 +1,88 @@ +From cef59e7993d21fd9fdf9c38804b6d96364c3acdf Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= +Date: Fri, 1 Jun 2018 17:53:28 +0200 +Subject: [PATCH 33/88] src/mb/pcengines/apu: add custom SeaBIOS config +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Upstream-Status: Pending +Signed-off-by: Michał Żygowski +--- + configs/config.pcengines_seabios_apu2 | 1 + + configs/config.pcengines_seabios_apu3 | 1 + + configs/config.pcengines_seabios_apu4 | 1 + + src/mainboard/pcengines/apu2/Kconfig | 4 ++++ + src/mainboard/pcengines/apu2/seabios_config | 9 +++++++++ + 5 files changed, 16 insertions(+) + create mode 100644 src/mainboard/pcengines/apu2/seabios_config + +diff --git a/configs/config.pcengines_seabios_apu2 b/configs/config.pcengines_seabios_apu2 +index e967f28613..1e1dc875c0 100644 +--- a/configs/config.pcengines_seabios_apu2 ++++ b/configs/config.pcengines_seabios_apu2 +@@ -13,6 +13,7 @@ CONFIG_LOCALVERSION="v24.08.00.01" + CONFIG_MEMTEST86PLUS_V5=y + CONFIG_MEMTEST_SECONDARY_PAYLOAD=y + CONFIG_NO_GFX_INIT=y ++CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config" + CONFIG_POST_IO_PORT=0x80 + CONFIG_PXE=y + CONFIG_PXE_ROM_ID="8086,157b" +diff --git a/configs/config.pcengines_seabios_apu3 b/configs/config.pcengines_seabios_apu3 +index 2aa97943af..c823f4ca16 100644 +--- a/configs/config.pcengines_seabios_apu3 ++++ b/configs/config.pcengines_seabios_apu3 +@@ -14,6 +14,7 @@ CONFIG_LOCALVERSION="v24.08.00.01" + CONFIG_MEMTEST86PLUS_V5=y + CONFIG_MEMTEST_SECONDARY_PAYLOAD=y + CONFIG_NO_GFX_INIT=y ++CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config" + CONFIG_POST_IO_PORT=0x80 + CONFIG_PXE=y + CONFIG_PXE_ROM_ID="8086,1539" +diff --git a/configs/config.pcengines_seabios_apu4 b/configs/config.pcengines_seabios_apu4 +index 28bc2bb00d..f51955a865 100644 +--- a/configs/config.pcengines_seabios_apu4 ++++ b/configs/config.pcengines_seabios_apu4 +@@ -14,6 +14,7 @@ CONFIG_LOCALVERSION="v24.08.00.01" + CONFIG_MEMTEST86PLUS_V5=y + CONFIG_MEMTEST_SECONDARY_PAYLOAD=y + CONFIG_NO_GFX_INIT=y ++CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config" + CONFIG_POST_IO_PORT=0x80 + CONFIG_PXE=y + CONFIG_PXE_ROM_ID="8086,1539" +diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig +index a0100209bf..613cff69cb 100644 +--- a/src/mainboard/pcengines/apu2/Kconfig ++++ b/src/mainboard/pcengines/apu2/Kconfig +@@ -40,6 +40,10 @@ config MAINBOARD_PART_NUMBER + default "apu4" if BOARD_PCENGINES_APU4 + default "apu5" if BOARD_PCENGINES_APU5 + ++config DEFAULT_CONSOLE_LOGLEVEL ++ int ++ default 1 ++ + config MAX_CPUS + int + default 4 +diff --git a/src/mainboard/pcengines/apu2/seabios_config b/src/mainboard/pcengines/apu2/seabios_config +new file mode 100644 +index 0000000000..42b3c6bf03 +--- /dev/null ++++ b/src/mainboard/pcengines/apu2/seabios_config +@@ -0,0 +1,9 @@ ++CONFIG_ATA_DMA=y ++CONFIG_ATA_PIO32=y ++# CONFIG_BOOTSPLASH is not set ++# CONFIG_MEGASAS is not set ++# CONFIG_FLOPPY is not set ++# CONFIG_PS2PORT is not set ++# CONFIG_USB_UHCI is not set ++# CONFIG_USB_OHCI is not set ++# CONFIG_LPT is not set +-- +2.49.0 + diff --git a/patches/0029-nb-amd-pi-00730F01-Add-initial-native-IVRS-support.patch b/patches/0034-nb-amd-pi-00730F01-Add-initial-native-IVRS-support.patch similarity index 83% rename from patches/0029-nb-amd-pi-00730F01-Add-initial-native-IVRS-support.patch rename to patches/0034-nb-amd-pi-00730F01-Add-initial-native-IVRS-support.patch index bbc4183..4a9c529 100644 --- a/patches/0029-nb-amd-pi-00730F01-Add-initial-native-IVRS-support.patch +++ b/patches/0034-nb-amd-pi-00730F01-Add-initial-native-IVRS-support.patch @@ -1,7 +1,7 @@ -From e3ac0b14847ed3747d59e4e490d42ec9346d147d Mon Sep 17 00:00:00 2001 +From 296fece5006740aeae39e25f66b6f1360118fd0f Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 13 Jun 2016 13:48:58 -0500 -Subject: [PATCH 29/80] nb/amd/pi/00730F01: Add initial native IVRS support +Subject: [PATCH 34/88] nb/amd/pi/00730F01: Add initial native IVRS support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -11,11 +11,16 @@ decrease complexity. - Code was structured to satisfy checkpatch Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4 +Upstream-Status: Accepted [CB:79677] Signed-off-by: Timothy Pearson Signed-off-by: Piotr Król Signed-off-by: Michał Witwicki +--- + src/northbridge/amd/pi/00730F01/northbridge.c | 16 ++++++++++------ + 1 file changed, 10 insertions(+), 6 deletions(-) + diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c -index 1be9421c72a2..0f08cddf63a7 100644 +index 1be9421c72..0f08cddf63 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -24,6 +24,8 @@ @@ -48,3 +53,6 @@ index 1be9421c72a2..0f08cddf63a7 100644 /* SRAT */ current = ALIGN_UP(current, 8); +-- +2.49.0 + diff --git a/patches/0030-payloads-external-iPXE-menu.ipxe-enable-autoboot-for.patch b/patches/0035-payloads-external-iPXE-menu.ipxe-enable-autoboot-for.patch similarity index 53% rename from patches/0030-payloads-external-iPXE-menu.ipxe-enable-autoboot-for.patch rename to patches/0035-payloads-external-iPXE-menu.ipxe-enable-autoboot-for.patch index 5509e7d..f21a5d1 100644 --- a/patches/0030-payloads-external-iPXE-menu.ipxe-enable-autoboot-for.patch +++ b/patches/0035-payloads-external-iPXE-menu.ipxe-enable-autoboot-for.patch @@ -1,64 +1,61 @@ -From a8d693c7d10ae3f67f224ff821f0dbaf26494294 Mon Sep 17 00:00:00 2001 +From ade0a0cbd3df2bb91380fb014ec851b4e73414bb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 31 Aug 2018 10:37:01 +0200 -Subject: [PATCH 30/80] payloads/external/iPXE/menu.ipxe: enable autoboot for +Subject: [PATCH 35/88] payloads/external/iPXE/menu.ipxe: enable autoboot for all interfaces MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Pending Signed-off-by: Michał Żygowski -diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2 -index 4cf8467b3997..f0164569d263 100644 ---- a/configs/config.pcengines_apu2 -+++ b/configs/config.pcengines_apu2 +--- + configs/config.pcengines_seabios_apu2 | 1 + + configs/config.pcengines_seabios_apu3 | 1 + + configs/config.pcengines_seabios_apu4 | 1 + + payloads/external/iPXE/menu.ipxe | 17 +++++++++++++++++ + 4 files changed, 20 insertions(+) + create mode 100644 payloads/external/iPXE/menu.ipxe + +diff --git a/configs/config.pcengines_seabios_apu2 b/configs/config.pcengines_seabios_apu2 +index 1e1dc875c0..12535e5357 100644 +--- a/configs/config.pcengines_seabios_apu2 ++++ b/configs/config.pcengines_seabios_apu2 @@ -9,6 +9,7 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y CONFIG_HUDSON_SATA_MODE=2 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="payloads/external/iPXE/menu.ipxe" - CONFIG_LOCALVERSION="v24.05.00.01" + CONFIG_LOCALVERSION="v24.08.00.01" CONFIG_MEMTEST86PLUS_V5=y CONFIG_MEMTEST_SECONDARY_PAYLOAD=y -diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3 -index 91e3cb3d10e4..195edbbdd264 100644 ---- a/configs/config.pcengines_apu3 -+++ b/configs/config.pcengines_apu3 +diff --git a/configs/config.pcengines_seabios_apu3 b/configs/config.pcengines_seabios_apu3 +index c823f4ca16..752b4ab0c6 100644 +--- a/configs/config.pcengines_seabios_apu3 ++++ b/configs/config.pcengines_seabios_apu3 @@ -10,6 +10,7 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y CONFIG_HUDSON_SATA_MODE=2 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="payloads/external/iPXE/menu.ipxe" - CONFIG_LOCALVERSION="v24.05.00.01" + CONFIG_LOCALVERSION="v24.08.00.01" CONFIG_MEMTEST86PLUS_V5=y CONFIG_MEMTEST_SECONDARY_PAYLOAD=y -diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4 -index a393e27a8f7b..18de4b0f34e8 100644 ---- a/configs/config.pcengines_apu4 -+++ b/configs/config.pcengines_apu4 +diff --git a/configs/config.pcengines_seabios_apu4 b/configs/config.pcengines_seabios_apu4 +index f51955a865..8b77bd859b 100644 +--- a/configs/config.pcengines_seabios_apu4 ++++ b/configs/config.pcengines_seabios_apu4 @@ -10,6 +10,7 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y CONFIG_HUDSON_SATA_MODE=2 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="payloads/external/iPXE/menu.ipxe" - CONFIG_LOCALVERSION="v24.05.00.01" - CONFIG_MEMTEST86PLUS_V5=y - CONFIG_MEMTEST_SECONDARY_PAYLOAD=y -diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5 -index 6169e26cbbbd..b155e00bd810 100644 ---- a/configs/config.pcengines_apu5 -+++ b/configs/config.pcengines_apu5 -@@ -10,6 +10,7 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y - CONFIG_HUDSON_SATA_MODE=2 - CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 - CONFIG_IPXE_ADD_SCRIPT=y -+CONFIG_IPXE_SCRIPT="payloads/external/iPXE/menu.ipxe" - CONFIG_LOCALVERSION="v24.05.00.01" + CONFIG_LOCALVERSION="v24.08.00.01" CONFIG_MEMTEST86PLUS_V5=y CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/payloads/external/iPXE/menu.ipxe b/payloads/external/iPXE/menu.ipxe new file mode 100644 -index 000000000000..1b5719588273 +index 0000000000..1b57195882 --- /dev/null +++ b/payloads/external/iPXE/menu.ipxe @@ -0,0 +1,17 @@ @@ -79,3 +76,6 @@ index 000000000000..1b5719588273 +goto MENU + +autoboot +-- +2.49.0 + diff --git a/patches/0031-src-mb-pcengines-apux-bootorder-prepare-bootorder-fi.patch b/patches/0036-src-mb-pcengines-apux-bootorder-prepare-bootorder-fi.patch similarity index 52% rename from patches/0031-src-mb-pcengines-apux-bootorder-prepare-bootorder-fi.patch rename to patches/0036-src-mb-pcengines-apux-bootorder-prepare-bootorder-fi.patch index b153a46..4024bec 100644 --- a/patches/0031-src-mb-pcengines-apux-bootorder-prepare-bootorder-fi.patch +++ b/patches/0036-src-mb-pcengines-apux-bootorder-prepare-bootorder-fi.patch @@ -1,21 +1,23 @@ -From 13fe2bef25689319bd185ebdb8e106ea3bd16767 Mon Sep 17 00:00:00 2001 +From 18b4bc4bb69dd627e9010946e689aa2eb526d854 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 27 Nov 2018 14:31:17 +0100 -Subject: [PATCH 31/80] src/mb/pcengines/apux/bootorder: prepare bootorder +Subject: [PATCH 36/88] src/mb/pcengines/apux/bootorder: prepare bootorder files for COM2 runtime configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Michał Żygowski --- src/mainboard/pcengines/apu2/bootorder_def | 1 + + .../pcengines/apu2/variants/apu2/bootorder | Bin 4096 -> 4096 bytes .../pcengines/apu2/variants/apu3/bootorder | Bin 4096 -> 4096 bytes .../pcengines/apu2/variants/apu4/bootorder | Bin 4096 -> 4096 bytes - 3 files changed, 1 insertion(+) + 4 files changed, 1 insertion(+) diff --git a/src/mainboard/pcengines/apu2/bootorder_def b/src/mainboard/pcengines/apu2/bootorder_def -index a27bc92a0e8c..a314740bde97 100644 +index a27bc92a0e..a314740bde 100644 --- a/src/mainboard/pcengines/apu2/bootorder_def +++ b/src/mainboard/pcengines/apu2/bootorder_def @@ -15,3 +15,4 @@ uartc1 @@ -23,24 +25,33 @@ index a27bc92a0e8c..a314740bde97 100644 ehcien0 mpcie2_clk0 +com2_en0 -diff --git a/src/mainboard/pcengines/apu2/variants/apu3/bootorder b/src/mainboard/pcengines/apu2/variants/apu3/bootorder -index 51b0fea1741238d986b4b47ac678fb344312d04b..2a0dfb2f39bf14f8fd195a7a9744a9ef1e1b51cc 100644 +diff --git a/src/mainboard/pcengines/apu2/variants/apu2/bootorder b/src/mainboard/pcengines/apu2/variants/apu2/bootorder +index 51b0fea1741238d986b4b47ac678fb344312d04b..1d19dba07707caefa7093fda865a2653f3219fa2 100644 GIT binary patch delta 26 -hcmZorXi(UY%gC9WpKFwwXTZg~xscJ6Z}MvXPylXc2mJs5 +hcmZorXi(UY%gC9WpKFwwXTZy~xscJ6Z}MvXPylXf2mJs5 delta 20 bcmZorXi(UY%ec9bQHyW#1V)j`tNB9#NCyU{ -diff --git a/src/mainboard/pcengines/apu2/variants/apu4/bootorder b/src/mainboard/pcengines/apu2/variants/apu4/bootorder -index 2d8efc15d84d9efb9751835a7b3e64a20de2412b..e94b77210661cd7789f90fa4897272994fba86d5 100644 +diff --git a/src/mainboard/pcengines/apu2/variants/apu3/bootorder b/src/mainboard/pcengines/apu2/variants/apu3/bootorder +index 51b0fea1741238d986b4b47ac678fb344312d04b..1d19dba07707caefa7093fda865a2653f3219fa2 100644 GIT binary patch delta 26 -hcmZorXi(Tt%E+0VpKFwwXTZg~xsg$eZ}JNM2mo(K2nqlI +hcmZorXi(UY%gC9WpKFwwXTZy~xscJ6Z}MvXPylXf2mJs5 delta 20 -bcmZorXi(Tt%DB0aQHyW#1V*08tNB9#NLL1? +bcmZorXi(UY%ec9bQHyW#1V)j`tNB9#NCyU{ + +diff --git a/src/mainboard/pcengines/apu2/variants/apu4/bootorder b/src/mainboard/pcengines/apu2/variants/apu4/bootorder +index 2d8efc15d84d9efb9751835a7b3e64a20de2412b..1d19dba07707caefa7093fda865a2653f3219fa2 100644 +GIT binary patch +delta 34 +qcmZorXi(T-&p6qgQI9h@Ki4QV&w!U}b0eb`-{c95+>=-HhXMewQwj_K + +delta 29 +lcmZorXi(T-&&X1oo|rn>n$c);Bcm4I Date: Tue, 27 Nov 2018 14:33:54 +0100 -Subject: [PATCH 32/80] src/drivers/uart/uart8250io.c: set correct serial port +Subject: [PATCH 37/88] src/drivers/uart/uart8250io.c: set correct serial port index according to COM2 status MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Michał Żygowski Signed-off-by: Piotr Król +--- + src/drivers/uart/uart8250io.c | 19 ++++++++++++++----- + src/mainboard/pcengines/apu2/Makefile.mk | 1 + + 2 files changed, 15 insertions(+), 5 deletions(-) + diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c -index a7fc3466f37f..1f33a612cdc2 100644 +index a7fc3466f3..1f33a612cd 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -8,6 +8,8 @@ @@ -72,7 +78,7 @@ index a7fc3466f37f..1f33a612cdc2 100644 serial->regwidth = 1; serial->input_hertz = uart_platform_refclk(); diff --git a/src/mainboard/pcengines/apu2/Makefile.mk b/src/mainboard/pcengines/apu2/Makefile.mk -index 423726ae10ee..e2882d2736c6 100644 +index 423726ae10..e2882d2736 100644 --- a/src/mainboard/pcengines/apu2/Makefile.mk +++ b/src/mainboard/pcengines/apu2/Makefile.mk @@ -1,6 +1,7 @@ @@ -83,3 +89,6 @@ index 423726ae10ee..e2882d2736c6 100644 romstage-y += bios_knobs.c romstage-y += BiosCallOuts.c +-- +2.49.0 + diff --git a/patches/0033-Makefile.inc-include-microcode-patch-inside-firmware.patch b/patches/0038-Makefile.inc-include-microcode-patch-inside-firmware.patch similarity index 68% rename from patches/0033-Makefile.inc-include-microcode-patch-inside-firmware.patch rename to patches/0038-Makefile.inc-include-microcode-patch-inside-firmware.patch index 3d3e5d2..61f2f5a 100644 --- a/patches/0033-Makefile.inc-include-microcode-patch-inside-firmware.patch +++ b/patches/0038-Makefile.inc-include-microcode-patch-inside-firmware.patch @@ -1,18 +1,23 @@ -From 7782d1b612aa674ccf67f23d8ecd126662fd4337 Mon Sep 17 00:00:00 2001 +From 3992e5cc8a3dedb4839b05dc785f8fa8403ff21e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 22 Nov 2018 12:29:52 +0100 -Subject: [PATCH 33/80] Makefile.inc: include microcode patch inside firmware +Subject: [PATCH 38/88] Makefile.inc: include microcode patch inside firmware image MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Microcode is not official] Signed-off-by: Michał Żygowski +--- + Makefile.mk | 3 +++ + 1 file changed, 3 insertions(+) + diff --git a/Makefile.mk b/Makefile.mk -index e642ac7a6edf..65b827fe3eaf 100644 +index 9efef49ba6..cc482acff4 100644 --- a/Makefile.mk +++ b/Makefile.mk -@@ -1255,6 +1255,9 @@ ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) +@@ -1302,6 +1302,9 @@ ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) $(IFITTOOL) -f $@.tmp -D $(TS_OPTIONS) -r COREBOOT endif # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE @@ -22,3 +27,6 @@ index e642ac7a6edf..65b827fe3eaf 100644 mv $@.tmp $@ @printf " CBFSLAYOUT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ layout +-- +2.49.0 + diff --git a/patches/0034-payloads-iPXE-option-for-reproducible-building.patch b/patches/0039-payloads-iPXE-option-for-reproducible-building.patch similarity index 67% rename from patches/0034-payloads-iPXE-option-for-reproducible-building.patch rename to patches/0039-payloads-iPXE-option-for-reproducible-building.patch index b6af748..67c9c15 100644 --- a/patches/0034-payloads-iPXE-option-for-reproducible-building.patch +++ b/patches/0039-payloads-iPXE-option-for-reproducible-building.patch @@ -1,59 +1,57 @@ -From 64a4ffe3f6fcaf8b3bac59c7d44dbca56e9c8b20 Mon Sep 17 00:00:00 2001 +From fd210c0bdcd1058b266e2d93a5db6ac96cd3e7f8 Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Fri, 28 Dec 2018 16:54:40 +0100 -Subject: [PATCH 34/80] payloads/iPXE: option for reproducible building +Subject: [PATCH 39/88] payloads/iPXE: option for reproducible building +Upstream-Status: Submitted [CB:82039] Signed-off-by: Krystian Hebel -diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2 -index feb2b864d6bc..d6acb129de7c 100644 ---- a/configs/config.pcengines_apu2 -+++ b/configs/config.pcengines_apu2 +--- + configs/config.pcengines_seabios_apu2 | 1 + + configs/config.pcengines_seabios_apu3 | 1 + + configs/config.pcengines_seabios_apu4 | 1 + + payloads/external/Makefile.mk | 1 + + payloads/external/iPXE/Kconfig | 7 +++++++ + payloads/external/iPXE/Makefile | 6 +++++- + 6 files changed, 16 insertions(+), 1 deletion(-) + +diff --git a/configs/config.pcengines_seabios_apu2 b/configs/config.pcengines_seabios_apu2 +index 12535e5357..572900c4bb 100644 +--- a/configs/config.pcengines_seabios_apu2 ++++ b/configs/config.pcengines_seabios_apu2 @@ -9,6 +9,7 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y CONFIG_HUDSON_SATA_MODE=2 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_CUSTOM_BUILD_ID="12345678" CONFIG_IPXE_SCRIPT="payloads/external/iPXE/menu.ipxe" - CONFIG_LOCALVERSION="v24.05.00.01" + CONFIG_LOCALVERSION="v24.08.00.01" CONFIG_MEMTEST86PLUS_V5=y -diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3 -index 8d77c74a63e1..754ceb47acf5 100644 ---- a/configs/config.pcengines_apu3 -+++ b/configs/config.pcengines_apu3 +diff --git a/configs/config.pcengines_seabios_apu3 b/configs/config.pcengines_seabios_apu3 +index 752b4ab0c6..0c36d4813b 100644 +--- a/configs/config.pcengines_seabios_apu3 ++++ b/configs/config.pcengines_seabios_apu3 @@ -10,6 +10,7 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y CONFIG_HUDSON_SATA_MODE=2 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_CUSTOM_BUILD_ID="12345678" CONFIG_IPXE_SCRIPT="payloads/external/iPXE/menu.ipxe" - CONFIG_LOCALVERSION="v24.05.00.01" + CONFIG_LOCALVERSION="v24.08.00.01" CONFIG_MEMTEST86PLUS_V5=y -diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4 -index 8ff97305edaf..3f3acd2aa6a6 100644 ---- a/configs/config.pcengines_apu4 -+++ b/configs/config.pcengines_apu4 +diff --git a/configs/config.pcengines_seabios_apu4 b/configs/config.pcengines_seabios_apu4 +index 8b77bd859b..7b737175e6 100644 +--- a/configs/config.pcengines_seabios_apu4 ++++ b/configs/config.pcengines_seabios_apu4 @@ -10,6 +10,7 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y CONFIG_HUDSON_SATA_MODE=2 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_CUSTOM_BUILD_ID="12345678" CONFIG_IPXE_SCRIPT="payloads/external/iPXE/menu.ipxe" - CONFIG_LOCALVERSION="v24.05.00.01" - CONFIG_MEMTEST86PLUS_V5=y -diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5 -index 9fa280cd752c..cb51d2e43cb0 100644 ---- a/configs/config.pcengines_apu5 -+++ b/configs/config.pcengines_apu5 -@@ -10,6 +10,7 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y - CONFIG_HUDSON_SATA_MODE=2 - CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 - CONFIG_IPXE_ADD_SCRIPT=y -+CONFIG_IPXE_CUSTOM_BUILD_ID="12345678" - CONFIG_IPXE_SCRIPT="payloads/external/iPXE/menu.ipxe" - CONFIG_LOCALVERSION="v24.05.00.01" + CONFIG_LOCALVERSION="v24.08.00.01" CONFIG_MEMTEST86PLUS_V5=y diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk -index b4e9567321ad..89b4cd41f44d 100644 +index d2961e0fec..eb6c014d46 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -431,6 +431,7 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(IPXE_CONFIG_SCRIPT) @@ -65,7 +63,7 @@ index b4e9567321ad..89b4cd41f44d 100644 CONFIG_HAS_SCRIPT=$(CONFIG_IPXE_ADD_SCRIPT) \ CONFIG_IPXE_NO_PROMPT=$(CONFIG_IPXE_NO_PROMPT) \ diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig -index 23171630f058..d734bb688e11 100644 +index 3f01073743..b8c30d6c03 100644 --- a/payloads/external/iPXE/Kconfig +++ b/payloads/external/iPXE/Kconfig @@ -83,6 +83,13 @@ config IPXE_SERIAL_CONSOLE @@ -83,7 +81,7 @@ index 23171630f058..d734bb688e11 100644 bool "Do not show prompt to boot from PXE" default n diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile -index dc28d87662f4..908b8cf10c67 100644 +index 83fa6b911b..75aab39074 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -18,6 +18,10 @@ unexport KCONFIG_SPLITCONFIG @@ -97,7 +95,7 @@ index dc28d87662f4..908b8cf10c67 100644 all: build $(project_dir): -@@ -71,7 +75,7 @@ endif +@@ -74,7 +78,7 @@ endif build: config $(CONFIG_SCRIPT) ifeq ($(CONFIG_HAS_SCRIPT),y) echo " MAKE $(project_name) $(TAG-y) EMBED=$(CONFIG_SCRIPT)" @@ -106,3 +104,6 @@ index dc28d87662f4..908b8cf10c67 100644 else echo " MAKE $(project_name) $(TAG-y)" $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom $(PXE_MAKE_OPTS) +-- +2.49.0 + diff --git a/patches/0035-mainboard-pcengines-add-boost-knob-check.patch b/patches/0040-mainboard-pcengines-add-boost-knob-check.patch similarity index 80% rename from patches/0035-mainboard-pcengines-add-boost-knob-check.patch rename to patches/0040-mainboard-pcengines-add-boost-knob-check.patch index a5a9b84..ba74eff 100644 --- a/patches/0035-mainboard-pcengines-add-boost-knob-check.patch +++ b/patches/0040-mainboard-pcengines-add-boost-knob-check.patch @@ -1,18 +1,19 @@ -From abd5ec00c2a084dff0ba1f9a831f6c532b570b72 Mon Sep 17 00:00:00 2001 +From 67e42e3dcd5669cfab53265004f19fd9ed7cf2ac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Mon, 6 May 2024 13:26:50 +0200 -Subject: [PATCH 35/80] mainboard/pcengines: add boost knob check +Subject: [PATCH 38/88] mainboard/pcengines: add boost knob check MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Piotr Król --- src/mainboard/pcengines/apu2/bios_knobs.c | 25 +++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/mainboard/pcengines/apu2/bios_knobs.c b/src/mainboard/pcengines/apu2/bios_knobs.c -index 1f237fc4d63a..5ae0da8e3a57 100644 +index 1f237fc4d6..5ae0da8e3a 100644 --- a/src/mainboard/pcengines/apu2/bios_knobs.c +++ b/src/mainboard/pcengines/apu2/bios_knobs.c @@ -170,6 +170,31 @@ int check_com2(void) @@ -48,5 +49,5 @@ index 1f237fc4d63a..5ae0da8e3a57 100644 { u8 uarten; -- -2.39.2 +2.49.0 diff --git a/patches/0036-src-mainboard-pcengines-apu2-OemCustomize.c-make-boo.patch b/patches/0041-src-mainboard-pcengines-apu2-OemCustomize.c-make-boo.patch similarity index 84% rename from patches/0036-src-mainboard-pcengines-apu2-OemCustomize.c-make-boo.patch rename to patches/0041-src-mainboard-pcengines-apu2-OemCustomize.c-make-boo.patch index 9ab23be..c7fee77 100644 --- a/patches/0036-src-mainboard-pcengines-apu2-OemCustomize.c-make-boo.patch +++ b/patches/0041-src-mainboard-pcengines-apu2-OemCustomize.c-make-boo.patch @@ -1,19 +1,20 @@ -From cec4b5828988c907ab39202941ac863db07f0248 Mon Sep 17 00:00:00 2001 +From 5bd1845d701eaf5ce2773019cf535e4cad8d21e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 26 Feb 2019 12:03:34 +0100 -Subject: [PATCH 36/80] src/mainboard/pcengines/apu2/OemCustomize.c: make boost +Subject: [PATCH 41/88] src/mainboard/pcengines/apu2/OemCustomize.c: make boost runtime configurable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Michał Żygowski --- src/mainboard/pcengines/apu2/OemCustomize.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c -index 95af6ef92d56..0a2b68529f4b 100644 +index 95af6ef92d..0a2b68529f 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -2,6 +2,7 @@ @@ -38,5 +39,5 @@ index 95af6ef92d56..0a2b68529f4b 100644 void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) -- -2.39.2 +2.49.0 diff --git a/patches/0037-src-mainboard-pcengines-apu2-bootorder-add-boost-kno.patch b/patches/0042-src-mainboard-pcengines-apu2-bootorder-add-boost-kno.patch similarity index 55% rename from patches/0037-src-mainboard-pcengines-apu2-bootorder-add-boost-kno.patch rename to patches/0042-src-mainboard-pcengines-apu2-bootorder-add-boost-kno.patch index bd9cd78..f7d9605 100644 --- a/patches/0037-src-mainboard-pcengines-apu2-bootorder-add-boost-kno.patch +++ b/patches/0042-src-mainboard-pcengines-apu2-bootorder-add-boost-kno.patch @@ -1,21 +1,22 @@ -From 6786d7de5a6fa1e9550fae1b69f540b09a103312 Mon Sep 17 00:00:00 2001 +From 1e308d523f8168d6e01c7905d68486557ec5f0e9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 26 Feb 2019 12:04:12 +0100 -Subject: [PATCH 37/80] src/mainboard/pcengines/apu2/bootorder: add boost knobs +Subject: [PATCH 42/88] src/mainboard/pcengines/apu2/bootorder: add boost knobs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Michał Żygowski --- src/mainboard/pcengines/apu2/bootorder_def | 1 + + .../pcengines/apu2/variants/apu2/bootorder | Bin 4096 -> 4096 bytes .../pcengines/apu2/variants/apu3/bootorder | Bin 4096 -> 4096 bytes .../pcengines/apu2/variants/apu4/bootorder | Bin 4096 -> 4096 bytes - .../pcengines/apu2/variants/apu5/bootorder | Bin 4096 -> 4096 bytes 4 files changed, 1 insertion(+) diff --git a/src/mainboard/pcengines/apu2/bootorder_def b/src/mainboard/pcengines/apu2/bootorder_def -index a314740bde97..2ff65ad42601 100644 +index a314740bde..2ff65ad426 100644 --- a/src/mainboard/pcengines/apu2/bootorder_def +++ b/src/mainboard/pcengines/apu2/bootorder_def @@ -16,3 +16,4 @@ uartd1 @@ -23,33 +24,33 @@ index a314740bde97..2ff65ad42601 100644 mpcie2_clk0 com2_en0 +boosten1 -diff --git a/src/mainboard/pcengines/apu2/variants/apu3/bootorder b/src/mainboard/pcengines/apu2/variants/apu3/bootorder -index 2a0dfb2f39bf14f8fd195a7a9744a9ef1e1b51cc..42e870d321980e78b9bc2891846b12d717a3d10f 100644 +diff --git a/src/mainboard/pcengines/apu2/variants/apu2/bootorder b/src/mainboard/pcengines/apu2/variants/apu2/bootorder +index 1d19dba07707caefa7093fda865a2653f3219fa2..42e870d321980e78b9bc2891846b12d717a3d10f 100644 GIT binary patch -delta 29 -kcmZorXi(Tt!pOtRm6V@fT#}k+$ji04kx`3p@+$r?0EGz%+5i9m +delta 27 +icmZorXi(Tt#>kbFpI=;(nrFz%wYiZ|i*NEO{xAT3Pzb{S -delta 23 -ecmZorXi(Tt!pOwMySb53i*ND-M()Y0`9lFv;Rd|` +delta 20 +bcmZorXi(Tt#<;nWQHyW#1V--3tNB9#NMQ!1 -diff --git a/src/mainboard/pcengines/apu2/variants/apu4/bootorder b/src/mainboard/pcengines/apu2/variants/apu4/bootorder -index e94b77210661cd7789f90fa4897272994fba86d5..42e870d321980e78b9bc2891846b12d717a3d10f 100644 +diff --git a/src/mainboard/pcengines/apu2/variants/apu3/bootorder b/src/mainboard/pcengines/apu2/variants/apu3/bootorder +index 1d19dba07707caefa7093fda865a2653f3219fa2..42e870d321980e78b9bc2891846b12d717a3d10f 100644 GIT binary patch -delta 33 -ocmZorXi(T-&p6qg(UgamD=9y}xFj{tke6$7Bcm4IA(0HciwwEzGB +delta 27 +icmZorXi(Tt#>kbFpI=;(nrFz%wYiZ|i*NEO{xAT3Pzb{S -delta 28 -jcmZorXi(T-&&X1oo|rn>n$ePpi+6J)qZZ%f75otZcTETd +delta 20 +bcmZorXi(Tt#<;nWQHyW#1V--3tNB9#NMQ!1 -diff --git a/src/mainboard/pcengines/apu2/variants/apu5/bootorder b/src/mainboard/pcengines/apu2/variants/apu5/bootorder -index 29c163d69ebbf7f0ac2a8c7bf2c7edcb2293dbc0..b60c6d827dcbc8dc0f7632d44c3f8fa093a971a7 100644 +diff --git a/src/mainboard/pcengines/apu2/variants/apu4/bootorder b/src/mainboard/pcengines/apu2/variants/apu4/bootorder +index 1d19dba07707caefa7093fda865a2653f3219fa2..42e870d321980e78b9bc2891846b12d717a3d10f 100644 GIT binary patch delta 27 -icmZorXi(UY%gB|KpI=;(nrFz%wYiYdgm3a{{!jpYNC>n5 +icmZorXi(Tt#>kbFpI=;(nrFz%wYiZ|i*NEO{xAT3Pzb{S delta 20 -bcmZorXi(UY%ec9bQHyW#1V)j`tNB9#NCyU{ +bcmZorXi(Tt#<;nWQHyW#1V--3tNB9#NMQ!1 -- -2.39.2 +2.49.0 diff --git a/patches/0038-src-northbridge-amd-pi-00730F01-pci_devs.h-add-IOMMU.patch b/patches/0043-src-northbridge-amd-pi-00730F01-pci_devs.h-add-IOMMU.patch similarity index 61% rename from patches/0038-src-northbridge-amd-pi-00730F01-pci_devs.h-add-IOMMU.patch rename to patches/0043-src-northbridge-amd-pi-00730F01-pci_devs.h-add-IOMMU.patch index 8025481..beed784 100644 --- a/patches/0038-src-northbridge-amd-pi-00730F01-pci_devs.h-add-IOMMU.patch +++ b/patches/0043-src-northbridge-amd-pi-00730F01-pci_devs.h-add-IOMMU.patch @@ -1,21 +1,25 @@ -From d72f7034e30cb2ef015c1718942ee63cbb9683a6 Mon Sep 17 00:00:00 2001 +From 8c0720ca6032b81ce9b9158bc858151a17311a1a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 24 Apr 2019 13:47:59 +0200 -Subject: [PATCH 38/80] src/northbridge/amd/pi/00730F01/pci_devs.h: add IOMMU +Subject: [PATCH 43/88] src/northbridge/amd/pi/00730F01/pci_devs.h: add IOMMU and GNB devfn +Upstream-Status: Pending +Signed-off-by: Michał Żygowski --- - src/northbridge/amd/pi/00730F01/pci_devs.h | 12 ++++++++++++ - 1 file changed, 12 insertions(+) + src/northbridge/amd/pi/00730F01/pci_devs.h | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) diff --git a/src/northbridge/amd/pi/00730F01/pci_devs.h b/src/northbridge/amd/pi/00730F01/pci_devs.h -index e6ae1dfba4ef..762cf825451c 100644 +index 92f6ac5c57..8762e2e32c 100644 --- a/src/northbridge/amd/pi/00730F01/pci_devs.h +++ b/src/northbridge/amd/pi/00730F01/pci_devs.h -@@ -5,6 +5,18 @@ - - #define BUS0 0 +@@ -3,6 +3,20 @@ + #ifndef _AMD_00730F01_PCI_DEVS_H_ + #define _AMD_00730F01_PCI_DEVS_H_ ++#define BUS0 0 ++ +/* GNB Root Complex */ +#define GNB_DEV 0x0 +#define GNB_FUNC 0 @@ -32,5 +36,5 @@ index e6ae1dfba4ef..762cf825451c 100644 #define GFX_DEV 0x1 #define GFX_FUNC 0 -- -2.39.2 +2.49.0 diff --git a/patches/0039-src-mainboard-pcengines-apu2-acpi-superio.asl-descri.patch b/patches/0044-src-mainboard-pcengines-apu2-acpi-superio.asl-descri.patch similarity index 81% rename from patches/0039-src-mainboard-pcengines-apu2-acpi-superio.asl-descri.patch rename to patches/0044-src-mainboard-pcengines-apu2-acpi-superio.asl-descri.patch index 3d9290c..92840f0 100644 --- a/patches/0039-src-mainboard-pcengines-apu2-acpi-superio.asl-descri.patch +++ b/patches/0044-src-mainboard-pcengines-apu2-acpi-superio.asl-descri.patch @@ -1,16 +1,23 @@ -From 320b320e0d3911bc8ced1c93d8ebbaf781554152 Mon Sep 17 00:00:00 2001 +From a543157797a73ba893eb71e77efabd1dd0b8189f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 24 May 2019 15:24:04 +0200 -Subject: [PATCH 39/80] src/mainboard/pcengines/apu2/acpi/superio.asl: describe +Subject: [PATCH 44/88] src/mainboard/pcengines/apu2/acpi/superio.asl: describe serial ports MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Pending Signed-off-by: Michał Żygowski +--- + src/mainboard/pcengines/apu2/acpi/superio.asl | 47 +++++++++++++++++++ + src/mainboard/pcengines/apu2/dsdt.asl | 3 ++ + 2 files changed, 50 insertions(+) + create mode 100644 src/mainboard/pcengines/apu2/acpi/superio.asl + diff --git a/src/mainboard/pcengines/apu2/acpi/superio.asl b/src/mainboard/pcengines/apu2/acpi/superio.asl new file mode 100644 -index 000000000000..e91da42ec1d3 +index 0000000000..e91da42ec1 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/superio.asl @@ -0,0 +1,47 @@ @@ -62,7 +69,7 @@ index 000000000000..e91da42ec1d3 + } +} diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl -index 789be13280af..d2120aef0b7d 100644 +index 789be13280..d2120aef0b 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -54,5 +54,8 @@ DefinitionBlock ( @@ -74,3 +81,6 @@ index 789be13280af..d2120aef0b7d 100644 + #include "acpi/superio.asl" } /* End of ASL file */ +-- +2.49.0 + diff --git a/patches/0040-src-mainboard-pcengines-apu2-enable-SD-3.0-mode.patch b/patches/0045-src-mainboard-pcengines-apu2-enable-SD-3.0-mode.patch similarity index 77% rename from patches/0040-src-mainboard-pcengines-apu2-enable-SD-3.0-mode.patch rename to patches/0045-src-mainboard-pcengines-apu2-enable-SD-3.0-mode.patch index 9366a9d..262d764 100644 --- a/patches/0040-src-mainboard-pcengines-apu2-enable-SD-3.0-mode.patch +++ b/patches/0045-src-mainboard-pcengines-apu2-enable-SD-3.0-mode.patch @@ -1,14 +1,21 @@ -From d0ee1b38d03c4690eb9d3c347887e2f5cfe3d719 Mon Sep 17 00:00:00 2001 +From da5012f5a71afdfc0711fa1b5e7752895ac01d04 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 20 May 2019 15:29:32 +0200 -Subject: [PATCH 40/80] src/mainboard/pcengines/apu2: enable SD 3.0 mode +Subject: [PATCH 45/88] src/mainboard/pcengines/apu2: enable SD 3.0 mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Pending Signed-off-by: Michał Żygowski +--- + src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb | 1 + + src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb | 1 + + src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb | 1 + + 3 files changed, 3 insertions(+) + diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb -index 7725c659c6d9..0c5c16013d4a 100644 +index 7725c659c6..0c5c16013d 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -51,6 +51,7 @@ chip northbridge/amd/pi/00730F01 @@ -20,7 +27,7 @@ index 7725c659c6d9..0c5c16013d4a 100644 device ref ehci_2 on end # USB EHCI2 usb[8:7] - muxed with XHCI end diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb -index eb0777b489ce..9bfb37033b3c 100644 +index eb0777b489..9bfb37033b 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -49,6 +49,7 @@ chip northbridge/amd/pi/00730F01 @@ -32,7 +39,7 @@ index eb0777b489ce..9bfb37033b3c 100644 device ref ehci_2 on end # USB EHCI2 usb[8:7] - muxed with XHCI end diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb -index 57eebb65220f..b07168334959 100644 +index 57eebb6522..b071683349 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -49,6 +49,7 @@ chip northbridge/amd/pi/00730F01 @@ -43,3 +50,6 @@ index 57eebb65220f..b07168334959 100644 device ref sdhci on end device ref ehci_2 on end # USB EHCI2 usb[8:7] - muxed with XHCI end +-- +2.49.0 + diff --git a/patches/0041-src-mainboard-pcengines-apu2-bootorder-update-bootor.patch b/patches/0046-src-mainboard-pcengines-apu2-bootorder-update-bootor.patch similarity index 68% rename from patches/0041-src-mainboard-pcengines-apu2-bootorder-update-bootor.patch rename to patches/0046-src-mainboard-pcengines-apu2-bootorder-update-bootor.patch index 9b2dea7..c5e9e86 100644 --- a/patches/0041-src-mainboard-pcengines-apu2-bootorder-update-bootor.patch +++ b/patches/0046-src-mainboard-pcengines-apu2-bootorder-update-bootor.patch @@ -1,23 +1,24 @@ -From 6fd6923aa0f78f92346b300b3d5eda0bf1cc9c67 Mon Sep 17 00:00:00 2001 +From dd28c5b4f3663b4e6710d209625e9fe76a1efc2c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 30 May 2019 15:49:17 +0200 -Subject: [PATCH 41/80] src/mainboard/pcengines/apu2/bootorder: update +Subject: [PATCH 46/88] src/mainboard/pcengines/apu2/bootorder: update bootorder with SD 3.0 mode knob MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Michał Żygowski Signed-off-by: Piotr Król --- src/mainboard/pcengines/apu2/bootorder_def | 1 + + .../pcengines/apu2/variants/apu2/bootorder | Bin 4096 -> 4096 bytes .../pcengines/apu2/variants/apu3/bootorder | Bin 4096 -> 4096 bytes .../pcengines/apu2/variants/apu4/bootorder | Bin 4096 -> 4096 bytes - .../pcengines/apu2/variants/apu5/bootorder | Bin 4096 -> 4096 bytes 4 files changed, 1 insertion(+) diff --git a/src/mainboard/pcengines/apu2/bootorder_def b/src/mainboard/pcengines/apu2/bootorder_def -index 2ff65ad42601..bfbe2fa7fd74 100644 +index 2ff65ad426..ed19a86d86 100644 --- a/src/mainboard/pcengines/apu2/bootorder_def +++ b/src/mainboard/pcengines/apu2/bootorder_def @@ -17,3 +17,4 @@ ehcien0 @@ -25,8 +26,7 @@ index 2ff65ad42601..bfbe2fa7fd74 100644 com2_en0 boosten1 +sd3mode0 -\ No newline at end of file -diff --git a/src/mainboard/pcengines/apu2/variants/apu3/bootorder b/src/mainboard/pcengines/apu2/variants/apu3/bootorder +diff --git a/src/mainboard/pcengines/apu2/variants/apu2/bootorder b/src/mainboard/pcengines/apu2/variants/apu2/bootorder index 42e870d321980e78b9bc2891846b12d717a3d10f..9de0201c66ee7e08e8ede7317cebc6e3855b4192 100644 GIT binary patch delta 27 @@ -35,7 +35,7 @@ icmZorXi(VDz{pjcVw{_wl4`)qwYiZ|k#F*9{!jpVKL~gL delta 20 ccmZorXi(VDz_@uLqZHrd1&o4|SM!Gg07<0=#sB~S -diff --git a/src/mainboard/pcengines/apu2/variants/apu4/bootorder b/src/mainboard/pcengines/apu2/variants/apu4/bootorder +diff --git a/src/mainboard/pcengines/apu2/variants/apu3/bootorder b/src/mainboard/pcengines/apu2/variants/apu3/bootorder index 42e870d321980e78b9bc2891846b12d717a3d10f..9de0201c66ee7e08e8ede7317cebc6e3855b4192 100644 GIT binary patch delta 27 @@ -44,17 +44,15 @@ icmZorXi(VDz{pjcVw{_wl4`)qwYiZ|k#F*9{!jpVKL~gL delta 20 ccmZorXi(VDz_@uLqZHrd1&o4|SM!Gg07<0=#sB~S -diff --git a/src/mainboard/pcengines/apu2/variants/apu5/bootorder b/src/mainboard/pcengines/apu2/variants/apu5/bootorder -index b60c6d827dcbc8dc0f7632d44c3f8fa093a971a7..ba72627431ca32a0815ac195f1176a7f8d81a3e9 100644 +diff --git a/src/mainboard/pcengines/apu2/variants/apu4/bootorder b/src/mainboard/pcengines/apu2/variants/apu4/bootorder +index 42e870d321980e78b9bc2891846b12d717a3d10f..9de0201c66ee7e08e8ede7317cebc6e3855b4192 100644 GIT binary patch -delta 195 -zcmZorXi%6?&Q@BS?0_pO^lH`n( -U{B#2#;N{xf$f(CVc{P7107Hg2?EnA( +delta 27 +icmZorXi(VDz{pjcVw{_wl4`)qwYiZ|k#F*9{!jpVKL~gL -delta 31 -ncmZorXi%6?&ZgyHXrg02Ihpa-=0+wh-pv!3xELp|<_`q`ogxX) +delta 20 +ccmZorXi(VDz_@uLqZHrd1&o4|SM!Gg07<0=#sB~S -- -2.39.2 +2.49.0 diff --git a/patches/0042-src-mainboard-pcengines-apu2-bootorder-unify-bootord.patch b/patches/0047-src-mainboard-pcengines-apu2-bootorder-unify-bootord.patch similarity index 53% rename from patches/0042-src-mainboard-pcengines-apu2-bootorder-unify-bootord.patch rename to patches/0047-src-mainboard-pcengines-apu2-bootorder-unify-bootord.patch index d7dc1f5..c640b57 100644 --- a/patches/0042-src-mainboard-pcengines-apu2-bootorder-unify-bootord.patch +++ b/patches/0047-src-mainboard-pcengines-apu2-bootorder-unify-bootord.patch @@ -1,24 +1,24 @@ -From 5486d095c1deecd8a13aba1f05547a002638b485 Mon Sep 17 00:00:00 2001 +From ad4eb9ea411be3b057366bb7500dcac0f038b5bc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 30 May 2019 17:00:12 +0200 -Subject: [PATCH 42/80] src/mainboard/pcengines/apu2/bootorder: unify bootorder +Subject: [PATCH 47/88] src/mainboard/pcengines/apu2/bootorder: unify bootorder for USB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Custom payload feature] Signed-off-by: Michał Żygowski --- - src/mainboard/pcengines/apu2/bootorder_def | 10 +++++++++- + src/mainboard/pcengines/apu2/bootorder_def | 8 ++++++++ src/mainboard/pcengines/apu2/bootorder_map | 16 ++++++++++++---- .../pcengines/apu2/variants/apu2/bootorder | Bin 4096 -> 4096 bytes .../pcengines/apu2/variants/apu3/bootorder | Bin 4096 -> 4096 bytes .../pcengines/apu2/variants/apu4/bootorder | Bin 4096 -> 4096 bytes - .../pcengines/apu2/variants/apu5/bootorder | Bin 4096 -> 4054 bytes - 6 files changed, 21 insertions(+), 5 deletions(-) + 5 files changed, 20 insertions(+), 4 deletions(-) diff --git a/src/mainboard/pcengines/apu2/bootorder_def b/src/mainboard/pcengines/apu2/bootorder_def -index bfbe2fa7fd74..37c4b8436e12 100644 +index ed19a86d86..37c4b8436e 100644 --- a/src/mainboard/pcengines/apu2/bootorder_def +++ b/src/mainboard/pcengines/apu2/bootorder_def @@ -2,6 +2,14 @@ @@ -36,15 +36,8 @@ index bfbe2fa7fd74..37c4b8436e12 100644 /pci@i0cf8/*@14,7 /pci@i0cf8/*@11/drive@0/disk@0 /pci@i0cf8/*@11/drive@1/disk@0 -@@ -17,4 +25,4 @@ ehcien0 - mpcie2_clk0 - com2_en0 - boosten1 --sd3mode0 -\ No newline at end of file -+sd3mode0 diff --git a/src/mainboard/pcengines/apu2/bootorder_map b/src/mainboard/pcengines/apu2/bootorder_map -index e3e7551e6496..f5d47e4ee46c 100644 +index e3e7551e64..f5d47e4ee4 100644 --- a/src/mainboard/pcengines/apu2/bootorder_map +++ b/src/mainboard/pcengines/apu2/bootorder_map @@ -1,7 +1,15 @@ @@ -68,51 +61,35 @@ index e3e7551e6496..f5d47e4ee46c 100644 c mSATA d SATA diff --git a/src/mainboard/pcengines/apu2/variants/apu2/bootorder b/src/mainboard/pcengines/apu2/variants/apu2/bootorder -index 51b0fea1741238d986b4b47ac678fb344312d04b..f7d2212919704217c11daeefb5ac33814fe0567a 100644 +index 9de0201c66ee7e08e8ede7317cebc6e3855b4192..f7d2212919704217c11daeefb5ac33814fe0567a 100644 GIT binary patch -delta 157 -zcmZorXi%6?&Q@BS9Vq1G(W +delta 122 +zcmZorXi%6?&Q@BS?pBNG?z=824+ypvb+hXMdk!z4ri +delta 122 +zcmZorXi%6?&Q@BSz<%>~+>Y80QGlWoA2 -poS$n1(w3B;Ut9u`EKV`b%}+@+;M&~Cq{TaV0u#&R)%?MXTmXz4OUeKM - -delta 238 -zcmW-cKMsO06o=C~+2qB+n1~BHI2!rm0i0bO91XOM5QGv7>ZqOo({K_G!sa!+f{%9i -ze!us%9p2Y{%o~RSYo>$1GVDn=@P0bfN6v_?p(X0B7o9@`OVrr=*JHCIK)@V`i@aL4 -zWQDyY%b~v(sm`_@m>-!Wz{ml7E*jKji=b - -- -2.39.2 +2.49.0 diff --git a/patches/0043-src-mainboard-pcengines-apu2-bootorder-add-watchdog-.patch b/patches/0048-src-mainboard-pcengines-apu2-bootorder-add-watchdog-.patch similarity index 68% rename from patches/0043-src-mainboard-pcengines-apu2-bootorder-add-watchdog-.patch rename to patches/0048-src-mainboard-pcengines-apu2-bootorder-add-watchdog-.patch index 49ef095..097eefc 100644 --- a/patches/0043-src-mainboard-pcengines-apu2-bootorder-add-watchdog-.patch +++ b/patches/0048-src-mainboard-pcengines-apu2-bootorder-add-watchdog-.patch @@ -1,12 +1,13 @@ -From bda1b9494f45ca6f13eb8687b8e84e67ef0a01b0 Mon Sep 17 00:00:00 2001 +From dfbb06159ee2b75fc8a967f356b3c2a74861b339 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 4 Jun 2019 14:21:15 +0200 -Subject: [PATCH 43/80] src/mainboard/pcengines/apu2/bootorder: add watchdog +Subject: [PATCH 48/88] src/mainboard/pcengines/apu2/bootorder: add watchdog entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Michał Żygowski Signed-off-by: Piotr Król --- @@ -14,11 +15,10 @@ Signed-off-by: Piotr Król .../pcengines/apu2/variants/apu2/bootorder | Bin 4096 -> 4096 bytes .../pcengines/apu2/variants/apu3/bootorder | Bin 4096 -> 4096 bytes .../pcengines/apu2/variants/apu4/bootorder | Bin 4096 -> 4096 bytes - .../pcengines/apu2/variants/apu5/bootorder | Bin 4054 -> 4067 bytes - 5 files changed, 1 insertion(+) + 4 files changed, 1 insertion(+) diff --git a/src/mainboard/pcengines/apu2/bootorder_def b/src/mainboard/pcengines/apu2/bootorder_def -index 37c4b8436e12..210845d97c1d 100644 +index 37c4b8436e..210845d97c 100644 --- a/src/mainboard/pcengines/apu2/bootorder_def +++ b/src/mainboard/pcengines/apu2/bootorder_def @@ -26,3 +26,4 @@ mpcie2_clk0 @@ -36,13 +36,13 @@ delta 20 bcmZorXi(UY#I(7P$%=P!0~7z`)%>9VM$ZO_ diff --git a/src/mainboard/pcengines/apu2/variants/apu3/bootorder b/src/mainboard/pcengines/apu2/variants/apu3/bootorder -index 2c845236b8f865227639b809248715ecea09d7a9..be63cf9a37ee5fd5ad7cfca3ad0f107aef88b744 100644 +index f7d2212919704217c11daeefb5ac33814fe0567a..be63cf9a37ee5fd5ad7cfca3ad0f107aef88b744 100644 GIT binary patch -delta 33 -ncmZorXi(UYz$C!SRi0RqoRN~BZU6+lT$>A-tavA{;tvA=rhy5u +delta 28 +jcmZorXi(UY#Kc{mSdyHPlAms1V6Zu!$&PpOYW`3Fh}H>0 -delta 23 -ecmZorXi(UYz{JGGySb3big$7Y6aVDZ{Gk9(76zXH +delta 20 +bcmZorXi(UY#I(7P$%=P!0~7z`)%>9VM$ZO_ diff --git a/src/mainboard/pcengines/apu2/variants/apu4/bootorder b/src/mainboard/pcengines/apu2/variants/apu4/bootorder index f7d2212919704217c11daeefb5ac33814fe0567a..be63cf9a37ee5fd5ad7cfca3ad0f107aef88b744 100644 @@ -53,15 +53,6 @@ jcmZorXi(UY#Kc{mSdyHPlAms1V6Zu!$&PpOYW`3Fh}H>0 delta 20 bcmZorXi(UY#I(7P$%=P!0~7z`)%>9VM$ZO_ -diff --git a/src/mainboard/pcengines/apu2/variants/apu5/bootorder b/src/mainboard/pcengines/apu2/variants/apu5/bootorder -index 41643e044d19de2be7d1bd5d5a784829e2981732..e7e7fb6d0f9d4b55de772dab37a7d4fff8324e18 100644 -GIT binary patch -delta 34 -ocmca6|5$!Q2orC4Vo7pFN`ATl5O8fyWK!gvT)@OTxrsjn0MpM3^Z)<= - -delta 12 -TcmaDXe@%Wv2-D_7rY2qhBWeVr - -- -2.39.2 +2.49.0 diff --git a/patches/0044-src-vendorcode-amd-pi-Makefile.inc-strip-quotes-from.patch b/patches/0049-src-vendorcode-amd-pi-Makefile.inc-strip-quotes-from.patch similarity index 78% rename from patches/0044-src-vendorcode-amd-pi-Makefile.inc-strip-quotes-from.patch rename to patches/0049-src-vendorcode-amd-pi-Makefile.inc-strip-quotes-from.patch index 1a5e18e..ebfe9dd 100644 --- a/patches/0044-src-vendorcode-amd-pi-Makefile.inc-strip-quotes-from.patch +++ b/patches/0049-src-vendorcode-amd-pi-Makefile.inc-strip-quotes-from.patch @@ -1,15 +1,20 @@ -From 3a8f6e454676ddb0845f5aeb259f8ac382407184 Mon Sep 17 00:00:00 2001 +From 90dce9b09db78a37789351cc80ee48720635e827 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 30 May 2019 11:44:11 +0200 -Subject: [PATCH 44/80] src/vendorcode/amd/pi/Makefile.inc: strip quotes from +Subject: [PATCH 49/88] src/vendorcode/amd/pi/Makefile.inc: strip quotes from AGESA CBFS name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Pending Signed-off-by: Michał Żygowski +--- + src/vendorcode/amd/pi/Makefile.mk | 10 ++++++---- + 1 file changed, 6 insertions(+), 4 deletions(-) + diff --git a/src/vendorcode/amd/pi/Makefile.mk b/src/vendorcode/amd/pi/Makefile.mk -index 446e9d477940..f99d901b9a1b 100644 +index 446e9d4779..f99d901b9a 100644 --- a/src/vendorcode/amd/pi/Makefile.mk +++ b/src/vendorcode/amd/pi/Makefile.mk @@ -165,9 +165,11 @@ ramstage-libs += $(agesa_output_path)/libagesa.a @@ -28,3 +33,6 @@ index 446e9d477940..f99d901b9a1b 100644 +$(agesa_binary)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION) endif +-- +2.49.0 + diff --git a/patches/0045-src-mainboard-pcengines-apu2-Kconfig-add-necessary-o.patch b/patches/0050-src-mainboard-pcengines-apu2-Kconfig-add-necessary-o.patch similarity index 85% rename from patches/0045-src-mainboard-pcengines-apu2-Kconfig-add-necessary-o.patch rename to patches/0050-src-mainboard-pcengines-apu2-Kconfig-add-necessary-o.patch index 937168c..1bd919a 100644 --- a/patches/0045-src-mainboard-pcengines-apu2-Kconfig-add-necessary-o.patch +++ b/patches/0050-src-mainboard-pcengines-apu2-Kconfig-add-necessary-o.patch @@ -1,22 +1,23 @@ -From 842529cff31ad32b57acb9d64f40e79c604adf19 Mon Sep 17 00:00:00 2001 +From 3588eed727f4fc6bca527a69ec061ef3cbdceacf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 30 May 2019 12:02:48 +0200 -Subject: [PATCH 45/80] src/mainboard/pcengines/apu2/Kconfig: add necessary +Subject: [PATCH 50/88] src/mainboard/pcengines/apu2/Kconfig: add necessary options for vboot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Pending Signed-off-by: Michał Żygowski --- src/mainboard/pcengines/apu2/Kconfig | 32 ++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig -index d375f45e1417..415918b388e4 100644 +index 613cff69cb..823bbf11c4 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig -@@ -106,6 +106,38 @@ config FORCE_MPCIE2_CLK +@@ -103,6 +103,38 @@ config FORCE_MPCIE2_CLK help If no card is attached to mPCIe2 slot, say N. @@ -56,5 +57,5 @@ index d375f45e1417..415918b388e4 100644 bool default y -- -2.39.2 +2.49.0 diff --git a/patches/0046-mb-pcengines-apu2-Avoid-pragma-pack-on-the-rest-of-t.patch b/patches/0051-mb-pcengines-apu2-Avoid-pragma-pack-on-the-rest-of-t.patch similarity index 84% rename from patches/0046-mb-pcengines-apu2-Avoid-pragma-pack-on-the-rest-of-t.patch rename to patches/0051-mb-pcengines-apu2-Avoid-pragma-pack-on-the-rest-of-t.patch index dbca279..5a5144c 100644 --- a/patches/0046-mb-pcengines-apu2-Avoid-pragma-pack-on-the-rest-of-t.patch +++ b/patches/0051-mb-pcengines-apu2-Avoid-pragma-pack-on-the-rest-of-t.patch @@ -1,7 +1,7 @@ -From 693ce7cb9cf9c8a847a9f0f697c1807e4802bc5c Mon Sep 17 00:00:00 2001 +From 5a6286c7eb3b908814ced0ce635fd6b95ec10f73 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Tue, 21 Jun 2022 15:24:01 +0200 -Subject: [PATCH 46/80] mb/pcengines/apu2: Avoid pragma pack on the rest of the +Subject: [PATCH 51/88] mb/pcengines/apu2: Avoid pragma pack on the rest of the file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -13,6 +13,7 @@ included below AGESA.h. Adapted from https://review.coreboot.org/c/coreboot/+/64382 +Upstream-Status: Pending Signed-off-by: Michał Kopeć Change-Id: I2ee658c0d2db9a4dffe2dd8dbf5f4a3a905eb75d --- @@ -20,7 +21,7 @@ Change-Id: I2ee658c0d2db9a4dffe2dd8dbf5f4a3a905eb75d 1 file changed, 4 insertions(+) diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c -index 5962392dc3eb..1fb452903f56 100644 +index 9b8518cdb0..f9d419399f 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -1,6 +1,10 @@ @@ -35,5 +36,5 @@ index 5962392dc3eb..1fb452903f56 100644 #include #include -- -2.39.2 +2.49.0 diff --git a/patches/0052-mainboard-pcengines-send-commands-to-the-LPC-MCU.patch b/patches/0052-mainboard-pcengines-send-commands-to-the-LPC-MCU.patch deleted file mode 100644 index be2a8cc..0000000 --- a/patches/0052-mainboard-pcengines-send-commands-to-the-LPC-MCU.patch +++ /dev/null @@ -1,151 +0,0 @@ -From 6fffbcc6069587429dee5240a7095ee97a77e48c Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= -Date: Fri, 3 May 2024 13:10:32 +0200 -Subject: [PATCH 52/80] mainboard/pcengines: send commands to the LPC MCU -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Michał Żygowski ---- - src/mainboard/pcengines/apu2/bootblock.c | 14 +++-- - src/mainboard/pcengines/apu2/romstage.c | 70 +++++++++++++++++++++++- - 2 files changed, 75 insertions(+), 9 deletions(-) - -diff --git a/src/mainboard/pcengines/apu2/bootblock.c b/src/mainboard/pcengines/apu2/bootblock.c -index 3fa35af0ad88..464b3c6035a4 100644 ---- a/src/mainboard/pcengines/apu2/bootblock.c -+++ b/src/mainboard/pcengines/apu2/bootblock.c -@@ -6,6 +6,8 @@ - #include - #include - -+#include "bios_knobs.h" -+ - #define SIO_PORT 0x2e - #define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) - #define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) -@@ -15,10 +17,10 @@ void bootblock_mainboard_early_init(void) - hudson_lpc_port80(); - hudson_clk_output_48Mhz(); - -- /* COM2 on apu5 is reserved so only COM1 should be supported */ -- if ((CONFIG_UART_FOR_CONSOLE == 1) && -- !CONFIG(BOARD_PCENGINES_APU5)) -- nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); -- else if (CONFIG_UART_FOR_CONSOLE == 0) -- nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); -+ /* Enable UARTB for LPC MCU */ -+ if (CONFIG(BOARD_PCENGINES_APU5)) -+ nuvoton_enable_serial(SERIAL2_DEV, 0x2f8); -+ -+ if ((check_com2() || (CONFIG_UART_FOR_CONSOLE == 1))) -+ nuvoton_enable_serial(SERIAL2_DEV, 0x2f8); - } -diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c -index e075983798da..5b9f9f7aa6c3 100644 ---- a/src/mainboard/pcengines/apu2/romstage.c -+++ b/src/mainboard/pcengines/apu2/romstage.c -@@ -2,11 +2,13 @@ - - #include - #include -+#include - #include - #include - #include - #include - #include -+#include - #include - #include - #include -@@ -17,6 +19,7 @@ - - static void early_lpc_init(void); - static void print_sign_of_life(void); -+static void lpc_mcu_msg(void); - extern char coreboot_dmi_date[]; - extern char coreboot_version[]; - -@@ -122,9 +125,12 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) - } - - // do not print SOL if reset will take place in FchInit -- if (check_console() && -- !(pm_read32(0xc0) & FCH_PMIOxC0_S5ResetStatus_All_Status)) -- print_sign_of_life(); -+ if (!(pm_read32(0xc0) & FCH_PMIOxC0_S5ResetStatus_All_Status)) { -+ if (check_console()) -+ print_sign_of_life(); -+ -+ lpc_mcu_msg(); -+ } - - if ((check_mpcie2_clk() || CONFIG(FORCE_MPCIE2_CLK)) && - CONFIG(BOARD_PCENGINES_APU2)) { -@@ -139,3 +145,61 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) - } - } - -+static void lpc_mcu_msg(void) -+{ -+ unsigned int i, timeout; -+ const char *post_msg = "BIOSBOOT"; -+ unsigned char sync_byte = 0; -+ -+ if (!CONFIG(BOARD_PCENGINES_APU5)) -+ return; -+ -+ uart_init(1); -+ -+ for (i = 0; i < 4; i++) { -+ uart_tx_byte(1, 0xe1); -+ uart_tx_flush(1); -+ timeout = 10; -+ while (sync_byte != 0xe1) { -+ sync_byte = uart_rx_byte(1); -+ if (timeout == 0) { -+ uart_init(CONFIG_UART_FOR_CONSOLE); -+ udelay(10000); -+ printk(BIOS_ERR, "Failed to sync with LPC" -+ " MCU, number of retries %d\n", 3 - i); -+ udelay(10000); -+ uart_init(1); -+ udelay(10000); -+ break; -+ } -+ udelay(100); -+ timeout--; -+ } -+ if (sync_byte == 0xe1) -+ break; -+ } -+ -+ if (sync_byte != 0xe1) -+ return; -+ -+ uart_init(1); -+ timeout = 10; -+ -+ for (i = 0; i < strlen(post_msg); i++) -+ uart_tx_byte(1, *(post_msg + i)); -+ -+ uart_tx_byte(1, 0xe1); -+ uart_tx_flush(1); -+ -+ while (uart_rx_byte(1) != 0xe1) { -+ if (timeout == 0) { -+ uart_init(CONFIG_UART_FOR_CONSOLE); -+ printk(BIOS_ERR, "Did not receive response to BIOSBOOT\n"); -+ return; -+ } -+ udelay(100); -+ timeout--; -+ } -+ -+ uart_init(CONFIG_UART_FOR_CONSOLE); -+} --- -2.39.2 - diff --git a/patches/0047-src-mainboard-pcengines-apu2-BiosCallOuts.c-fix-SPD-.patch b/patches/0052-src-mainboard-pcengines-apu2-BiosCallOuts.c-fix-SPD-.patch similarity index 84% rename from patches/0047-src-mainboard-pcengines-apu2-BiosCallOuts.c-fix-SPD-.patch rename to patches/0052-src-mainboard-pcengines-apu2-BiosCallOuts.c-fix-SPD-.patch index 6d1fc19..1b08f4a 100644 --- a/patches/0047-src-mainboard-pcengines-apu2-BiosCallOuts.c-fix-SPD-.patch +++ b/patches/0052-src-mainboard-pcengines-apu2-BiosCallOuts.c-fix-SPD-.patch @@ -1,19 +1,20 @@ -From 5d7a3946ed4b20c158de8f45c213d63e4f09940c Mon Sep 17 00:00:00 2001 +From cca45187b7234eed99b43def2d18c846dec05439 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 3 Jun 2019 17:42:22 +0200 -Subject: [PATCH 47/80] src/mainboard/pcengines/apu2/BiosCallOuts.c: fix SPD +Subject: [PATCH 52/88] src/mainboard/pcengines/apu2/BiosCallOuts.c: fix SPD retrieval when FMAP is used MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Pending Signed-off-by: Michał Żygowski --- src/mainboard/pcengines/apu2/BiosCallOuts.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c -index 1fb452903f56..24f34e5ae919 100644 +index f9d419399f..cc03d1ed29 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -124,9 +124,8 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi @@ -29,5 +30,5 @@ index 1fb452903f56..24f34e5ae919 100644 return AGESA_SUCCESS; } -- -2.39.2 +2.49.0 diff --git a/patches/0048-mainboard-pcengines-add-FMAP-descriptor-files.patch b/patches/0053-mainboard-pcengines-add-FMAP-descriptor-files.patch similarity index 87% rename from patches/0048-mainboard-pcengines-add-FMAP-descriptor-files.patch rename to patches/0053-mainboard-pcengines-add-FMAP-descriptor-files.patch index a0fc822..b6425be 100644 --- a/patches/0048-mainboard-pcengines-add-FMAP-descriptor-files.patch +++ b/patches/0053-mainboard-pcengines-add-FMAP-descriptor-files.patch @@ -1,11 +1,12 @@ -From 53d3ae5b58bf8935f326fa4d7c44300a05a6b8ea Mon Sep 17 00:00:00 2001 +From 35ff317e29d92bd160fa5ae12eb919fa8df5d17f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Thu, 2 May 2024 23:25:08 +0200 -Subject: [PATCH 48/80] mainboard/pcengines: add FMAP descriptor files +Subject: [PATCH 53/88] mainboard/pcengines: add FMAP descriptor files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Pending Signed-off-by: Piotr Król --- src/mainboard/pcengines/apu2/vboot-rw-ab.fmd | 29 ++++++++++++++++++++ @@ -14,7 +15,7 @@ Signed-off-by: Piotr Król diff --git a/src/mainboard/pcengines/apu2/vboot-rw-ab.fmd b/src/mainboard/pcengines/apu2/vboot-rw-ab.fmd new file mode 100644 -index 000000000000..c17402e6160e +index 0000000000..c17402e616 --- /dev/null +++ b/src/mainboard/pcengines/apu2/vboot-rw-ab.fmd @@ -0,0 +1,29 @@ @@ -48,5 +49,5 @@ index 000000000000..c17402e6160e + } +} -- -2.39.2 +2.49.0 diff --git a/patches/0049-src-mainboard-pcengines-apu2-acpi-add-GPIOs-LEDS-and.patch b/patches/0054-src-mainboard-pcengines-apu2-acpi-add-GPIOs-LEDS-and.patch similarity index 93% rename from patches/0049-src-mainboard-pcengines-apu2-acpi-add-GPIOs-LEDS-and.patch rename to patches/0054-src-mainboard-pcengines-apu2-acpi-add-GPIOs-LEDS-and.patch index 3415859..9dcff10 100644 --- a/patches/0049-src-mainboard-pcengines-apu2-acpi-add-GPIOs-LEDS-and.patch +++ b/patches/0054-src-mainboard-pcengines-apu2-acpi-add-GPIOs-LEDS-and.patch @@ -1,26 +1,27 @@ -From 229aa3461d0bc54b82d7afa7af70868d183e3d16 Mon Sep 17 00:00:00 2001 +From c58b396d4a70a8d3e2ae09a261fc481f092ce64f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 23 Jul 2019 15:52:35 +0200 -Subject: [PATCH 49/80] src/mainboard/pcengines/apu2/acpi: add GPIOs, LEDS and +Subject: [PATCH 54/88] src/mainboard/pcengines/apu2/acpi: add GPIOs, LEDS and S1 button MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Breaks kernel driver] Signed-off-by: Michał Żygowski --- src/mainboard/pcengines/apu2/acpi/buttons.asl | 60 +++++++++++++++ src/mainboard/pcengines/apu2/acpi/gpio.asl | 34 +++++++++ - src/mainboard/pcengines/apu2/acpi/leds.asl | 75 +++++++++++++++++++ + src/mainboard/pcengines/apu2/acpi/leds.asl | 74 +++++++++++++++++++ src/mainboard/pcengines/apu2/dsdt.asl | 17 +++++ - 4 files changed, 186 insertions(+) + 4 files changed, 185 insertions(+) create mode 100644 src/mainboard/pcengines/apu2/acpi/buttons.asl create mode 100644 src/mainboard/pcengines/apu2/acpi/gpio.asl create mode 100644 src/mainboard/pcengines/apu2/acpi/leds.asl diff --git a/src/mainboard/pcengines/apu2/acpi/buttons.asl b/src/mainboard/pcengines/apu2/acpi/buttons.asl new file mode 100644 -index 000000000000..4448e9aeac4f +index 0000000000..4448e9aeac --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/buttons.asl @@ -0,0 +1,60 @@ @@ -86,7 +87,7 @@ index 000000000000..4448e9aeac4f +} diff --git a/src/mainboard/pcengines/apu2/acpi/gpio.asl b/src/mainboard/pcengines/apu2/acpi/gpio.asl new file mode 100644 -index 000000000000..8a05cdf539de +index 0000000000..8a05cdf539 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/gpio.asl @@ -0,0 +1,34 @@ @@ -126,10 +127,10 @@ index 000000000000..8a05cdf539de +} diff --git a/src/mainboard/pcengines/apu2/acpi/leds.asl b/src/mainboard/pcengines/apu2/acpi/leds.asl new file mode 100644 -index 000000000000..38fe2c3ff1d7 +index 0000000000..6fc7418f54 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/leds.asl -@@ -0,0 +1,75 @@ +@@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * @@ -174,7 +175,6 @@ index 000000000000..38fe2c3ff1d7 + Package () {"gpios", Package () {^^LEDS, 0, 0, 1 }}, + Package () {"default-state", "on"} + } -+ + }) + } + @@ -206,7 +206,7 @@ index 000000000000..38fe2c3ff1d7 + } +} diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl -index 6564ccc2709a..c0188ee3a671 100644 +index d2120aef0b..af979a9bcb 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -1,6 +1,17 @@ @@ -227,7 +227,7 @@ index 6564ccc2709a..c0188ee3a671 100644 #include DefinitionBlock ( "dsdt.aml", -@@ -50,6 +61,8 @@ DefinitionBlock ( +@@ -47,6 +58,8 @@ DefinitionBlock ( /* Describe PCI INT[A-H] for the Southbridge */ #include @@ -236,7 +236,7 @@ index 6564ccc2709a..c0188ee3a671 100644 } /* End \_SB scope */ /* Describe SMBUS for the Southbridge */ -@@ -60,5 +73,9 @@ DefinitionBlock ( +@@ -57,5 +70,9 @@ DefinitionBlock ( /* Super IO devices (COM ports) */ #include "acpi/superio.asl" @@ -247,5 +247,5 @@ index 6564ccc2709a..c0188ee3a671 100644 } /* End of ASL file */ -- -2.39.2 +2.49.0 diff --git a/patches/0050-mainboard-pcengines-add-IOMMU-status-to-bootorder_de.patch b/patches/0055-mainboard-pcengines-add-IOMMU-status-to-bootorder_de.patch similarity index 75% rename from patches/0050-mainboard-pcengines-add-IOMMU-status-to-bootorder_de.patch rename to patches/0055-mainboard-pcengines-add-IOMMU-status-to-bootorder_de.patch index 7c2cbdf..28eb4f3 100644 --- a/patches/0050-mainboard-pcengines-add-IOMMU-status-to-bootorder_de.patch +++ b/patches/0055-mainboard-pcengines-add-IOMMU-status-to-bootorder_de.patch @@ -1,22 +1,22 @@ -From 727c6219d46de80be221e2502ea7568f1f04ca8e Mon Sep 17 00:00:00 2001 +From 6c9e25e78dc961427fb070947ed969d64db99cc3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Witwicki?= Date: Thu, 19 Dec 2019 10:14:12 +0100 -Subject: [PATCH 50/80] mainboard/pcengines: add IOMMU status to bootorder_def +Subject: [PATCH 55/88] mainboard/pcengines: add IOMMU status to bootorder_def MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Michał Witwicki --- src/mainboard/pcengines/apu2/bootorder_def | 1 + .../pcengines/apu2/variants/apu2/bootorder | Bin 4096 -> 4096 bytes .../pcengines/apu2/variants/apu3/bootorder | Bin 4096 -> 4096 bytes .../pcengines/apu2/variants/apu4/bootorder | Bin 4096 -> 4096 bytes - .../pcengines/apu2/variants/apu5/bootorder | Bin 4067 -> 4074 bytes - 5 files changed, 1 insertion(+) + 4 files changed, 1 insertion(+) diff --git a/src/mainboard/pcengines/apu2/bootorder_def b/src/mainboard/pcengines/apu2/bootorder_def -index 210845d97c1d..26686bea9cee 100644 +index 210845d97c..26686bea9c 100644 --- a/src/mainboard/pcengines/apu2/bootorder_def +++ b/src/mainboard/pcengines/apu2/bootorder_def @@ -26,4 +26,5 @@ mpcie2_clk0 @@ -52,15 +52,6 @@ dcmZorXi(UY#KfAJpPO5{IiAUdck*ifPykm82Z#Uw delta 20 bcmZorXi(UY#I!k!$&q*R1SXEjtNB9#M-B#& -diff --git a/src/mainboard/pcengines/apu2/variants/apu5/bootorder b/src/mainboard/pcengines/apu2/variants/apu5/bootorder -index e7e7fb6d0f9d4b55de772dab37a7d4fff8324e18..5718bbceec04846298ea90b63671a2d354416bea 100644 -GIT binary patch -delta 18 -ZcmaDX|4M#C2oq~&er|5*<{+ktyZ}ep2IBw# - -delta 12 -TcmaDQ|5$!Q2-D_hrhZ-kBtitf - -- -2.39.2 +2.49.0 diff --git a/patches/0051-mainboard-apu2-fix-watchdog-issues.patch b/patches/0056-mainboard-apu2-fix-watchdog-issues.patch similarity index 59% rename from patches/0051-mainboard-apu2-fix-watchdog-issues.patch rename to patches/0056-mainboard-apu2-fix-watchdog-issues.patch index 1bb3252..c2efb9d 100644 --- a/patches/0051-mainboard-apu2-fix-watchdog-issues.patch +++ b/patches/0056-mainboard-apu2-fix-watchdog-issues.patch @@ -1,7 +1,10 @@ -From f8db781582384a04f4a45c58020df7ce22c51970 Mon Sep 17 00:00:00 2001 +From c5ea55e10da22548799b8a66cb043bed259ab14b Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Tue, 31 Dec 2019 20:30:21 +0100 -Subject: [PATCH 51/80] mainboard/apu2: fix watchdog issues +Subject: [PATCH 56/88] mainboard/apu2: fix watchdog issues +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit Platform hanged without setting RstToCpuPwrGdEn. @@ -9,14 +12,17 @@ Code for enabling watchdog is now in board_BeforeInitEarly, as hardware is not enabled before InitReset. It didn't work on first boot after power cycle. +Upstream-Status: Pending Signed-off-by: Krystian Hebel +Signed-off-by: Michał Żygowski --- - src/mainboard/pcengines/apu2/OemCustomize.c | 34 +++++++++++ - src/mainboard/pcengines/apu2/romstage.c | 68 +++++++++++++++++++++ - 2 files changed, 102 insertions(+) + src/mainboard/pcengines/apu2/OemCustomize.c | 34 +++++ + src/mainboard/pcengines/apu2/bootblock.c | 14 ++- + src/mainboard/pcengines/apu2/romstage.c | 132 ++++++++++++++++++++ + 3 files changed, 174 insertions(+), 6 deletions(-) diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c -index 0a2b68529f4b..2f837fd9d832 100644 +index 0a2b68529f..2f837fd9d8 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -3,6 +3,9 @@ @@ -67,20 +73,52 @@ index 0a2b68529f4b..2f837fd9d832 100644 } void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +diff --git a/src/mainboard/pcengines/apu2/bootblock.c b/src/mainboard/pcengines/apu2/bootblock.c +index 3fa35af0ad..464b3c6035 100644 +--- a/src/mainboard/pcengines/apu2/bootblock.c ++++ b/src/mainboard/pcengines/apu2/bootblock.c +@@ -6,6 +6,8 @@ + #include + #include + ++#include "bios_knobs.h" ++ + #define SIO_PORT 0x2e + #define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) + #define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) +@@ -15,10 +17,10 @@ void bootblock_mainboard_early_init(void) + hudson_lpc_port80(); + hudson_clk_output_48Mhz(); + +- /* COM2 on apu5 is reserved so only COM1 should be supported */ +- if ((CONFIG_UART_FOR_CONSOLE == 1) && +- !CONFIG(BOARD_PCENGINES_APU5)) +- nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); +- else if (CONFIG_UART_FOR_CONSOLE == 0) +- nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); ++ /* Enable UARTB for LPC MCU */ ++ if (CONFIG(BOARD_PCENGINES_APU5)) ++ nuvoton_enable_serial(SERIAL2_DEV, 0x2f8); ++ ++ if ((check_com2() || (CONFIG_UART_FOR_CONSOLE == 1))) ++ nuvoton_enable_serial(SERIAL2_DEV, 0x2f8); + } diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c -index 2509031f3e5f..e075983798da 100644 +index 2509031f3e..5b9f9f7aa6 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c -@@ -1,6 +1,7 @@ +@@ -1,17 +1,27 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include ++#include #include #include #include -@@ -8,10 +9,16 @@ + #include #include ++#include #include #include +#include @@ -91,12 +129,13 @@ index 2509031f3e5f..e075983798da 100644 static void early_lpc_init(void); +static void print_sign_of_life(void); ++static void lpc_mcu_msg(void); +extern char coreboot_dmi_date[]; +extern char coreboot_version[]; void board_BeforeAgesa(struct sysinfo *cb) { -@@ -71,3 +78,64 @@ static void early_lpc_init(void) +@@ -71,3 +81,125 @@ static void early_lpc_init(void) if (CONFIG(BOARD_PCENGINES_APU5)) gpio_configure_pads(gpio_apu5, ARRAY_SIZE(gpio_apu5)); } @@ -144,9 +183,12 @@ index 2509031f3e5f..e075983798da 100644 + } + + // do not print SOL if reset will take place in FchInit -+ if (check_console() && -+ !(pm_read32(0xc0) & FCH_PMIOxC0_S5ResetStatus_All_Status)) -+ print_sign_of_life(); ++ if (!(pm_read32(0xc0) & FCH_PMIOxC0_S5ResetStatus_All_Status)) { ++ if (check_console()) ++ print_sign_of_life(); ++ ++ lpc_mcu_msg(); ++ } + + if ((check_mpcie2_clk() || CONFIG(FORCE_MPCIE2_CLK)) && + CONFIG(BOARD_PCENGINES_APU2)) { @@ -161,6 +203,64 @@ index 2509031f3e5f..e075983798da 100644 + } +} + ++static void lpc_mcu_msg(void) ++{ ++ unsigned int i, timeout; ++ const char *post_msg = "BIOSBOOT"; ++ unsigned char sync_byte = 0; ++ ++ if (!CONFIG(BOARD_PCENGINES_APU5)) ++ return; ++ ++ uart_init(1); ++ ++ for (i = 0; i < 4; i++) { ++ uart_tx_byte(1, 0xe1); ++ uart_tx_flush(1); ++ timeout = 10; ++ while (sync_byte != 0xe1) { ++ sync_byte = uart_rx_byte(1); ++ if (timeout == 0) { ++ uart_init(CONFIG_UART_FOR_CONSOLE); ++ udelay(10000); ++ printk(BIOS_ERR, "Failed to sync with LPC" ++ " MCU, number of retries %d\n", 3 - i); ++ udelay(10000); ++ uart_init(1); ++ udelay(10000); ++ break; ++ } ++ udelay(100); ++ timeout--; ++ } ++ if (sync_byte == 0xe1) ++ break; ++ } ++ ++ if (sync_byte != 0xe1) ++ return; ++ ++ uart_init(1); ++ timeout = 10; ++ ++ for (i = 0; i < strlen(post_msg); i++) ++ uart_tx_byte(1, *(post_msg + i)); ++ ++ uart_tx_byte(1, 0xe1); ++ uart_tx_flush(1); ++ ++ while (uart_rx_byte(1) != 0xe1) { ++ if (timeout == 0) { ++ uart_init(CONFIG_UART_FOR_CONSOLE); ++ printk(BIOS_ERR, "Did not receive response to BIOSBOOT\n"); ++ return; ++ } ++ udelay(100); ++ timeout--; ++ } ++ ++ uart_init(CONFIG_UART_FOR_CONSOLE); ++} -- -2.39.2 +2.49.0 diff --git a/patches/0057-mainboard-pcengines-send-commands-to-the-LPC-MCU.patch b/patches/0057-mainboard-pcengines-send-commands-to-the-LPC-MCU.patch new file mode 100644 index 0000000..8717e39 --- /dev/null +++ b/patches/0057-mainboard-pcengines-send-commands-to-the-LPC-MCU.patch @@ -0,0 +1,30 @@ +From 55c4de41be78a7e1d5b11c6bc243229cd90f934f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= +Date: Fri, 3 May 2024 13:10:32 +0200 +Subject: [PATCH 57/88] mainboard/pcengines: send commands to the LPC MCU +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Upstream-Status: Inappropriate [Custom feature] +Signed-off-by: Michał Żygowski +--- + src/mainboard/pcengines/apu2/romstage.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c +index 5b9f9f7aa6..71b5170ce4 100644 +--- a/src/mainboard/pcengines/apu2/romstage.c ++++ b/src/mainboard/pcengines/apu2/romstage.c +@@ -128,7 +128,7 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) + if (!(pm_read32(0xc0) & FCH_PMIOxC0_S5ResetStatus_All_Status)) { + if (check_console()) + print_sign_of_life(); +- ++ + lpc_mcu_msg(); + } + +-- +2.49.0 + diff --git a/patches/0053-src-northbridge-amd-pi-00730F01-acpi-northbridge.asl.patch b/patches/0058-src-northbridge-amd-pi-00730F01-acpi-northbridge.asl.patch similarity index 82% rename from patches/0053-src-northbridge-amd-pi-00730F01-acpi-northbridge.asl.patch rename to patches/0058-src-northbridge-amd-pi-00730F01-acpi-northbridge.asl.patch index ce75429..b1293bb 100644 --- a/patches/0053-src-northbridge-amd-pi-00730F01-acpi-northbridge.asl.patch +++ b/patches/0058-src-northbridge-amd-pi-00730F01-acpi-northbridge.asl.patch @@ -1,19 +1,20 @@ -From a99addbce69c7be0155936be83302231a18a114d Mon Sep 17 00:00:00 2001 +From fa9982ef8494eb28ba25f3167240aadb22379a64 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 1 Apr 2020 16:49:30 +0200 -Subject: [PATCH 53/80] src/northbridge/amd/pi/00730F01/acpi/northbridge.asl: +Subject: [PATCH 58/88] src/northbridge/amd/pi/00730F01/acpi/northbridge.asl: add missing device lost after rebase MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Pending Signed-off-by: Michał Żygowski --- src/northbridge/amd/pi/00730F01/acpi/northbridge.asl | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl -index eb4d4c6b9dfa..f69d0206a96b 100644 +index d502af4137..c5f60b94ff 100644 --- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl @@ -31,6 +31,10 @@ Device(AMRT) { @@ -28,5 +29,5 @@ index eb4d4c6b9dfa..f69d0206a96b 100644 Device(PBR4) { Name(_ADR, 0x00020001) -- -2.39.2 +2.49.0 diff --git a/patches/0054-src-southbridge-amd-pi-hudson-sd.c-move-SD-3.0-check.patch b/patches/0059-src-southbridge-amd-pi-hudson-sd.c-move-SD-3.0-check.patch similarity index 80% rename from patches/0054-src-southbridge-amd-pi-hudson-sd.c-move-SD-3.0-check.patch rename to patches/0059-src-southbridge-amd-pi-hudson-sd.c-move-SD-3.0-check.patch index 8ef80d4..b5418ca 100644 --- a/patches/0054-src-southbridge-amd-pi-hudson-sd.c-move-SD-3.0-check.patch +++ b/patches/0059-src-southbridge-amd-pi-hudson-sd.c-move-SD-3.0-check.patch @@ -1,19 +1,20 @@ -From 2d848767395101f580100918d8fe0e51bb188e91 Mon Sep 17 00:00:00 2001 +From 000a2917c27d80c6d1ab77d5cb5761b1f80baf44 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 1 Apr 2020 17:36:43 +0200 -Subject: [PATCH 54/80] src/southbridge/amd/pi/hudson/sd.c: move SD 3.0 check +Subject: [PATCH 59/88] src/southbridge/amd/pi/hudson/sd.c: move SD 3.0 check to southbridge MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Michał Żygowski --- src/southbridge/amd/pi/hudson/sd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/southbridge/amd/pi/hudson/sd.c b/src/southbridge/amd/pi/hudson/sd.c -index 6dad3349916b..3896ff6c3b2d 100644 +index 6dad334991..3896ff6c3b 100644 --- a/src/southbridge/amd/pi/hudson/sd.c +++ b/src/southbridge/amd/pi/hudson/sd.c @@ -7,6 +7,7 @@ @@ -34,5 +35,5 @@ index 6dad3349916b..3896ff6c3b2d 100644 if (sd_mode == 3) { /* SD 3.0 mode */ -- -2.39.2 +2.49.0 diff --git a/patches/0055-mainboard-pcengines-add-pciepm-runtime-option.patch b/patches/0060-mainboard-pcengines-add-pciepm-runtime-option.patch similarity index 82% rename from patches/0055-mainboard-pcengines-add-pciepm-runtime-option.patch rename to patches/0060-mainboard-pcengines-add-pciepm-runtime-option.patch index 7702ff3..d2810a5 100644 --- a/patches/0055-mainboard-pcengines-add-pciepm-runtime-option.patch +++ b/patches/0060-mainboard-pcengines-add-pciepm-runtime-option.patch @@ -1,24 +1,23 @@ -From a733d46543d3dee026a4a16b3d7bbd5e5e3a266c Mon Sep 17 00:00:00 2001 +From 85ce51bf02103eeac267cd2fa3c503338e55ab88 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Mon, 6 May 2024 13:10:51 +0200 -Subject: [PATCH 55/80] mainboard/pcengines: add pciepm runtime option +Subject: [PATCH 60/88] mainboard/pcengines: add pciepm runtime option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Piotr Król --- src/mainboard/pcengines/apu2/OemCustomize.c | 77 +++++++++++++++++- src/mainboard/pcengines/apu2/bootorder_def | 1 + - .../pcengines/apu2/bootorder_def_apu5 | 1 + .../pcengines/apu2/variants/apu2/bootorder | Bin 4096 -> 4096 bytes .../pcengines/apu2/variants/apu3/bootorder | Bin 4096 -> 4096 bytes .../pcengines/apu2/variants/apu4/bootorder | Bin 4096 -> 4096 bytes - .../pcengines/apu2/variants/apu5/bootorder | Bin 4074 -> 4082 bytes - 7 files changed, 77 insertions(+), 2 deletions(-) + 5 files changed, 76 insertions(+), 2 deletions(-) diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c -index 2f837fd9d832..ad23370637af 100644 +index 2f837fd9d8..ad23370637 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -9,7 +9,7 @@ @@ -122,19 +121,9 @@ index 2f837fd9d832..ad23370637af 100644 InitEarly->PlatformConfig.CStateMode = CStateModeC6; InitEarly->PlatformConfig.CpbMode = CpbModeAuto; diff --git a/src/mainboard/pcengines/apu2/bootorder_def b/src/mainboard/pcengines/apu2/bootorder_def -index 26686bea9cee..d7f6d7feef74 100644 +index 26686bea9c..d7f6d7feef 100644 --- a/src/mainboard/pcengines/apu2/bootorder_def +++ b/src/mainboard/pcengines/apu2/bootorder_def -@@ -27,4 +27,5 @@ com2_en0 - boosten1 - sd3mode0 - iommu0 -+pciepm0 - watchdog0000 -diff --git a/src/mainboard/pcengines/apu2/bootorder_def_apu5 b/src/mainboard/pcengines/apu2/bootorder_def_apu5 -index 5f562f2468ab..a32975687413 100644 ---- a/src/mainboard/pcengines/apu2/bootorder_def_apu5 -+++ b/src/mainboard/pcengines/apu2/bootorder_def_apu5 @@ -27,4 +27,5 @@ com2_en0 boosten1 sd3mode0 @@ -168,15 +157,6 @@ ecmZorXi(UY#l%*SoS9mXyE&c7ns@SQ{!jp4ZU^T8 delta 20 bcmZorXi(UY#k9GY$%1$C1SZbOtNB9#N1XA# - -- -2.39.2 +2.49.0 diff --git a/patches/0061-src-commonlib-include-commonlib-tpm_log_serialized.h.patch b/patches/0061-src-commonlib-include-commonlib-tpm_log_serialized.h.patch deleted file mode 100644 index 0ca8f66..0000000 --- a/patches/0061-src-commonlib-include-commonlib-tpm_log_serialized.h.patch +++ /dev/null @@ -1,10 +0,0 @@ -From 55b282644d77bd0ec12dfebc9ff97f320583feb0 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= -Date: Sun, 28 Jun 2020 19:22:14 +0200 -Subject: [PATCH 61/80] src/commonlib/include/commonlib/tpm_log_serialized.h: - unify TPM log into one header file -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Michał Żygowski diff --git a/patches/0056-src-device-pciexp_device.c-enable-PCIe-PM-feature-on.patch b/patches/0061-src-device-pciexp_device.c-enable-PCIe-PM-feature-on.patch similarity index 86% rename from patches/0056-src-device-pciexp_device.c-enable-PCIe-PM-feature-on.patch rename to patches/0061-src-device-pciexp_device.c-enable-PCIe-PM-feature-on.patch index 5dd35a2..1c2040c 100644 --- a/patches/0056-src-device-pciexp_device.c-enable-PCIe-PM-feature-on.patch +++ b/patches/0061-src-device-pciexp_device.c-enable-PCIe-PM-feature-on.patch @@ -1,19 +1,20 @@ -From ca88680fabf68412deced84580f7f4651cc761f6 Mon Sep 17 00:00:00 2001 +From 7ae4b2ce20b928f330a84ac7edcf264c44f588c2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sun, 26 Apr 2020 13:40:02 +0200 -Subject: [PATCH 56/80] src/device/pciexp_device.c: enable PCIe PM feature on +Subject: [PATCH 61/88] src/device/pciexp_device.c: enable PCIe PM feature on demand MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Michał Żygowski --- src/device/pciexp_device.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c -index c9441fb22e86..8781c0ebad36 100644 +index db351efd49..885240f8b1 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -9,6 +9,8 @@ @@ -25,7 +26,7 @@ index c9441fb22e86..8781c0ebad36 100644 static unsigned int ext_cap_id(unsigned int cap) { return cap & 0xffff; -@@ -620,21 +622,23 @@ static void pciexp_tune_dev(struct device *dev) +@@ -698,21 +700,23 @@ static void pciexp_tune_dev(struct device *dev) if (!root_cap) return; @@ -62,5 +63,5 @@ index c9441fb22e86..8781c0ebad36 100644 /* Clear PCIe Lane Error Status */ if (CONFIG(PCIEXP_LANE_ERR_STAT_CLEAR)) -- -2.39.2 +2.49.0 diff --git a/patches/0057-acpi-add-DRTM-table.patch b/patches/0062-acpi-add-DRTM-table.patch similarity index 82% rename from patches/0057-acpi-add-DRTM-table.patch rename to patches/0062-acpi-add-DRTM-table.patch index 75ed10d..4eed682 100644 --- a/patches/0057-acpi-add-DRTM-table.patch +++ b/patches/0062-acpi-add-DRTM-table.patch @@ -1,17 +1,23 @@ -From 2ae6a63ee3ef096491203f4b4232f7fe72dca26f Mon Sep 17 00:00:00 2001 +From cf9f5f8a1c2ad370596dde4b55b68f5b831ad942 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sat, 27 Jun 2020 21:01:31 +0200 -Subject: [PATCH 57/80] acpi: add DRTM table +Subject: [PATCH 62/88] acpi: add DRTM table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Submitted [CB:51580] Signed-off-by: Michał Żygowski +--- + src/acpi/acpi.c | 4 +++- + src/include/acpi/acpi.h | 45 +++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 48 insertions(+), 1 deletion(-) + diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c -index 39eadc3a7f27..b04f5f759ad8 100644 +index 06aa038caa..ab0cc2315b 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c -@@ -1774,7 +1774,9 @@ int get_acpi_table_revision(enum acpi_tables table) +@@ -1783,7 +1783,9 @@ int get_acpi_table_revision(enum acpi_tables table) return 2; case DMAR: return 1; @@ -23,7 +29,7 @@ index 39eadc3a7f27..b04f5f759ad8 100644 case SPMI: /* IMPI 2.0 */ return 5; diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h -index d6c30c1b5f63..0857c71562ab 100644 +index a36e65c9d9..60581636b8 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -104,6 +104,7 @@ enum acpi_tables { @@ -34,7 +40,7 @@ index d6c30c1b5f63..0857c71562ab 100644 /* Additional proprietary tables used by coreboot */ CRAT, /* Component Resource Attribute Table */ IORT, /* Input Output Remapping Table */ -@@ -1034,6 +1035,50 @@ typedef struct acpi_fadt { +@@ -1041,6 +1042,50 @@ typedef struct acpi_fadt { #define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1) /* bits 2-16: reserved since ACPI 5.1 */ @@ -85,3 +91,6 @@ index d6c30c1b5f63..0857c71562ab 100644 /* FADT Preferred Power Management Profile */ enum acpi_preferred_pm_profiles { PM_UNSPECIFIED = 0, +-- +2.49.0 + diff --git a/patches/0058-src-commonlib-include-commonlib-cbmem_id.h-add-new-I.patch b/patches/0063-src-commonlib-include-commonlib-cbmem_id.h-add-new-I.patch similarity index 78% rename from patches/0058-src-commonlib-include-commonlib-cbmem_id.h-add-new-I.patch rename to patches/0063-src-commonlib-include-commonlib-cbmem_id.h-add-new-I.patch index b9cfec9..37428c7 100644 --- a/patches/0058-src-commonlib-include-commonlib-cbmem_id.h-add-new-I.patch +++ b/patches/0063-src-commonlib-include-commonlib-cbmem_id.h-add-new-I.patch @@ -1,15 +1,20 @@ -From 6a58ec0d7b9712c898f893ec820c2742bc6990e1 Mon Sep 17 00:00:00 2001 +From b00806c5bf01dce9c5b60511a295fd76fb830a81 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sat, 27 Jun 2020 21:01:55 +0200 -Subject: [PATCH 58/80] src/commonlib/include/commonlib/cbmem_id.h: add new ID +Subject: [PATCH 63/88] src/commonlib/include/commonlib/cbmem_id.h: add new ID for DRTM TPM log MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Submitted [CB:51582] Signed-off-by: Michał Żygowski +--- + src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h | 2 ++ + 1 file changed, 2 insertions(+) + diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h -index b88a0831b953..caa8a17dab6f 100644 +index b88a0831b9..caa8a17dab 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -20,6 +20,7 @@ @@ -28,3 +33,6 @@ index b88a0831b953..caa8a17dab6f 100644 { CBMEM_ID_CPU_CRASHLOG, "CPU CRASHLOG (deprecated)"}, \ { CBMEM_ID_EHCI_DEBUG, "USBDEBUG " }, \ { CBMEM_ID_ELOG, "ELOG " }, \ +-- +2.49.0 + diff --git a/patches/0059-src-northbridge-amd-pi-00730F01-northbridge.c-genera.patch b/patches/0064-src-northbridge-amd-pi-00730F01-northbridge.c-genera.patch similarity index 90% rename from patches/0059-src-northbridge-amd-pi-00730F01-northbridge.c-genera.patch rename to patches/0064-src-northbridge-amd-pi-00730F01-northbridge.c-genera.patch index 9e68fdd..4c7ecd5 100644 --- a/patches/0059-src-northbridge-amd-pi-00730F01-northbridge.c-genera.patch +++ b/patches/0064-src-northbridge-amd-pi-00730F01-northbridge.c-genera.patch @@ -1,22 +1,23 @@ -From 3714c397372f135d83e814216a7b8e6036d657a4 Mon Sep 17 00:00:00 2001 +From 9af1ceaa6ab5d9da388cc36c2d4e686fc448ea28 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sat, 27 Jun 2020 21:02:35 +0200 -Subject: [PATCH 59/80] src/northbridge/amd/pi/00730F01/northbridge.c: generate +Subject: [PATCH 64/88] src/northbridge/amd/pi/00730F01/northbridge.c: generate DRTM table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Submitted [CB:51581] Signed-off-by: Michał Żygowski --- src/northbridge/amd/pi/00730F01/northbridge.c | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c -index f3a9d8438578..afaa7b22f353 100644 +index 0f08cddf63..519c190812 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c -@@ -10,6 +10,8 @@ +@@ -11,6 +11,8 @@ #include #include #include @@ -24,8 +25,8 @@ index f3a9d8438578..afaa7b22f353 100644 +#include #include #include - #include -@@ -560,6 +562,83 @@ static void northbridge_fill_ssdt_generator(const struct device *device) + #include +@@ -421,6 +423,83 @@ static void northbridge_fill_ssdt_generator(const struct device *device) acpigen_pop_len(); } @@ -109,7 +110,7 @@ index f3a9d8438578..afaa7b22f353 100644 static unsigned long agesa_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) -@@ -569,6 +648,7 @@ static unsigned long agesa_write_acpi_tables(const struct device *device, +@@ -430,6 +509,7 @@ static unsigned long agesa_write_acpi_tables(const struct device *device, acpi_header_t *ssdt; acpi_header_t *alib; acpi_ivrs_t *ivrs; @@ -117,7 +118,7 @@ index f3a9d8438578..afaa7b22f353 100644 /* HEST */ current = ALIGN_UP(current, 8); -@@ -642,6 +722,15 @@ static unsigned long agesa_write_acpi_tables(const struct device *device, +@@ -503,6 +583,15 @@ static unsigned long agesa_write_acpi_tables(const struct device *device, acpi_add_table(rsdp, ssdt); printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); @@ -134,5 +135,5 @@ index f3a9d8438578..afaa7b22f353 100644 } -- -2.39.2 +2.49.0 diff --git a/patches/0060-coreboot_table-include-DRTM-TPM-log-in-coreboot-tabl.patch b/patches/0065-coreboot_table-include-DRTM-TPM-log-in-coreboot-tabl.patch similarity index 74% rename from patches/0060-coreboot_table-include-DRTM-TPM-log-in-coreboot-tabl.patch rename to patches/0065-coreboot_table-include-DRTM-TPM-log-in-coreboot-tabl.patch index f24bb75..82fc15a 100644 --- a/patches/0060-coreboot_table-include-DRTM-TPM-log-in-coreboot-tabl.patch +++ b/patches/0065-coreboot_table-include-DRTM-TPM-log-in-coreboot-tabl.patch @@ -1,11 +1,12 @@ -From f3ad13bee65873ea1199da544ac7ded9b160e58f Mon Sep 17 00:00:00 2001 +From 7b833a1de756e84ecae0beeff07947ef099b9d14 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sun, 28 Jun 2020 19:21:45 +0200 -Subject: [PATCH 60/80] coreboot_table: include DRTM TPM log in coreboot tables +Subject: [PATCH 65/88] coreboot_table: include DRTM TPM log in coreboot tables MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Submitted [CB:5155157981] Signed-off-by: Michał Żygowski --- src/commonlib/include/commonlib/coreboot_tables.h | 1 + @@ -13,22 +14,22 @@ Signed-off-by: Michał Żygowski 2 files changed, 2 insertions(+) diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h -index 86bf5438b7ca..04c6ea603d03 100644 +index a9e14c7bff..9699139a76 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h -@@ -87,6 +87,7 @@ enum { - LB_TAG_TYPE_C_INFO = 0x0042, - LB_TAG_ACPI_RSDP = 0x0043, +@@ -88,6 +88,7 @@ enum { + LB_TAG_ACPI_RSDP = 0x0043, LB_TAG_PCIE = 0x0044, -+ LB_TAG_DRTM_LOG = 0x0045, + LB_TAG_EFI_FW_INFO = 0x0045, ++ LB_TAG_DRTM_LOG = 0x0046, /* The following options are CMOS-related */ LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c -index 0707fd3eca5e..15dbe8794d96 100644 +index 913588feb6..bb5d6498cc 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c -@@ -268,6 +268,7 @@ static void add_cbmem_pointers(struct lb_header *header) +@@ -270,6 +270,7 @@ static void add_cbmem_pointers(struct lb_header *header) {CBMEM_ID_VPD, LB_TAG_VPD}, {CBMEM_ID_WIFI_CALIBRATION, LB_TAG_WIFI_CALIBRATION}, {CBMEM_ID_TPM_CB_LOG, LB_TAG_TPM_CB_LOG}, @@ -37,5 +38,5 @@ index 0707fd3eca5e..15dbe8794d96 100644 {CBMEM_ID_VBOOT_WORKBUF, LB_TAG_VBOOT_WORKBUF}, {CBMEM_ID_TYPE_C_INFO, LB_TAG_TYPE_C_INFO}, -- -2.39.2 +2.49.0 diff --git a/patches/0062-util-cbmem-cbmem.c-implement-DRTM-TPM-log-parser.patch b/patches/0066-util-cbmem-cbmem.c-implement-DRTM-TPM-log-parser.patch similarity index 92% rename from patches/0062-util-cbmem-cbmem.c-implement-DRTM-TPM-log-parser.patch rename to patches/0066-util-cbmem-cbmem.c-implement-DRTM-TPM-log-parser.patch index ed38b55..696efc6 100644 --- a/patches/0062-util-cbmem-cbmem.c-implement-DRTM-TPM-log-parser.patch +++ b/patches/0066-util-cbmem-cbmem.c-implement-DRTM-TPM-log-parser.patch @@ -1,11 +1,12 @@ -From 778bfca6a34f099e09236ecfe1da9f0e933a0855 Mon Sep 17 00:00:00 2001 +From 19e672236e41c98101f9316ab4c10e26632d9cf7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sun, 28 Jun 2020 19:22:30 +0200 -Subject: [PATCH 62/80] util/cbmem/cbmem.c: implement DRTM TPM log parser +Subject: [PATCH 66/88] util/cbmem/cbmem.c: implement DRTM TPM log parser MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Submitted [CB:51583] Signed-off-by: Michał Żygowski Signed-off-by: Krystian Hebel Signed-off-by: Michał Kopeć @@ -16,10 +17,10 @@ Signed-off-by: Marek Kasiewicz 2 files changed, 250 insertions(+), 10 deletions(-) diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile -index 9219a08f3c03..84df80ab2b03 100644 +index 0c88aebbbe..bd27b9c379 100644 --- a/util/cbmem/Makefile +++ b/util/cbmem/Makefile -@@ -8,7 +8,7 @@ CC ?= $(CROSS_COMPILE)gcc +@@ -9,7 +9,7 @@ CC ?= $(CROSS_COMPILE)gcc INSTALL ?= /usr/bin/env install PREFIX ?= /usr/local CFLAGS ?= -O2 @@ -29,10 +30,10 @@ index 9219a08f3c03..84df80ab2b03 100644 CPPFLAGS += -I . -I $(ROOT)/commonlib/include -I $(ROOT)/commonlib/bsd/include CPPFLAGS += -include $(ROOT)/commonlib/bsd/include/commonlib/bsd/compiler.h diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c -index c0b39ea6d004..22c0e0564e29 100644 +index 15b6770315..b8e3e317ff 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c -@@ -268,6 +268,7 @@ static int find_cbmem_entry(uint32_t id, uint64_t *addr, size_t *size) +@@ -249,6 +249,7 @@ static int find_cbmem_entry(uint32_t id, uint64_t *addr, size_t *size) static struct lb_cbmem_ref timestamps; static struct lb_cbmem_ref console; static struct lb_cbmem_ref tpm_cb_log; @@ -40,7 +41,7 @@ index c0b39ea6d004..22c0e0564e29 100644 static struct lb_memory_range cbmem; /* This is a work-around for a nasty problem introduced by initially having -@@ -342,10 +343,12 @@ static int parse_cbtable_entries(const struct mapping *table_mapping) +@@ -323,10 +324,12 @@ static int parse_cbtable_entries(const struct mapping *table_mapping) parse_cbmem_ref((struct lb_cbmem_ref *)lbr_p); continue; } @@ -56,8 +57,8 @@ index c0b39ea6d004..22c0e0564e29 100644 case LB_TAG_FORWARD: { int ret; /* -@@ -884,6 +887,213 @@ static void dump_tpm_cb_log(void) - unmap_memory(&log_mapping); +@@ -1095,6 +1098,213 @@ static void dump_tpm_log(void) + dump_tpm_cb_log(); } +static void print_hex(uint8_t *hex, size_t len) @@ -270,7 +271,7 @@ index c0b39ea6d004..22c0e0564e29 100644 struct cbmem_console { u32 size; u32 cursor; -@@ -1325,8 +1535,10 @@ static void print_version(void) +@@ -1536,8 +1746,10 @@ static void print_version(void) static void print_usage(const char *name, int exit_code) { @@ -282,7 +283,7 @@ index c0b39ea6d004..22c0e0564e29 100644 " -c | --console: print cbmem console\n" " -1 | --oneboot: print cbmem console for last boot only\n" " -2 | --2ndtolast: print cbmem console for the boot that came before the last one only\n" -@@ -1340,6 +1552,7 @@ static void print_usage(const char *name, int exit_code) +@@ -1551,6 +1763,7 @@ static void print_usage(const char *name, int exit_code) " -S | --stacked-timestamps: print stacked timestamps (e.g. for flame graph tools)\n" " -a | --add-timestamp ID: append timestamp with ID\n" " -L | --tcpa-log print TPM log\n" @@ -290,7 +291,7 @@ index c0b39ea6d004..22c0e0564e29 100644 " -V | --verbose: verbose (debugging) output\n" " -v | --version: print the version\n" " -h | --help: print this help\n" -@@ -1464,6 +1677,9 @@ static char *dt_find_compat(const char *parent, const char *compat, +@@ -1675,6 +1888,9 @@ static char *dt_find_compat(const char *parent, const char *compat, int main(int argc, char** argv) { @@ -300,7 +301,7 @@ index c0b39ea6d004..22c0e0564e29 100644 int print_defaults = 1; int print_console = 0; int print_coverage = 0; -@@ -1471,6 +1687,7 @@ int main(int argc, char** argv) +@@ -1682,6 +1898,7 @@ int main(int argc, char** argv) int print_hexdump = 0; int print_rawdump = 0; int print_tcpa_log = 0; @@ -308,7 +309,7 @@ index c0b39ea6d004..22c0e0564e29 100644 enum timestamps_print_type timestamp_type = TIMESTAMPS_PRINT_NONE; enum console_print_type console_type = CONSOLE_PRINT_FULL; unsigned int rawdump_id = 0; -@@ -1480,6 +1697,8 @@ int main(int argc, char** argv) +@@ -1691,6 +1908,8 @@ int main(int argc, char** argv) int opt, option_index = 0; static struct option long_options[] = { @@ -317,7 +318,7 @@ index c0b39ea6d004..22c0e0564e29 100644 {"console", 0, 0, 'c'}, {"oneboot", 0, 0, '1'}, {"2ndtolast", 0, 0, '2'}, -@@ -1487,6 +1706,7 @@ int main(int argc, char** argv) +@@ -1698,6 +1917,7 @@ int main(int argc, char** argv) {"coverage", 0, 0, 'C'}, {"list", 0, 0, 'l'}, {"tcpa-log", 0, 0, 'L'}, @@ -325,7 +326,7 @@ index c0b39ea6d004..22c0e0564e29 100644 {"timestamps", 0, 0, 't'}, {"parseable-timestamps", 0, 0, 'T'}, {"stacked-timestamps", 0, 0, 'S'}, -@@ -1498,9 +1718,19 @@ int main(int argc, char** argv) +@@ -1709,9 +1929,19 @@ int main(int argc, char** argv) {"help", 0, 0, 'h'}, {0, 0, 0, 0} }; @@ -346,7 +347,7 @@ index c0b39ea6d004..22c0e0564e29 100644 case 'c': print_console = 1; print_defaults = 0; -@@ -1530,6 +1760,10 @@ int main(int argc, char** argv) +@@ -1741,6 +1971,10 @@ int main(int argc, char** argv) print_tcpa_log = 1; print_defaults = 0; break; @@ -357,7 +358,7 @@ index c0b39ea6d004..22c0e0564e29 100644 case 'x': print_hexdump = 1; print_defaults = 0; -@@ -1640,12 +1874,15 @@ int main(int argc, char** argv) +@@ -1851,12 +2085,15 @@ int main(int argc, char** argv) parse_cbtable(baseaddr, cb_table_size); #else @@ -377,9 +378,9 @@ index c0b39ea6d004..22c0e0564e29 100644 } #endif -@@ -1679,6 +1916,9 @@ int main(int argc, char** argv) +@@ -1890,6 +2127,9 @@ int main(int argc, char** argv) if (print_tcpa_log) - dump_tpm_cb_log(); + dump_tpm_log(); + if (print_drtm_log) + dump_drtm_log(); @@ -388,5 +389,5 @@ index c0b39ea6d004..22c0e0564e29 100644 close(mem_fd); -- -2.39.2 +2.49.0 diff --git a/patches/0067-mainboard-pcengines-Update-GPIO-configuration-and-re.patch b/patches/0067-mainboard-pcengines-Update-GPIO-configuration-and-re.patch deleted file mode 100644 index 65fece5..0000000 --- a/patches/0067-mainboard-pcengines-Update-GPIO-configuration-and-re.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 424fe2d12e46eecbcb7893d88945d282ac91891d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= -Date: Sun, 5 May 2024 00:35:25 +0200 -Subject: [PATCH 67/80] mainboard/pcengines: Update GPIO configuration and - remove unused macros -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This commit updates the GPIO configuration for apu3, apu4, and apu7 -boards. It also removes unused macros for SIO_PORT and SERIAL_DEV. - -Signed-off-by: Piotr Król ---- - src/mainboard/pcengines/apu2/romstage.c | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - -diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c -index 5b9f9f7aa6c3..7329896fb14a 100644 ---- a/src/mainboard/pcengines/apu2/romstage.c -+++ b/src/mainboard/pcengines/apu2/romstage.c -@@ -27,6 +27,8 @@ void board_BeforeAgesa(struct sysinfo *cb) - { - u32 val; - -+ pm_write8(FCH_PMIOA_REGC5, 0); -+ - early_lpc_init(); - - /* Disable SVI2 controller to wait for command completion */ -@@ -57,7 +59,7 @@ const struct soc_amd_gpio gpio_apu2[] = { - PAD_GPI(GPIO_32, PULL_NONE), - }; - --const struct soc_amd_gpio gpio_apu34[] = { -+const struct soc_amd_gpio gpio_apu347[] = { - PAD_GPI(GPIO_32, PULL_NONE), - PAD_GPO(GPIO_33, LOW), - }; -@@ -75,8 +77,8 @@ static void early_lpc_init(void) - if (CONFIG(BOARD_PCENGINES_APU2)) - gpio_configure_pads(gpio_apu2, ARRAY_SIZE(gpio_apu2)); - -- if (CONFIG(BOARD_PCENGINES_APU3) || CONFIG(BOARD_PCENGINES_APU4)) -- gpio_configure_pads(gpio_apu34, ARRAY_SIZE(gpio_apu34)); -+ if (CONFIG(BOARD_PCENGINES_APU3) || CONFIG(BOARD_PCENGINES_APU4) || CONFIG(BOARD_PCENGINES_APU7)) -+ gpio_configure_pads(gpio_apu347, ARRAY_SIZE(gpio_apu347)); - - if (CONFIG(BOARD_PCENGINES_APU5)) - gpio_configure_pads(gpio_apu5, ARRAY_SIZE(gpio_apu5)); --- -2.39.2 - diff --git a/patches/0063-mainboard-pcengines-apu2-Add-reversed-PCI-address-or.patch b/patches/0067-mainboard-pcengines-apu2-Add-reversed-PCI-address-or.patch similarity index 86% rename from patches/0063-mainboard-pcengines-apu2-Add-reversed-PCI-address-or.patch rename to patches/0067-mainboard-pcengines-apu2-Add-reversed-PCI-address-or.patch index 044f0dd..f7afccb 100644 --- a/patches/0063-mainboard-pcengines-apu2-Add-reversed-PCI-address-or.patch +++ b/patches/0067-mainboard-pcengines-apu2-Add-reversed-PCI-address-or.patch @@ -1,22 +1,21 @@ -From c287fbb5b5f57b5b2fb339754a4c142c2fddc8e7 Mon Sep 17 00:00:00 2001 +From 99137202cf1447f4204bb61e9f663c67f9680d5f Mon Sep 17 00:00:00 2001 From: Marek Kasiewicz Date: Thu, 16 Jul 2020 14:52:52 +0200 -Subject: [PATCH 63/80] mainboard/pcengines/apu2/: Add reversed PCI address +Subject: [PATCH 67/88] mainboard/pcengines/apu2/: Add reversed PCI address order option +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Marek Kasiewicz --- src/mainboard/pcengines/apu2/OemCustomize.c | 155 +++++++++++++++++- src/mainboard/pcengines/apu2/bootorder_def | 1 + - .../pcengines/apu2/bootorder_def_apu5 | 1 + .../pcengines/apu2/variants/apu2/bootorder | Bin 4096 -> 4096 bytes .../pcengines/apu2/variants/apu3/bootorder | Bin 4096 -> 4096 bytes .../pcengines/apu2/variants/apu4/bootorder | Bin 4096 -> 4096 bytes - .../pcengines/apu2/variants/apu5/bootorder | Bin 4082 -> 4095 bytes - 7 files changed, 153 insertions(+), 4 deletions(-) + 5 files changed, 152 insertions(+), 4 deletions(-) diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c -index ad23370637af..d868850ff90e 100644 +index ad23370637..d868850ff9 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -133,6 +133,132 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { @@ -191,19 +190,9 @@ index ad23370637af..d868850ff90e 100644 if (check_boost()) { InitEarly->PlatformConfig.CStateMode = CStateModeC6; diff --git a/src/mainboard/pcengines/apu2/bootorder_def b/src/mainboard/pcengines/apu2/bootorder_def -index d7f6d7feef74..88da074dd189 100644 +index d7f6d7feef..88da074dd1 100644 --- a/src/mainboard/pcengines/apu2/bootorder_def +++ b/src/mainboard/pcengines/apu2/bootorder_def -@@ -28,4 +28,5 @@ boosten1 - sd3mode0 - iommu0 - pciepm0 -+pciereverse0 - watchdog0000 -diff --git a/src/mainboard/pcengines/apu2/bootorder_def_apu5 b/src/mainboard/pcengines/apu2/bootorder_def_apu5 -index a32975687413..7885710c5476 100644 ---- a/src/mainboard/pcengines/apu2/bootorder_def_apu5 -+++ b/src/mainboard/pcengines/apu2/bootorder_def_apu5 @@ -28,4 +28,5 @@ boosten1 sd3mode0 iommu0 @@ -237,15 +226,6 @@ jcmZorXi(Tt%*0)goS9mbT9#T=oVvMyNtbu>YW`3Fl6MLZ delta 20 bcmZorXi(Tt%(S_YNsD*#0w%u6tNB9#NXZ7c -diff --git a/src/mainboard/pcengines/apu2/variants/apu5/bootorder b/src/mainboard/pcengines/apu2/variants/apu5/bootorder -index 1588e7c12710c5c0ba9df2af00c16783621f0807..dede5fc25b031f767dbd94e6f488bcdcc25e65e1 100644 -GIT binary patch -delta 24 -fcmew)|6hJXG81<}a%O5#YFTPgaq8worir`&fXxY^ - -delta 12 -Tcmew_|4DvBGSlV)rhZ-kCXodO - -- -2.39.2 +2.49.0 diff --git a/patches/0064-src-mainboard-pcengines-apu2-fix-TPM-visibility-in-O.patch b/patches/0068-src-mainboard-pcengines-apu2-fix-TPM-visibility-in-O.patch similarity index 76% rename from patches/0064-src-mainboard-pcengines-apu2-fix-TPM-visibility-in-O.patch rename to patches/0068-src-mainboard-pcengines-apu2-fix-TPM-visibility-in-O.patch index d43e447..496f22f 100644 --- a/patches/0064-src-mainboard-pcengines-apu2-fix-TPM-visibility-in-O.patch +++ b/patches/0068-src-mainboard-pcengines-apu2-fix-TPM-visibility-in-O.patch @@ -1,15 +1,21 @@ -From 7c780dc6bf462baaec8f7122d7ed61bda20ab6aa Mon Sep 17 00:00:00 2001 +From 0521803056983afb9d5c7971a48f768b2edaeaf7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 20 Aug 2020 10:37:14 +0200 -Subject: [PATCH 64/80] src/mainboard/pcengines/apu2: fix TPM visibility in OS +Subject: [PATCH 68/88] src/mainboard/pcengines/apu2: fix TPM visibility in OS for apu3d and apu4d MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Pending Signed-off-by: Michał Żygowski +--- + src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb | 3 +++ + src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb | 3 +++ + 2 files changed, 6 insertions(+) + diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb -index 9bfb37033b3c..354b272a43e1 100644 +index 9bfb37033b..354b272a43 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -48,6 +48,9 @@ chip northbridge/amd/pi/00730F01 @@ -23,7 +29,7 @@ index 9bfb37033b3c..354b272a43e1 100644 register "sd_mode" = "3" device ref sdhci on end diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb -index b07168334959..911df5af962e 100644 +index b071683349..911df5af96 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -48,6 +48,9 @@ chip northbridge/amd/pi/00730F01 @@ -36,3 +42,6 @@ index b07168334959..911df5af962e 100644 end register "sd_mode" = "3" device ref sdhci on end +-- +2.49.0 + diff --git a/patches/0065-src-mainboard-pcengines-apu2-add-apu6-variant.patch b/patches/0069-src-mainboard-pcengines-apu2-add-apu6-variant.patch similarity index 76% rename from patches/0065-src-mainboard-pcengines-apu2-add-apu6-variant.patch rename to patches/0069-src-mainboard-pcengines-apu2-add-apu6-variant.patch index ca50014..cbb0d32 100644 --- a/patches/0065-src-mainboard-pcengines-apu2-add-apu6-variant.patch +++ b/patches/0069-src-mainboard-pcengines-apu2-add-apu6-variant.patch @@ -1,18 +1,31 @@ -From 1328b295b79c5023d129ca773cba3b5a19c60789 Mon Sep 17 00:00:00 2001 +From 3d5d96843fe085e128b6918544f6ba79eee4b25c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 25 Sep 2020 13:40:12 +0200 -Subject: [PATCH 65/80] src/mainboard/pcengines/apu2: add apu6 variant +Subject: [PATCH 69/88] src/mainboard/pcengines/apu2: add apu6 variant MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Pending Signed-off-by: Michał Żygowski -diff --git a/configs/config.pcengines_apu6 b/configs/config.pcengines_apu6 +--- + configs/config.pcengines_seabios_apu6 | 34 ++++++++++ + src/mainboard/pcengines/apu2/Kconfig | 8 ++- + src/mainboard/pcengines/apu2/Kconfig.name | 3 + + src/mainboard/pcengines/apu2/dsdt.asl | 2 + + .../pcengines/apu2/variants/apu6/bootorder | Bin 0 -> 4096 bytes + .../apu2/variants/apu6/devicetree.cb | 60 ++++++++++++++++++ + 6 files changed, 104 insertions(+), 3 deletions(-) + create mode 100644 configs/config.pcengines_seabios_apu6 + create mode 100644 src/mainboard/pcengines/apu2/variants/apu6/bootorder + create mode 100644 src/mainboard/pcengines/apu2/variants/apu6/devicetree.cb + +diff --git a/configs/config.pcengines_seabios_apu6 b/configs/config.pcengines_seabios_apu6 new file mode 100644 -index 000000000000..7f9bf753accd +index 0000000000..639811e0c8 --- /dev/null -+++ b/configs/config.pcengines_apu6 -@@ -0,0 +1,33 @@ ++++ b/configs/config.pcengines_seabios_apu6 +@@ -0,0 +1,34 @@ +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_IPXE_SERIAL_CONSOLE is not set @@ -25,8 +38,9 @@ index 000000000000..7f9bf753accd +CONFIG_HUDSON_SATA_MODE=2 +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_IPXE_ADD_SCRIPT=y ++CONFIG_IPXE_CUSTOM_BUILD_ID="12345678" +CONFIG_IPXE_SCRIPT="payloads/external/iPXE/menu.ipxe" -+CONFIG_LOCALVERSION="v24.05.00.01" ++CONFIG_LOCALVERSION="v24.08.00.01" +CONFIG_MEMTEST86PLUS_V5=y +CONFIG_MEMTEST_SECONDARY_PAYLOAD=y +CONFIG_NO_GFX_INIT=y @@ -37,17 +51,17 @@ index 000000000000..7f9bf753accd +CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" +CONFIG_SEABIOS_DEBUG_LEVEL=0 +CONFIG_SEABIOS_REVISION=y -+CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" ++CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" +CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 +CONFIG_SORTBOOTORDER_REVISION=y -+CONFIG_SORTBOOTORDER_REVISION_ID="v24.05.00.01" ++CONFIG_SORTBOOTORDER_REVISION_ID="v24.08.00.01" +CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_TPM2=y +CONFIG_VENDOR_PCENGINES=y diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig -index 823bbf11c410..fbf29a452d8f 100644 +index 823bbf11c4..ee8e8c9f47 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -1,7 +1,7 @@ @@ -80,7 +94,7 @@ index 823bbf11c410..fbf29a452d8f 100644 bool "GPIO" depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \ - BOARD_PCENGINES_APU4 -+ BOARD_PCENGINES_APU4 || BOARD_PCENGINES_APU6 ++ BOARD_PCENGINES_APU4 || BOARD_PCENGINES_APU6 config APU2_PINMUX_UART_C bool "UART 0x3e8" @@ -89,12 +103,12 @@ index 823bbf11c410..fbf29a452d8f 100644 bool "GPIO" depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \ - BOARD_PCENGINES_APU4 -+ BOARD_PCENGINES_APU4 || BOARD_PCENGINES_APU6 ++ BOARD_PCENGINES_APU4 || BOARD_PCENGINES_APU6 config APU2_PINMUX_UART_D bool "UART 0x2e8" diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name -index 170080396ce5..8ee55dbe6057 100644 +index 170080396c..8ee55dbe60 100644 --- a/src/mainboard/pcengines/apu2/Kconfig.name +++ b/src/mainboard/pcengines/apu2/Kconfig.name @@ -11,3 +11,6 @@ config BOARD_PCENGINES_APU4 @@ -105,7 +119,7 @@ index 170080396ce5..8ee55dbe6057 100644 +config BOARD_PCENGINES_APU6 + bool "APU6" diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl -index af979a9bcb21..0a91feec580e 100644 +index af979a9bcb..0a91feec58 100644 --- a/src/mainboard/pcengines/apu2/dsdt.asl +++ b/src/mainboard/pcengines/apu2/dsdt.asl @@ -10,6 +10,8 @@ @@ -122,19 +136,19 @@ new file mode 100644 index 0000000000000000000000000000000000000000..7e7e1b1a227ebaedc09bb74c05f3bc051d3b7b8f GIT binary patch literal 4096 -zcmeH_OK!s;5Qek1v -zf+m(;45hPl_w*CMQqMlf_)Jw%g;DBdpP?XVzT|YFCh1JGtai>}SQ=5a#wj4EoiSIc -zv0*lU6Aw4=81eTx$WghWqEQyRJhFjoAREXAvVm+M8^{K-fovcf$Od*{)W~{00kZ%K -xS#YcacB($#Sa%PAY;tyB+A`-A_=v#q=1vYcHE@0VPcPB9s-gkx36r~Qlpw1@NEY8X66?>XjCZl +z`Ga3mucVmEp;3|&UQlgW9n0$UU$y0|Rc&OgY9nh^8(GJ4)~YtLR<)6}s^_dm$8p*BlADM(P=Xsw7bQwwZuy|`&_^@_sCNI#n|VulTe17k?&z%=z(sEp4|jNp-cl0o +z-~=T}dnYNmrXH5s#jNLh7qgL+z^HNQvq2-YUwXO-O0>7_^4fc!@-mpr(Ru@d67<$y +z1ts%9u)l{0H;8H0-(A+D@q-XTP_nC3DwRs5QmIrbmC7!UnAjO7U=F|}mObl%oy6xG +o>mL~so4gwsI_9H+IBRejBTSEZYGRV5fb2YVX=Dj>_Hjqa58`6o(EtDd literal 0 HcmV?d00001 diff --git a/src/mainboard/pcengines/apu2/variants/apu6/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu6/devicetree.cb new file mode 100644 -index 000000000000..911df5af962e +index 0000000000..911df5af96 --- /dev/null +++ b/src/mainboard/pcengines/apu2/variants/apu6/devicetree.cb @@ -0,0 +1,60 @@ @@ -198,3 +212,6 @@ index 000000000000..911df5af962e + end + end +end +-- +2.49.0 + diff --git a/patches/0070-mainboard-pcengines-Use-FMAP-layout.patch b/patches/0070-mainboard-pcengines-Use-FMAP-layout.patch deleted file mode 100644 index 2670cc8..0000000 --- a/patches/0070-mainboard-pcengines-Use-FMAP-layout.patch +++ /dev/null @@ -1,143 +0,0 @@ -From 9fbeb3229cc84e739cb111ed4b969d1af5c0e7bc Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= -Date: Fri, 3 Apr 2020 13:33:39 +0200 -Subject: [PATCH 70/80] mainboard/pcengines: Use FMAP layout -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This commit removes the condition for the 'board.fmd' path, making it -the default path regardless of the VBOOT configuration. The changes have -been applied to the configurations of pcengines_apu2, pcengines_apu3, -pcengines_apu4, pcengines_apu5, and pcengines_apu6. A new file -'board.fmd' has also been added to 'src/mainboard/pcengines/apu2'. - -Signed-off-by: Michał Żygowski ---- - configs/config.pcengines_apu2 | 1 + - configs/config.pcengines_apu3 | 1 + - configs/config.pcengines_apu4 | 1 + - configs/config.pcengines_apu5 | 1 + - configs/config.pcengines_apu6 | 1 + - src/mainboard/pcengines/apu2/Kconfig | 5 +++-- - src/mainboard/pcengines/apu2/board.fmd | 18 ++++++++++++++++++ - 7 files changed, 26 insertions(+), 2 deletions(-) - create mode 100644 src/mainboard/pcengines/apu2/board.fmd - -diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2 -index 0e97a3d7d780..ddcea3688e7e 100644 ---- a/configs/config.pcengines_apu2 -+++ b/configs/config.pcengines_apu2 -@@ -18,6 +18,7 @@ CONFIG_PXE_CUSTOM_BUILD_ID="12345678" - CONFIG_PXE_ROM_ID="8086,157b" - CONFIG_PXE_SCRIPT="payloads/external/iPXE/menu.ipxe" - CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" -+CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y - CONFIG_SEABIOS_DEBUG_LEVEL=0 - CONFIG_SEABIOS_REVISION=y - CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" -diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3 -index 7296287d0cab..2d6035ba8c02 100644 ---- a/configs/config.pcengines_apu3 -+++ b/configs/config.pcengines_apu3 -@@ -19,6 +19,7 @@ CONFIG_PXE_CUSTOM_BUILD_ID="12345678" - CONFIG_PXE_ROM_ID="8086,1539" - CONFIG_PXE_SCRIPT="payloads/external/iPXE/menu.ipxe" - CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" -+CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y - CONFIG_SEABIOS_DEBUG_LEVEL=0 - CONFIG_SEABIOS_REVISION=y - CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" -diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4 -index bd765c2f606c..725d823abbfa 100644 ---- a/configs/config.pcengines_apu4 -+++ b/configs/config.pcengines_apu4 -@@ -19,6 +19,7 @@ CONFIG_PXE_CUSTOM_BUILD_ID="12345678" - CONFIG_PXE_ROM_ID="8086,1539" - CONFIG_PXE_SCRIPT="payloads/external/iPXE/menu.ipxe" - CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" -+CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y - CONFIG_SEABIOS_DEBUG_LEVEL=0 - CONFIG_SEABIOS_REVISION=y - CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" -diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5 -index b1b91846d394..7fc5be58711e 100644 ---- a/configs/config.pcengines_apu5 -+++ b/configs/config.pcengines_apu5 -@@ -19,6 +19,7 @@ CONFIG_PXE_CUSTOM_BUILD_ID="12345678" - CONFIG_PXE_ROM_ID="8086,1539" - CONFIG_PXE_SCRIPT="payloads/external/iPXE/menu.ipxe" - CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" -+CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y - CONFIG_SEABIOS_DEBUG_LEVEL=0 - CONFIG_SEABIOS_REVISION=y - CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" -diff --git a/configs/config.pcengines_apu6 b/configs/config.pcengines_apu6 -index 0cee4afcecdb..cdde0474b25a 100644 ---- a/configs/config.pcengines_apu6 -+++ b/configs/config.pcengines_apu6 -@@ -19,6 +19,7 @@ CONFIG_PXE_CUSTOM_BUILD_ID="12345678" - CONFIG_PXE_ROM_ID="8086,1539" - CONFIG_PXE_SCRIPT="payloads/external/iPXE/menu.ipxe" - CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" -+CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y - CONFIG_SEABIOS_DEBUG_LEVEL=0 - CONFIG_SEABIOS_REVISION=y - CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" -diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig -index 66424e3ca995..152e23352196 100644 ---- a/src/mainboard/pcengines/apu2/Kconfig -+++ b/src/mainboard/pcengines/apu2/Kconfig -@@ -75,7 +75,7 @@ config APU2_PINMUX_OFF_C - config APU2_PINMUX_GPIO0 - bool "GPIO" - depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \ -- BOARD_PCENGINES_APU4 || BOARD_PCENGINES_APU6 -+ BOARD_PCENGINES_APU4 || BOARD_PCENGINES_APU6 - - config APU2_PINMUX_UART_C - bool "UART 0x3e8" -@@ -92,7 +92,7 @@ config APU2_PINMUX_OFF_D - config APU2_PINMUX_GPIO1 - bool "GPIO" - depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \ -- BOARD_PCENGINES_APU4 || BOARD_PCENGINES_APU6 -+ BOARD_PCENGINES_APU4 || BOARD_PCENGINES_APU6 - - config APU2_PINMUX_UART_D - bool "UART 0x2e8" -@@ -111,6 +111,7 @@ config FORCE_MPCIE2_CLK - config FMDFILE - string - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rw-ab.fmd" if VBOOT -+ default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" - - config CBFS_SIZE - hex -diff --git a/src/mainboard/pcengines/apu2/board.fmd b/src/mainboard/pcengines/apu2/board.fmd -new file mode 100644 -index 000000000000..0f344e580caa ---- /dev/null -+++ b/src/mainboard/pcengines/apu2/board.fmd -@@ -0,0 +1,18 @@ -+FLASH 8M { -+ SI_BIOS@0x0 0x800000 { -+ BOOTORDER(PRESERVE)@0x0 0x1000 -+ RW_VPD(PRESERVE)@0x1000 0x4000 -+ SMMSTORE(PRESERVE)@0x5000 0x20000 -+ RW_UNUSED@0x25000 0x1db000 -+ WP_RO@0x200000 0x600000{ -+ RO_VPD(PRESERVE)@0x0 0x4000 -+ RO_SECTION@0x4000 0x5fc000{ -+ FMAP@0x0 0x800 -+ RO_FRID@0x800 0x40 -+ RO_FRID_PAD@0x840 0x7c0 -+ GBB@0x1000 0x40000 -+ COREBOOT(CBFS)@0x41000 0x5bb000 -+ } -+ } -+ } -+} --- -2.39.2 - diff --git a/patches/0066-pcengines-apu2-OemCustomize.c-Add-specific-PCIe-orde.patch b/patches/0070-pcengines-apu2-OemCustomize.c-Add-specific-PCIe-orde.patch similarity index 97% rename from patches/0066-pcengines-apu2-OemCustomize.c-Add-specific-PCIe-orde.patch rename to patches/0070-pcengines-apu2-OemCustomize.c-Add-specific-PCIe-orde.patch index c2cd8bd..d08945a 100644 --- a/patches/0066-pcengines-apu2-OemCustomize.c-Add-specific-PCIe-orde.patch +++ b/patches/0070-pcengines-apu2-OemCustomize.c-Add-specific-PCIe-orde.patch @@ -1,16 +1,17 @@ -From 6d67b8767a689e0c2c61c387788860a9224722af Mon Sep 17 00:00:00 2001 +From 50a7205c4ae8e43ce1b0176a26b04f66c5ca2531 Mon Sep 17 00:00:00 2001 From: Marek Kasiewicz Date: Fri, 23 Oct 2020 14:13:52 +0200 -Subject: [PATCH 66/80] pcengines/apu2/OemCustomize.c: Add specific PCIe order +Subject: [PATCH 70/88] pcengines/apu2/OemCustomize.c: Add specific PCIe order config for apu2 +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Marek Kasiewicz --- src/mainboard/pcengines/apu2/OemCustomize.c | 156 ++++++++++++++++++-- 1 file changed, 141 insertions(+), 15 deletions(-) diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c -index d868850ff90e..e803173716d8 100644 +index d868850ff9..e803173716 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -132,9 +132,9 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { @@ -261,5 +262,5 @@ index d868850ff90e..e803173716d8 100644 .Flags = DESCRIPTOR_TERMINATE_LIST, .SocketId = 0, -- -2.39.2 +2.49.0 diff --git a/patches/0071-mainboard-pcengines-Update-GPIO-configuration-and-re.patch b/patches/0071-mainboard-pcengines-Update-GPIO-configuration-and-re.patch new file mode 100644 index 0000000..03fb0fe --- /dev/null +++ b/patches/0071-mainboard-pcengines-Update-GPIO-configuration-and-re.patch @@ -0,0 +1,34 @@ +From 711d4be70a678bddbd21e847d6e4f60cd9c99c33 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= +Date: Sun, 5 May 2024 00:35:25 +0200 +Subject: [PATCH 71/88] mainboard/pcengines: Update GPIO configuration and + remove unused macros +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This commit updates the GPIO configuration for apu3, apu4, and apu7 +boards. It also removes unused macros for SIO_PORT and SERIAL_DEV. + +Upstream-Status: Pending +Signed-off-by: Piotr Król +--- + src/mainboard/pcengines/apu2/romstage.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c +index 71b5170ce4..aa428874b0 100644 +--- a/src/mainboard/pcengines/apu2/romstage.c ++++ b/src/mainboard/pcengines/apu2/romstage.c +@@ -27,6 +27,8 @@ void board_BeforeAgesa(struct sysinfo *cb) + { + u32 val; + ++ pm_write8(FCH_PMIOA_REGC5, 0); ++ + early_lpc_init(); + + /* Disable SVI2 controller to wait for command completion */ +-- +2.49.0 + diff --git a/patches/0068-payloads-external-SeaBIOS-add-bootorder-in-FMAP-opti.patch b/patches/0072-payloads-external-SeaBIOS-add-bootorder-in-FMAP-opti.patch similarity index 83% rename from patches/0068-payloads-external-SeaBIOS-add-bootorder-in-FMAP-opti.patch rename to patches/0072-payloads-external-SeaBIOS-add-bootorder-in-FMAP-opti.patch index bb4d9f4..03c5245 100644 --- a/patches/0068-payloads-external-SeaBIOS-add-bootorder-in-FMAP-opti.patch +++ b/patches/0072-payloads-external-SeaBIOS-add-bootorder-in-FMAP-opti.patch @@ -1,15 +1,21 @@ -From 53112ce1182affdd15cd610bd79f8e7589553511 Mon Sep 17 00:00:00 2001 +From 8172d927c4c78fceb79e29b4d12de6ad35dc392e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 3 Apr 2020 13:32:04 +0200 -Subject: [PATCH 68/80] payloads/external/SeaBIOS: add bootorder in FMAP option +Subject: [PATCH 72/88] payloads/external/SeaBIOS: add bootorder in FMAP option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Michał Żygowski Signed-off-by: Piotr Król +--- + payloads/external/Makefile.mk | 11 +++++++++++ + payloads/external/SeaBIOS/Kconfig | 6 ++++++ + 2 files changed, 17 insertions(+) + diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk -index a4698e749ad8..4f2d51015a5d 100644 +index eb6c014d46..f40fb68db1 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -99,12 +99,14 @@ img/seabios-type := payload @@ -44,7 +50,7 @@ index a4698e749ad8..4f2d51015a5d 100644 ifneq ($(strip $(CONFIG_SEABIOS_BOOTORDER_DEF_FILE)),) cbfs-files-y += bootorder_def diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig -index 20b65495f437..13d69f6c077d 100644 +index 990923858e..bc749b04c0 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -93,6 +93,12 @@ config PAYLOAD_CONFIGFILE @@ -60,3 +66,6 @@ index 20b65495f437..13d69f6c077d 100644 config SEABIOS_BOOTORDER_FILE string "SeaBIOS bootorder file" default "" +-- +2.49.0 + diff --git a/patches/0069-mainboard-pcengines-Add-support-for-sercon-port.patch b/patches/0073-mainboard-pcengines-Add-support-for-sercon-port.patch similarity index 74% rename from patches/0069-mainboard-pcengines-Add-support-for-sercon-port.patch rename to patches/0073-mainboard-pcengines-Add-support-for-sercon-port.patch index 469804f..5c909a9 100644 --- a/patches/0069-mainboard-pcengines-Add-support-for-sercon-port.patch +++ b/patches/0073-mainboard-pcengines-Add-support-for-sercon-port.patch @@ -1,7 +1,7 @@ -From 1b17efb4b72f50ed27e2e60110fcf3fbbdafb0a3 Mon Sep 17 00:00:00 2001 +From b4d9867dedd8c7897008de4ef52a01017c5d794c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Wed, 8 May 2024 01:30:49 +0200 -Subject: [PATCH 69/80] mainboard/pcengines: Add support for sercon-port +Subject: [PATCH 73/88] mainboard/pcengines: Add support for sercon-port MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit @@ -10,9 +10,16 @@ This commit adds support for sercon-port in the SeaBIOS for the pcengines mainboard. The sercon-port file is added to the cbfs-files if the CONFIG_SEABIOS_SERCON_PORT_FILE is set. +Upstream-Status: Inappropriate [Use SEABIOS_SERCON_PORT_ADDR Kconfig] Signed-off-by: Piotr Król +--- + payloads/external/Makefile.mk | 7 ++++++- + src/mainboard/pcengines/apu2/sercon-port | Bin 0 -> 8 bytes + 2 files changed, 6 insertions(+), 1 deletion(-) + create mode 100644 src/mainboard/pcengines/apu2/sercon-port + diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk -index 4f2d51015a5d..f3e561cacf33 100644 +index f40fb68db1..dafc3b7fb2 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -151,7 +151,12 @@ cbfs-files-y += etc/boot-menu-message @@ -39,3 +46,6 @@ Lcmeyt%m4-e2i*Yt literal 0 HcmV?d00001 +-- +2.49.0 + diff --git a/patches/0074-mainboard-pcengines-Use-FMAP-layout.patch b/patches/0074-mainboard-pcengines-Use-FMAP-layout.patch new file mode 100644 index 0000000..3810515 --- /dev/null +++ b/patches/0074-mainboard-pcengines-Use-FMAP-layout.patch @@ -0,0 +1,113 @@ +From a6d61669fb5dfabd942db5020e97a806a6441a23 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= +Date: Fri, 3 Apr 2020 13:33:39 +0200 +Subject: [PATCH 74/88] mainboard/pcengines: Use FMAP layout +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This commit removes the condition for the 'board.fmd' path, making it +the default path regardless of the VBOOT configuration. The changes have +been applied to the configurations of pcengines_apu2, pcengines_apu3, +pcengines_apu4, pcengines_apu5, and pcengines_apu6. A new file +'board.fmd' has also been added to 'src/mainboard/pcengines/apu2'. + +Upstream-Status: Inappropriate [Should utilize existing option backend] +Signed-off-by: Michał Żygowski +--- + configs/config.pcengines_seabios_apu2 | 1 + + configs/config.pcengines_seabios_apu3 | 1 + + configs/config.pcengines_seabios_apu4 | 1 + + configs/config.pcengines_seabios_apu6 | 1 + + src/mainboard/pcengines/apu2/Kconfig | 1 + + src/mainboard/pcengines/apu2/board.fmd | 18 ++++++++++++++++++ + 6 files changed, 23 insertions(+) + create mode 100644 src/mainboard/pcengines/apu2/board.fmd + +diff --git a/configs/config.pcengines_seabios_apu2 b/configs/config.pcengines_seabios_apu2 +index 572900c4bb..69eca3ee40 100644 +--- a/configs/config.pcengines_seabios_apu2 ++++ b/configs/config.pcengines_seabios_apu2 +@@ -20,6 +20,7 @@ CONFIG_POST_IO_PORT=0x80 + CONFIG_PXE=y + CONFIG_PXE_ROM_ID="8086,157b" + CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" ++CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y + CONFIG_SEABIOS_DEBUG_LEVEL=0 + CONFIG_SEABIOS_REVISION=y + CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" +diff --git a/configs/config.pcengines_seabios_apu3 b/configs/config.pcengines_seabios_apu3 +index 0c36d4813b..b9f7a009ef 100644 +--- a/configs/config.pcengines_seabios_apu3 ++++ b/configs/config.pcengines_seabios_apu3 +@@ -21,6 +21,7 @@ CONFIG_POST_IO_PORT=0x80 + CONFIG_PXE=y + CONFIG_PXE_ROM_ID="8086,1539" + CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" ++CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y + CONFIG_SEABIOS_DEBUG_LEVEL=0 + CONFIG_SEABIOS_REVISION=y + CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" +diff --git a/configs/config.pcengines_seabios_apu4 b/configs/config.pcengines_seabios_apu4 +index 7b737175e6..c71e9826ee 100644 +--- a/configs/config.pcengines_seabios_apu4 ++++ b/configs/config.pcengines_seabios_apu4 +@@ -21,6 +21,7 @@ CONFIG_POST_IO_PORT=0x80 + CONFIG_PXE=y + CONFIG_PXE_ROM_ID="8086,1539" + CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" ++CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y + CONFIG_SEABIOS_DEBUG_LEVEL=0 + CONFIG_SEABIOS_REVISION=y + CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" +diff --git a/configs/config.pcengines_seabios_apu6 b/configs/config.pcengines_seabios_apu6 +index 639811e0c8..764f24f198 100644 +--- a/configs/config.pcengines_seabios_apu6 ++++ b/configs/config.pcengines_seabios_apu6 +@@ -21,6 +21,7 @@ CONFIG_POST_IO_PORT=0x80 + CONFIG_PXE=y + CONFIG_PXE_ROM_ID="8086,1539" + CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" ++CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y + CONFIG_SEABIOS_DEBUG_LEVEL=0 + CONFIG_SEABIOS_REVISION=y + CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" +diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig +index ee8e8c9f47..0561dcdfa9 100644 +--- a/src/mainboard/pcengines/apu2/Kconfig ++++ b/src/mainboard/pcengines/apu2/Kconfig +@@ -108,6 +108,7 @@ config FORCE_MPCIE2_CLK + config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rw-ab.fmd" if VBOOT ++ default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + + config CBFS_SIZE + hex +diff --git a/src/mainboard/pcengines/apu2/board.fmd b/src/mainboard/pcengines/apu2/board.fmd +new file mode 100644 +index 0000000000..0f344e580c +--- /dev/null ++++ b/src/mainboard/pcengines/apu2/board.fmd +@@ -0,0 +1,18 @@ ++FLASH 8M { ++ SI_BIOS@0x0 0x800000 { ++ BOOTORDER(PRESERVE)@0x0 0x1000 ++ RW_VPD(PRESERVE)@0x1000 0x4000 ++ SMMSTORE(PRESERVE)@0x5000 0x20000 ++ RW_UNUSED@0x25000 0x1db000 ++ WP_RO@0x200000 0x600000{ ++ RO_VPD(PRESERVE)@0x0 0x4000 ++ RO_SECTION@0x4000 0x5fc000{ ++ FMAP@0x0 0x800 ++ RO_FRID@0x800 0x40 ++ RO_FRID_PAD@0x840 0x7c0 ++ GBB@0x1000 0x40000 ++ COREBOOT(CBFS)@0x41000 0x5bb000 ++ } ++ } ++ } ++} +-- +2.49.0 + diff --git a/patches/0074-nb-amd-enable-ProcessorScopeInSb-for-fam14-and-00730.patch b/patches/0074-nb-amd-enable-ProcessorScopeInSb-for-fam14-and-00730.patch deleted file mode 100644 index c57bba1..0000000 --- a/patches/0074-nb-amd-enable-ProcessorScopeInSb-for-fam14-and-00730.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 299ef598aca1512678db42c30e7cad0c83e5d43d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= -Date: Tue, 5 Oct 2021 13:26:54 +0200 -Subject: [PATCH 74/80] nb/amd: enable ProcessorScopeInSb for fam14 and - 00730F01 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Michał Kopeć ---- - src/northbridge/amd/pi/00730F01/state_machine.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c -index ba34dabde906..9215f7a86b38 100644 ---- a/src/northbridge/amd/pi/00730F01/state_machine.c -+++ b/src/northbridge/amd/pi/00730F01/state_machine.c -@@ -72,6 +72,8 @@ void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) - * present AGESA_ERROR is returned, which confuses users. CDIT is not - * written to the ACPI tables anyway. */ - Late->PlatformConfig.UserOptionCdit = 0; -+ -+ Late->PlatformConfig.ProcessorScopeInSb = 1; - } - - void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) --- -2.39.2 - diff --git a/patches/0071-mainboard-pcengines-avoid-ASSERT-on-the-stack-overwr.patch b/patches/0075-mainboard-pcengines-avoid-ASSERT-on-the-stack-overwr.patch similarity index 73% rename from patches/0071-mainboard-pcengines-avoid-ASSERT-on-the-stack-overwr.patch rename to patches/0075-mainboard-pcengines-avoid-ASSERT-on-the-stack-overwr.patch index 1fc45a2..3112d08 100644 --- a/patches/0071-mainboard-pcengines-avoid-ASSERT-on-the-stack-overwr.patch +++ b/patches/0075-mainboard-pcengines-avoid-ASSERT-on-the-stack-overwr.patch @@ -1,22 +1,23 @@ -From 76a167dd928f766722ecd4c47ceb08f8a5508557 Mon Sep 17 00:00:00 2001 +From 6c819f6c3c14c7878446d7ca8ccbff80c3c3e766 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Thu, 2 May 2024 12:17:52 +0200 -Subject: [PATCH 71/80] mainboard/pcengines: avoid ASSERT on the stack +Subject: [PATCH 75/88] mainboard/pcengines: avoid ASSERT on the stack overwrite during flashing bootorder MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Piotr Król --- src/mainboard/pcengines/apu2/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig -index 152e23352196..9167f2f0bf08 100644 +index 0561dcdfa9..0de22561a2 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig -@@ -151,4 +151,9 @@ config AGESA_USE_1_0_0_4_HEADER +@@ -148,4 +148,9 @@ config AGESA_USE_1_0_0_4_HEADER revisions. This option removes the changes in headers introduced with AGESA 1.0.0.A to fit the 1.0.0.4 revision. @@ -27,5 +28,5 @@ index 152e23352196..9167f2f0bf08 100644 + endif # BOARD_PCENGINES_APU2 -- -2.39.2 +2.49.0 diff --git a/patches/0072-amdblocks-psp_efs.h-allow-for-PI-00730F01-platforms.patch b/patches/0076-amdblocks-psp_efs.h-allow-for-PI-00730F01-platforms.patch similarity index 82% rename from patches/0072-amdblocks-psp_efs.h-allow-for-PI-00730F01-platforms.patch rename to patches/0076-amdblocks-psp_efs.h-allow-for-PI-00730F01-platforms.patch index b7fb373..095a4f2 100644 --- a/patches/0072-amdblocks-psp_efs.h-allow-for-PI-00730F01-platforms.patch +++ b/patches/0076-amdblocks-psp_efs.h-allow-for-PI-00730F01-platforms.patch @@ -1,18 +1,19 @@ -From 8a376acfe8d8c8baa1ce885c3882993cca2b3da8 Mon Sep 17 00:00:00 2001 +From d72b66a93fd27ed86cd5fb951077c29ef4b594db Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Fri, 3 Sep 2021 15:03:06 +0200 -Subject: [PATCH 72/80] amdblocks/psp_efs.h: allow for PI 00730F01 platforms +Subject: [PATCH 76/88] amdblocks/psp_efs.h: allow for PI 00730F01 platforms MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Pending Signed-off-by: Michał Kopeć --- src/soc/amd/common/block/include/amdblocks/psp_efs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h -index 51b06a68100b..9cc3fc2a6e10 100644 +index d0b9b016d2..17efc1adb3 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h +++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h @@ -10,7 +10,7 @@ @@ -25,5 +26,5 @@ index 51b06a68100b..9cc3fc2a6e10 100644 #define SPI_SPEED_FIELD fast_speed_new_f15_mod_60_6f #elif CONFIG(SOC_AMD_PICASSO) -- -2.39.2 +2.49.0 diff --git a/patches/0077-mb-pcengines-apu2-add-variant-apu7.patch b/patches/0077-mb-pcengines-apu2-add-variant-apu7.patch deleted file mode 100644 index d1d1779..0000000 --- a/patches/0077-mb-pcengines-apu2-add-variant-apu7.patch +++ /dev/null @@ -1,204 +0,0 @@ -From d55f700035eba51312308523c150e469d667168e Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= -Date: Thu, 2 Jun 2022 17:48:42 +0200 -Subject: [PATCH 77/80] mb/pcengines/apu2: add variant apu7 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -apu7 is an apu3 with different NICs (Intel i225). - -For now, it doesn't support iPXE network booting. - -Change-Id: I495879f1527643b217f9facb07dace5d70175a3e -Signed-off-by: Michał Kopeć -diff --git a/configs/config.pcengines_apu7 b/configs/config.pcengines_apu7 -new file mode 100644 -index 000000000000..a416468b44fb ---- /dev/null -+++ b/configs/config.pcengines_apu7 -@@ -0,0 +1,29 @@ -+# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set -+# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set -+# CONFIG_IPXE_SERIAL_CONSOLE is not set -+CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000 -+CONFIG_BOARD_PCENGINES_APU7=y -+CONFIG_BOTTOMIO_POSITION=0xD0000000 -+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 -+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y -+CONFIG_HUDSON_SATA_MODE=2 -+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 -+CONFIG_IPXE_ADD_SCRIPT=y -+CONFIG_IPXE_SCRIPT="payloads/external/iPXE/menu.ipxe" -+CONFIG_LOCALVERSION="v24.05.00.01" -+CONFIG_MEMTEST86PLUS_V5=y -+CONFIG_MEMTEST_SECONDARY_PAYLOAD=y -+CONFIG_NO_GFX_INIT=y -+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config" -+CONFIG_POST_IO_PORT=0x80 -+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder" -+CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y -+CONFIG_SEABIOS_DEBUG_LEVEL=0 -+CONFIG_SEABIOS_NO_OPROMS=y -+CONFIG_SEABIOS_REVISION=y -+CONFIG_SEABIOS_REVISION_ID="rel-1.16.0.1" -+CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 -+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 -+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 -+CONFIG_TPM2=y -+CONFIG_VENDOR_PCENGINES=y -diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig -index 0de22561a2a0..6271f6430382 100644 ---- a/src/mainboard/pcengines/apu2/Kconfig -+++ b/src/mainboard/pcengines/apu2/Kconfig -@@ -1,7 +1,7 @@ - # SPDX-License-Identifier: GPL-2.0-only - - if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \ -- BOARD_PCENGINES_APU5 || BOARD_PCENGINES_APU6 -+ BOARD_PCENGINES_APU5 || BOARD_PCENGINES_APU6 || BOARD_PCENGINES_APU7 - - config BOARD_SPECIFIC_OPTIONS - def_bool y -@@ -31,6 +31,7 @@ config VARIANT_DIR - default "apu4" if BOARD_PCENGINES_APU4 - default "apu5" if BOARD_PCENGINES_APU5 - default "apu6" if BOARD_PCENGINES_APU6 -+ default "apu7" if BOARD_PCENGINES_APU7 - - config DEVICETREE - default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" -@@ -41,10 +42,7 @@ config MAINBOARD_PART_NUMBER - default "apu4" if BOARD_PCENGINES_APU4 - default "apu5" if BOARD_PCENGINES_APU5 - default "apu6" if BOARD_PCENGINES_APU6 -- --config DEFAULT_CONSOLE_LOGLEVEL -- int -- default 1 -+ default "apu7" if BOARD_PCENGINES_APU7 - - config MAX_CPUS - int -@@ -72,7 +70,7 @@ config APU2_PINMUX_OFF_C - config APU2_PINMUX_GPIO0 - bool "GPIO" - depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \ -- BOARD_PCENGINES_APU4 || BOARD_PCENGINES_APU6 -+ BOARD_PCENGINES_APU4 || BOARD_PCENGINES_APU6 || BOARD_PCENGINES_APU7 - - config APU2_PINMUX_UART_C - bool "UART 0x3e8" -@@ -89,7 +87,7 @@ config APU2_PINMUX_OFF_D - config APU2_PINMUX_GPIO1 - bool "GPIO" - depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \ -- BOARD_PCENGINES_APU4 || BOARD_PCENGINES_APU6 -+ BOARD_PCENGINES_APU4 || BOARD_PCENGINES_APU6 || BOARD_PCENGINES_APU7 - - config APU2_PINMUX_UART_D - bool "UART 0x2e8" -diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name -index 8ee55dbe6057..c65a5131e121 100644 ---- a/src/mainboard/pcengines/apu2/Kconfig.name -+++ b/src/mainboard/pcengines/apu2/Kconfig.name -@@ -14,3 +14,6 @@ config BOARD_PCENGINES_APU5 - - config BOARD_PCENGINES_APU6 - bool "APU6" -+ -+config BOARD_PCENGINES_APU7 -+ bool "APU7" -diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl -index 0a91feec580e..4c11ca2ab67b 100644 ---- a/src/mainboard/pcengines/apu2/dsdt.asl -+++ b/src/mainboard/pcengines/apu2/dsdt.asl -@@ -12,6 +12,8 @@ - #define DEVICE_NAME "apu5 - #elif CONFIG(BOARD_PCENGINES_APU6) - #define DEVICE_NAME "apu6 -+#elif CONFIG(BOARD_PCENGINES_APU7) -+#define DEVICE_NAME "apu7 - #endif - - #include -diff --git a/src/mainboard/pcengines/apu2/variants/apu7/bootorder b/src/mainboard/pcengines/apu2/variants/apu7/bootorder -new file mode 100644 -index 0000000000000000000000000000000000000000..f2dc50a9717e36e2211eb381ef66ae185d5b37da -GIT binary patch -literal 4096 -zcmeH_OK!s;5Qek1sOHLPRlFl?scjp|2g`;YXQ$SEVW3E(V -z!)*R09&X?<;_q{iqjEz Date: Wed, 28 Jul 2021 11:14:13 +0200 -Subject: [PATCH 73/80] pcengines/apu2: enable EHCI controller by default +Subject: [PATCH 77/88] pcengines/apu2: enable EHCI controller by default MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit on apu3,4,5 and 6 +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Michał Kopeć --- src/mainboard/pcengines/apu2/bootorder_def | 2 +- - .../pcengines/apu2/bootorder_def_apu5 | 2 +- .../pcengines/apu2/variants/apu3/bootorder | Bin 4096 -> 4096 bytes .../pcengines/apu2/variants/apu4/bootorder | Bin 4096 -> 4096 bytes .../pcengines/apu2/variants/apu6/bootorder | Bin 4096 -> 4096 bytes - 5 files changed, 2 insertions(+), 2 deletions(-) + 4 files changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/pcengines/apu2/bootorder_def b/src/mainboard/pcengines/apu2/bootorder_def -index 88da074dd189..774434f980f8 100644 +index 88da074dd1..774434f980 100644 --- a/src/mainboard/pcengines/apu2/bootorder_def +++ b/src/mainboard/pcengines/apu2/bootorder_def @@ -21,7 +21,7 @@ scon1 @@ -26,19 +26,6 @@ index 88da074dd189..774434f980f8 100644 uartc1 uartd1 -ehcien0 -+ehcien1 - mpcie2_clk0 - com2_en0 - boosten1 -diff --git a/src/mainboard/pcengines/apu2/bootorder_def_apu5 b/src/mainboard/pcengines/apu2/bootorder_def_apu5 -index 7885710c5476..0a00cc00b309 100644 ---- a/src/mainboard/pcengines/apu2/bootorder_def_apu5 -+++ b/src/mainboard/pcengines/apu2/bootorder_def_apu5 -@@ -21,7 +21,7 @@ scon1 - usben1 - uartc1 - uartd1 --ehcien0 +ehcien1 mpcie2_clk0 com2_en0 @@ -71,5 +58,5 @@ delta 14 VcmZorXi(T-%EV}}*^KEFF909_1RDSV -- -2.39.2 +2.49.0 diff --git a/patches/0075-src-northbridge-amd-pi-00730F01-northbridge.c-enable.patch b/patches/0078-src-northbridge-amd-pi-00730F01-northbridge.c-enable.patch similarity index 73% rename from patches/0075-src-northbridge-amd-pi-00730F01-northbridge.c-enable.patch rename to patches/0078-src-northbridge-amd-pi-00730F01-northbridge.c-enable.patch index 33b9b64..4d6347c 100644 --- a/patches/0075-src-northbridge-amd-pi-00730F01-northbridge.c-enable.patch +++ b/patches/0078-src-northbridge-amd-pi-00730F01-northbridge.c-enable.patch @@ -1,22 +1,23 @@ -From 17b503d79a81e9cda8e21966fcea381f4f9720b3 Mon Sep 17 00:00:00 2001 +From c7a62852e7dc9c3d200d39d2f215e27bf235fc29 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 7 Mar 2022 13:06:38 +0100 -Subject: [PATCH 75/80] src/northbridge/amd/pi/00730F01/northbridge.c: enable +Subject: [PATCH 78/88] src/northbridge/amd/pi/00730F01/northbridge.c: enable PSP MMIO BARs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Pending Signed-off-by: Michał Żygowski --- src/northbridge/amd/pi/00730F01/northbridge.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c -index afaa7b22f353..565a4c37cbf5 100644 +index 519c190812..f9540973b9 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c -@@ -794,6 +794,11 @@ static void fam16_finalize(void *chip_info) +@@ -643,6 +643,11 @@ static void fam16_finalize(void *chip_info) if (dev != NULL) { pci_and_config32(dev, 0x60, ~(1 << 11)); } @@ -27,7 +28,7 @@ index afaa7b22f353..565a4c37cbf5 100644 + pci_update_config8(dev, 0x48, 0xff, 0x3d); } - struct chip_operations northbridge_amd_pi_00730F01_ops = { + struct hw_mem_hole_info { -- -2.39.2 +2.49.0 diff --git a/patches/0079-mainboard-pcengines-make-HUDSON_LEGACY_FREE-n-by-def.patch b/patches/0079-mainboard-pcengines-make-HUDSON_LEGACY_FREE-n-by-def.patch deleted file mode 100644 index 91324f1..0000000 --- a/patches/0079-mainboard-pcengines-make-HUDSON_LEGACY_FREE-n-by-def.patch +++ /dev/null @@ -1,30 +0,0 @@ -From e231b58275e9f177abd13cf60fafa29b83c6349d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= -Date: Fri, 3 May 2024 01:11:49 +0200 -Subject: [PATCH 79/80] mainboard/pcengines: make HUDSON_LEGACY_FREE n by - default -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Piotr Król ---- - src/mainboard/pcengines/apu2/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig -index da13f5750106..b5d9b2cd03dc 100644 ---- a/src/mainboard/pcengines/apu2/Kconfig -+++ b/src/mainboard/pcengines/apu2/Kconfig -@@ -57,7 +57,7 @@ config ONBOARD_VGA_IS_PRIMARY - - config HUDSON_LEGACY_FREE - bool -- default y -+ default n - - config AGESA_BINARY_PI_FILE - string --- -2.39.2 - diff --git a/patches/0076-payloads-external-SeaBIOS-add-bootorder-in-FMAP-opti.patch b/patches/0079-payloads-external-SeaBIOS-add-bootorder-in-FMAP-opti.patch similarity index 80% rename from patches/0076-payloads-external-SeaBIOS-add-bootorder-in-FMAP-opti.patch rename to patches/0079-payloads-external-SeaBIOS-add-bootorder-in-FMAP-opti.patch index 36f572b..5744e6a 100644 --- a/patches/0076-payloads-external-SeaBIOS-add-bootorder-in-FMAP-opti.patch +++ b/patches/0079-payloads-external-SeaBIOS-add-bootorder-in-FMAP-opti.patch @@ -1,15 +1,21 @@ -From 70997c8bb05c22d483c61be2bea4dbcc67fd2a7b Mon Sep 17 00:00:00 2001 +From 86ac9900a76915fbfd1b917a97cd8f6a137e91de Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Thu, 2 Jun 2022 17:42:14 +0200 -Subject: [PATCH 76/80] payloads/external/SeaBIOS: add bootorder in FMAP option +Subject: [PATCH 79/88] payloads/external/SeaBIOS: add bootorder in FMAP option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit +Upstream-Status: Inappropriate [Should utilize existing option backend] Signed-off-by: Michał Żygowski Signed-off-by: Piotr Król +--- + payloads/external/Makefile.mk | 8 ++++++++ + payloads/external/SeaBIOS/Kconfig | 7 +++++++ + 2 files changed, 15 insertions(+) + diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk -index f3e561cacf33..5fc5efa4dd3c 100644 +index dafc3b7fb2..ba68632d1f 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -157,6 +157,14 @@ cbfs-files-y += etc/sercon-port @@ -28,7 +34,7 @@ index f3e561cacf33..5fc5efa4dd3c 100644 ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) $(call add_intermediate, seabios_ps2_timeout, $(CBFSTOOL)) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig -index 13d69f6c077d..fe7648e6e340 100644 +index bc749b04c0..2ad5b01335 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -52,6 +52,13 @@ config SEABIOS_PS2_TIMEOUT @@ -45,3 +51,6 @@ index 13d69f6c077d..fe7648e6e340 100644 config SEABIOS_THREAD_OPTIONROMS prompt "Hardware init during option ROM execution" default n +-- +2.49.0 + diff --git a/patches/0078-mainboard-pcengines-fix-sign-of-life-coreboot-build-.patch b/patches/0080-mainboard-pcengines-fix-sign-of-life-coreboot-build-.patch similarity index 83% rename from patches/0078-mainboard-pcengines-fix-sign-of-life-coreboot-build-.patch rename to patches/0080-mainboard-pcengines-fix-sign-of-life-coreboot-build-.patch index 7f70008..9a36b12 100644 --- a/patches/0078-mainboard-pcengines-fix-sign-of-life-coreboot-build-.patch +++ b/patches/0080-mainboard-pcengines-fix-sign-of-life-coreboot-build-.patch @@ -1,7 +1,7 @@ -From a80c0e940afee2fa80f6ff9e24292cd55e016104 Mon Sep 17 00:00:00 2001 +From f8a0a0a6a6d1447367c077f328226d37af00edc7 Mon Sep 17 00:00:00 2001 From: Mark Mentovai Date: Sun, 5 Jun 2022 09:25:24 -0400 -Subject: [PATCH 78/80] mainboard/pcengines: fix sign-of-life coreboot build +Subject: [PATCH 80/88] mainboard/pcengines: fix sign-of-life coreboot build date The coreboot build date shown by print_sign_of_life at early boot was @@ -11,13 +11,14 @@ yyyymmdd. https://github.com/pcengines/coreboot/pull/517 contains a complete explanation of the history of this date string. +Upstream-Status: Inappropriate [Custom prints] Signed-off-by: Mark Mentovai --- src/mainboard/pcengines/apu2/romstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c -index 7329896fb14a..0e8105a0f1c9 100644 +index aa428874b0..d22c482a21 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -96,8 +96,8 @@ static void print_sign_of_life(void) @@ -32,5 +33,5 @@ index 7329896fb14a..0e8105a0f1c9 100644 printk(BIOS_ALERT, CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER "\n"); -- -2.39.2 +2.49.0 diff --git a/patches/0080-src-southbridge-amd-pi-hudson-Makefile.inc-fix-AMDFW.patch b/patches/0081-src-southbridge-amd-pi-hudson-Makefile.inc-fix-AMDFW.patch similarity index 80% rename from patches/0080-src-southbridge-amd-pi-hudson-Makefile.inc-fix-AMDFW.patch rename to patches/0081-src-southbridge-amd-pi-hudson-Makefile.inc-fix-AMDFW.patch index ae44012..51dda3f 100644 --- a/patches/0080-src-southbridge-amd-pi-hudson-Makefile.inc-fix-AMDFW.patch +++ b/patches/0081-src-southbridge-amd-pi-hudson-Makefile.inc-fix-AMDFW.patch @@ -1,7 +1,7 @@ -From 3812d71fa7cbb096b4af310ed4910ecb8b723fd7 Mon Sep 17 00:00:00 2001 +From da14b1ad66d3c9ed31737488fa48e228af6e7676 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 7 Oct 2019 15:41:52 +0200 -Subject: [PATCH 80/80] src/southbridge/amd/pi/hudson/Makefile.inc: fix AMDFW +Subject: [PATCH 81/88] src/southbridge/amd/pi/hudson/Makefile.inc: fix AMDFW outside CBFS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 @@ -16,10 +16,15 @@ Use shell printf to generate a hexadecimal value of HUDSON_FWM_POSITION. TEST=prepare simple FMD file with AMD_FW region at 0x20000, select CONFIG_AMDFW_OUTSIDE_CBFS and build PC Engines apu2 board +Upstream-Status: Submitted [CB:35853] Change-Id: Ib4b03f971b88acbc3392b66e084babe738659ea6 Signed-off-by: Michał Żygowski +--- + src/southbridge/amd/pi/hudson/Makefile.mk | 1 + + 1 file changed, 1 insertion(+) + diff --git a/src/southbridge/amd/pi/hudson/Makefile.mk b/src/southbridge/amd/pi/hudson/Makefile.mk -index e7ec1b73ec5a..5a4f88baeca3 100644 +index e7ec1b73ec..5a4f88baec 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.mk +++ b/src/southbridge/amd/pi/hudson/Makefile.mk @@ -126,6 +126,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ @@ -30,3 +35,6 @@ index e7ec1b73ec5a..5a4f88baeca3 100644 --config $(CONFIG_AMDFW_CONFIG_FILE) \ --output $@ +-- +2.49.0 + diff --git a/patches/makefile.mk-if-in-git-repository-use-git-describe-for-kernelversion.patch b/patches/0082-Makefile.mk-Use-git-describe-for-KERNELVERSION-if-in.patch similarity index 54% rename from patches/makefile.mk-if-in-git-repository-use-git-describe-for-kernelversion.patch rename to patches/0082-Makefile.mk-Use-git-describe-for-KERNELVERSION-if-in.patch index 49e3915..6b60aa7 100644 --- a/patches/makefile.mk-if-in-git-repository-use-git-describe-for-kernelversion.patch +++ b/patches/0082-Makefile.mk-Use-git-describe-for-KERNELVERSION-if-in.patch @@ -1,5 +1,17 @@ +From 051f96cacd0f9d35cc0393b0a59c6245bb9ae923 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= +Date: Thu, 29 May 2025 16:16:54 +0200 +Subject: [PATCH 82/88] Makefile.mk: Use git describe for KERNELVERSION if in + git repo + +Upstream-Status: Pending +Signed-off-by: Michał Żygowski +--- + Makefile.mk | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + diff --git a/Makefile.mk b/Makefile.mk -index 65b827fe3eaf..52b7a92d104d 100644 +index cc482acff4..8c10d54f7b 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -20,7 +20,9 @@ CONFIG_MEMLAYOUT_LD_FILE:=$(call strip_quotes, $(CONFIG_MEMLAYOUT_LD_FILE)) @@ -13,3 +25,6 @@ index 65b827fe3eaf..52b7a92d104d 100644 else KERNELVERSION := $(strip $(if $(GIT),\ $(shell git describe --abbrev=12 --dirty --always || git describe),\ +-- +2.49.0 + diff --git a/patches/0083-gitignore-add-memtest86plu_v5-and-sortbootorder-payl.patch b/patches/0083-gitignore-add-memtest86plu_v5-and-sortbootorder-payl.patch new file mode 100644 index 0000000..e04c4ff --- /dev/null +++ b/patches/0083-gitignore-add-memtest86plu_v5-and-sortbootorder-payl.patch @@ -0,0 +1,33 @@ +From 40632d0524518195063c9600eec6f179fbe62d25 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= +Date: Thu, 29 May 2025 16:17:54 +0200 +Subject: [PATCH 83/88] gitignore: add memtest86plu_v5 and sortbootorder + payloads +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Upstream-Status: Pending +Signed-off-by: Piotr Król +--- + .gitignore | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/.gitignore b/.gitignore +index e813493526..40f0f7cd78 100644 +--- a/.gitignore ++++ b/.gitignore +@@ -29,6 +29,10 @@ site-local + .test + .dependencies + ++# payloads ++payloads/external/Memtest86Plus/memtest86plus_v5/ ++payloads/external/sortbootorder/sortbootorder/ ++ + # Development friendly files + tags + .clang_complete +-- +2.49.0 + diff --git a/patches/0084-add-support-for-Dasharo-coreboot-SeaBIOS-for-QEMU-Q3.patch b/patches/0084-add-support-for-Dasharo-coreboot-SeaBIOS-for-QEMU-Q3.patch new file mode 100644 index 0000000..b05db68 --- /dev/null +++ b/patches/0084-add-support-for-Dasharo-coreboot-SeaBIOS-for-QEMU-Q3.patch @@ -0,0 +1,318 @@ +From 02cd3557cfd6ae74f3767eb1349be5283b63fd53 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= +Date: Thu, 29 May 2025 16:18:18 +0200 +Subject: [PATCH 84/88] add support for Dasharo(coreboot+SeaBIOS) for QEMU Q35 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Upstream-Status: Inappropriate [Should utilize existing option backend] +Signed-off-by: Piotr Król +--- + build.sh | 26 +++++++++----- + ...ig.emulation_qemu_x86_q35_smm_tseg_seabios | 30 ++++++++++++++++ + src/device/pciexp_device.c | 2 +- + src/drivers/uart/uart8250io.c | 2 +- + src/mainboard/emulation/qemu-q35/Kconfig | 2 +- + src/mainboard/emulation/qemu-q35/board.fmd | 18 ++++++++++ + .../emulation/qemu-q35/boot-menu-key | Bin 0 -> 8 bytes + .../emulation/qemu-q35/boot-menu-message | 1 + + .../emulation/qemu-q35/boot-menu-wait | Bin 0 -> 8 bytes + src/mainboard/emulation/qemu-q35/bootorder | Bin 0 -> 4096 bytes + .../emulation/qemu-q35/bootorder_def | 32 ++++++++++++++++++ + .../emulation/qemu-q35/bootorder_map | 18 ++++++++++ + .../emulation/qemu-q35/seabios_config | 9 +++++ + 13 files changed, 129 insertions(+), 11 deletions(-) + create mode 100644 configs/config.emulation_qemu_x86_q35_smm_tseg_seabios + create mode 100644 src/mainboard/emulation/qemu-q35/board.fmd + create mode 100644 src/mainboard/emulation/qemu-q35/boot-menu-key + create mode 100644 src/mainboard/emulation/qemu-q35/boot-menu-message + create mode 100644 src/mainboard/emulation/qemu-q35/boot-menu-wait + create mode 100644 src/mainboard/emulation/qemu-q35/bootorder + create mode 100644 src/mainboard/emulation/qemu-q35/bootorder_def + create mode 100644 src/mainboard/emulation/qemu-q35/bootorder_map + create mode 100644 src/mainboard/emulation/qemu-q35/seabios_config + +diff --git a/build.sh b/build.sh +index bb9f7acfc6..3ef32f241b 100755 +--- a/build.sh ++++ b/build.sh +@@ -26,6 +26,7 @@ usage() { + echo -e "\toptiplex_9010_seabios - build Dasharo compatible with Dell OptiPlex 7010/9010 (SeaBIOS)" + echo -e "\tqemu - build Dasharo for QEMU Q35" + echo -e "\tqemu_full - build Dasharo for QEMU Q35 with all menus available" ++ echo -e "\tqemu_seabios - build Dasharo(coreboot+SeaBIOS) for QEMU Q35" + echo -e "\todroid_h4 - build Dasharo compatible with Hardkernel ODROID H4" + } + +@@ -203,13 +204,19 @@ function build_pcengines { + } + + function build_qemu { +- DEFCONFIG="configs/config.emulation_qemu_x86_q35_uefi${1:-}" ++ DEFCONFIG="configs/config.emulation_qemu_x86_q35_${1:-}" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + +- # checkout several submodules needed by these boards (some others are checked +- # out by coreboot's Makefile) +- git submodule update --init --force --checkout \ +- 3rdparty/dasharo-blobs ++ if [[ ${DEFCONFIG} == *_seabios ]]; then ++ git submodule update --init --recursive --checkout ++ else ++ # checkout several submodules needed by these boards (some others are checked ++ # out by coreboot's Makefile) ++ git submodule update --init --force --checkout \ ++ 3rdparty/dasharo-blobs \ ++ 3rdparty/vboot ++ fi ++ + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ +@@ -223,7 +230,7 @@ function build_qemu { + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot ${DASHARO_SDK} \ +- /bin/bash -c "make olddefconfig && make -j$(nproc)" ++ /bin/bash -c "make olddefconfig && make BUILD_TIMELESS=1 -j$(nproc)" + + cp build/coreboot.rom qemu_q35_${FW_VERSION}.rom + if [ $? -eq 0 ]; then +@@ -389,10 +396,13 @@ case "$CMD" in + build_optiplex_9010 "configs/config.dell_optiplex_9010_sff_txt" + ;; + "qemu" | "QEMU" | "q35" | "Q35" ) +- build_qemu ++ build_qemu "uefi" + ;; + "qemu_full" | "QEMU_full" | "q35_full" | "Q35_full" ) +- build_qemu "_all_menus" ++ build_qemu "uefi_all_menus" ++ ;; ++ "qemu_seabios" ) ++ build_qemu "smm_tseg_seabios" + ;; + "odroid_h4" | "odroid_H4" | "ODROID_H4" ) + BOARD="odroid_h4" +diff --git a/configs/config.emulation_qemu_x86_q35_smm_tseg_seabios b/configs/config.emulation_qemu_x86_q35_smm_tseg_seabios +new file mode 100644 +index 0000000000..37e4156d54 +--- /dev/null ++++ b/configs/config.emulation_qemu_x86_q35_smm_tseg_seabios +@@ -0,0 +1,30 @@ ++# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set ++# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set ++# CONFIG_IPXE_SERIAL_CONSOLE is not set ++CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y ++CONFIG_BUILD_IPXE=y ++CONFIG_CPU_QEMU_X86_TSEG_SMM=y ++CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y ++CONFIG_IPXE_ADD_SCRIPT=y ++CONFIG_IPXE_CUSTOM_BUILD_ID="12345678" ++CONFIG_IPXE_SCRIPT="payloads/external/iPXE/menu.ipxe" ++CONFIG_LOCALVERSION="v24.08.00.01" ++CONFIG_MEMTEST86PLUS_V5=y ++CONFIG_MEMTEST_SECONDARY_PAYLOAD=y ++CONFIG_OPTION_BACKEND_NONE=y ++CONFIG_FMDFILE="$(top)/src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" ++CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(CONFIG_MAINBOARD_DIR)/seabios_config" ++CONFIG_PXE=y ++CONFIG_PXE_ROM_ID="8086,157b" ++CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(CONFIG_MAINBOARD_DIR)/bootorder" ++CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y ++CONFIG_SEABIOS_DEBUG_LEVEL=0 ++CONFIG_SEABIOS_REVISION=y ++CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" ++CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y ++CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 ++CONFIG_SORTBOOTORDER_REVISION=y ++CONFIG_SORTBOOTORDER_REVISION_ID="95692853947e0b36e4d7fb57bf6a951baa9f78c5" ++CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y ++CONFIG_TPM2=y ++CONFIG_VENDOR_EMULATION=y +diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c +index 885240f8b1..b973f3d9b3 100644 +--- a/src/device/pciexp_device.c ++++ b/src/device/pciexp_device.c +@@ -700,7 +700,7 @@ static void pciexp_tune_dev(struct device *dev) + if (!root_cap) + return; + +- if (check_pciepm()) { ++ if (CONFIG(VENDOR_PCENGINES) && check_pciepm()) { + /* Check for and enable Common Clock */ + if (CONFIG(PCIEXP_COMMON_CLOCK)) + pciexp_enable_common_clock(root, root_cap, dev, cap); +diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c +index 1f33a612cd..51faeb65fe 100644 +--- a/src/drivers/uart/uart8250io.c ++++ b/src/drivers/uart/uart8250io.c +@@ -94,7 +94,7 @@ void uart_init(unsigned int idx) + unsigned int div; + div = uart_baudrate_divisor(get_uart_baudrate(), + uart_platform_refclk(), uart_input_clock_divider()); +- if (check_com2()) ++ if (CONFIG(VENDOR_PCENGINES) && check_com2()) + port_index = 1; + else + port_index = idx; +diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig +index 2fb180b7ec..424375e3af 100644 +--- a/src/mainboard/emulation/qemu-q35/Kconfig ++++ b/src/mainboard/emulation/qemu-q35/Kconfig +@@ -10,7 +10,7 @@ config BOARD_SPECIFIC_OPTIONS + select HAVE_OPTION_TABLE + # select HAVE_PIRQ_TABLE + select HAVE_ACPI_TABLES +- select BOARD_ROMSIZE_KB_16384 ++ select BOARD_ROMSIZE_KB_8192 + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_FORCE_NATIVE_VGA_INIT if !CHROMEOS + select MEMORY_MAPPED_TPM +diff --git a/src/mainboard/emulation/qemu-q35/board.fmd b/src/mainboard/emulation/qemu-q35/board.fmd +new file mode 100644 +index 0000000000..0f344e580c +--- /dev/null ++++ b/src/mainboard/emulation/qemu-q35/board.fmd +@@ -0,0 +1,18 @@ ++FLASH 8M { ++ SI_BIOS@0x0 0x800000 { ++ BOOTORDER(PRESERVE)@0x0 0x1000 ++ RW_VPD(PRESERVE)@0x1000 0x4000 ++ SMMSTORE(PRESERVE)@0x5000 0x20000 ++ RW_UNUSED@0x25000 0x1db000 ++ WP_RO@0x200000 0x600000{ ++ RO_VPD(PRESERVE)@0x0 0x4000 ++ RO_SECTION@0x4000 0x5fc000{ ++ FMAP@0x0 0x800 ++ RO_FRID@0x800 0x40 ++ RO_FRID_PAD@0x840 0x7c0 ++ GBB@0x1000 0x40000 ++ COREBOOT(CBFS)@0x41000 0x5bb000 ++ } ++ } ++ } ++} +diff --git a/src/mainboard/emulation/qemu-q35/boot-menu-key b/src/mainboard/emulation/qemu-q35/boot-menu-key +new file mode 100644 +index 0000000000000000000000000000000000000000..0ddf4f28e385d304edf8c8f82b4b59687420ba14 +GIT binary patch +literal 8 +KcmZ=^fB*mjC;&wO + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/emulation/qemu-q35/boot-menu-message b/src/mainboard/emulation/qemu-q35/boot-menu-message +new file mode 100644 +index 0000000000..2b61487904 +--- /dev/null ++++ b/src/mainboard/emulation/qemu-q35/boot-menu-message +@@ -0,0 +1 @@ ++Press F10 key now for boot menu, N for PXE boot +diff --git a/src/mainboard/emulation/qemu-q35/boot-menu-wait b/src/mainboard/emulation/qemu-q35/boot-menu-wait +new file mode 100644 +index 0000000000000000000000000000000000000000..b1dea8d7af3241677efd07b78cb866e0825e5291 +GIT binary patch +literal 8 +LcmXRAX8;2L1StTB + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/emulation/qemu-q35/bootorder b/src/mainboard/emulation/qemu-q35/bootorder +new file mode 100644 +index 0000000000000000000000000000000000000000..7e7e1b1a227ebaedc09bb74c05f3bc051d3b7b8f +GIT binary patch +literal 4096 +zcmeH?OK!s;5Qeix;ts5>q=1vYcHE@0VPcPB9s-gkx36r~Qlpw1@NEY8X66?>XjCZl +z`Ga3mucVmEp;3|&UQlgW9n0$UU$y0|Rc&OgY9nh^8(GJ4)~YtLR<)6}s^_dm$8p*BlADM(P=Xsw7bQwwZuy|`&_^@_sCNI#n|VulTe17k?&z%=z(sEp4|jNp-cl0o +z-~=T}dnYNmrXH5s#jNLh7qgL+z^HNQvq2-YUwXO-O0>7_^4fc!@-mpr(Ru@d67<$y +z1ts%9u)l{0H;8H0-(A+D@q-XTP_nC3DwRs5QmIrbmC7!UnAjO7U=F|}mObl%oy6xG +o>mL~so4gwsI_9H+IBRejBTSEZYGRV5fb2YVX=Dj>_Hjqa58`6o(EtDd + +literal 0 +HcmV?d00001 + +diff --git a/src/mainboard/emulation/qemu-q35/bootorder_def b/src/mainboard/emulation/qemu-q35/bootorder_def +new file mode 100644 +index 0000000000..774434f980 +--- /dev/null ++++ b/src/mainboard/emulation/qemu-q35/bootorder_def +@@ -0,0 +1,32 @@ ++/pci@i0cf8/usb@10/usb-*@1 ++/pci@i0cf8/usb@10/usb-*@2 ++/pci@i0cf8/usb@10/usb-*@3 ++/pci@i0cf8/usb@10/usb-*@4 ++/pci@i0cf8/usb@12/usb-*@1 ++/pci@i0cf8/usb@12/usb-*@2 ++/pci@i0cf8/usb@12/usb-*@3 ++/pci@i0cf8/usb@12/usb-*@4 ++/pci@i0cf8/usb@13/usb-*@1 ++/pci@i0cf8/usb@13/usb-*@2 ++/pci@i0cf8/usb@13/usb-*@3 ++/pci@i0cf8/usb@13/usb-*@4 ++/pci@i0cf8/*@14,7 ++/pci@i0cf8/*@11/drive@0/disk@0 ++/pci@i0cf8/*@11/drive@1/disk@0 ++/pci@i0cf8/pci-bridge@2,5/*@0/drive@0/disk@0 ++/pci@i0cf8/pci-bridge@2,5/*@0/drive@1/disk@0 ++/rom@genroms/pxe.rom ++pxen0 ++scon1 ++usben1 ++uartc1 ++uartd1 ++ehcien1 ++mpcie2_clk0 ++com2_en0 ++boosten1 ++sd3mode0 ++iommu0 ++pciepm0 ++pciereverse0 ++watchdog0000 +diff --git a/src/mainboard/emulation/qemu-q35/bootorder_map b/src/mainboard/emulation/qemu-q35/bootorder_map +new file mode 100644 +index 0000000000..f5d47e4ee4 +--- /dev/null ++++ b/src/mainboard/emulation/qemu-q35/bootorder_map +@@ -0,0 +1,18 @@ ++a USB ++a USB ++a USB ++a USB ++a USB ++a USB ++a USB ++a USB ++a USB ++a USB ++a USB ++a USB ++b SDCARD ++c mSATA ++d SATA ++e mPCIe1 SATA1 and SATA2 ++e mPCIe1 SATA1 and SATA2 ++f iPXE +diff --git a/src/mainboard/emulation/qemu-q35/seabios_config b/src/mainboard/emulation/qemu-q35/seabios_config +new file mode 100644 +index 0000000000..42b3c6bf03 +--- /dev/null ++++ b/src/mainboard/emulation/qemu-q35/seabios_config +@@ -0,0 +1,9 @@ ++CONFIG_ATA_DMA=y ++CONFIG_ATA_PIO32=y ++# CONFIG_BOOTSPLASH is not set ++# CONFIG_MEGASAS is not set ++# CONFIG_FLOPPY is not set ++# CONFIG_PS2PORT is not set ++# CONFIG_USB_UHCI is not set ++# CONFIG_USB_OHCI is not set ++# CONFIG_LPT is not set +-- +2.49.0 + diff --git a/patches/0085-libpayload-Make-builds-reproducible-by-using-ffile-p.patch b/patches/0085-libpayload-Make-builds-reproducible-by-using-ffile-p.patch new file mode 100644 index 0000000..6d58b95 --- /dev/null +++ b/patches/0085-libpayload-Make-builds-reproducible-by-using-ffile-p.patch @@ -0,0 +1,27 @@ +From ff51b25b17e7154750325fb0124569834ff38441 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= +Date: Thu, 29 May 2025 16:18:18 +0200 +Subject: [PATCH 85/88] libpayload: Make builds reproducible by using + -ffile-prefix-map + +Upstream-Status: Pending +Signed-off-by: Michał Żygowski +--- + payloads/libpayload/Makefile.mk | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/payloads/libpayload/Makefile.mk b/payloads/libpayload/Makefile.mk +index 6dd33e1197..0a41408238 100644 +--- a/payloads/libpayload/Makefile.mk ++++ b/payloads/libpayload/Makefile.mk +@@ -80,6 +80,7 @@ CFLAGS += -ffunction-sections -fdata-sections + CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wvla + CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough + CFLAGS += -Wstrict-aliasing -Wshadow -Werror ++CFLAGS += -ffile-prefix-map=$(coreboottop)=. + + ifeq ($(CONFIG_LP_LTO),y) + CFLAGS += -flto +-- +2.49.0 + diff --git a/patches/0086-add-dasharo-blobs-submodule.patch b/patches/0086-add-dasharo-blobs-submodule.patch new file mode 100644 index 0000000..3efba30 --- /dev/null +++ b/patches/0086-add-dasharo-blobs-submodule.patch @@ -0,0 +1,34 @@ +From bb3f5b3c60341c17cf75dd634799ca241ed97de1 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= +Date: Thu, 29 May 2025 16:18:18 +0200 +Subject: [PATCH 86/88] add dasharo-blobs submodule + +Upstream-Status: Inappropriate [Custom submodule] +Signed-off-by: Michał Żygowski +--- + .gitmodules | 3 +++ + 3rdparty/dasharo-blobs | 1 + + 2 files changed, 4 insertions(+) + create mode 160000 3rdparty/dasharo-blobs + +diff --git a/.gitmodules b/.gitmodules +index eec69fd1ec..0c8fc8917f 100644 +--- a/.gitmodules ++++ b/.gitmodules +@@ -65,3 +65,6 @@ + [submodule "src/vendorcode/amd/opensil/genoa_poc/opensil"] + path = src/vendorcode/amd/opensil/genoa_poc/opensil + url = https://review.coreboot.org/opensil_genoa_poc.git ++[submodule "3rdparty/dasharo-blobs"] ++ path = 3rdparty/dasharo-blobs ++ url = https://github.com/Dasharo/dasharo-blobs.git +diff --git a/3rdparty/dasharo-blobs b/3rdparty/dasharo-blobs +new file mode 160000 +index 0000000000..c4ecc9e3f4 +--- /dev/null ++++ b/3rdparty/dasharo-blobs +@@ -0,0 +1 @@ ++Subproject commit c4ecc9e3f4baf5cc4c68d07c84c23b6f673f90f9 +-- +2.49.0 + diff --git a/patches/0087-use-3rdparty-dasharo-blobs-dasharo-dasharo.ipxe.patch b/patches/0087-use-3rdparty-dasharo-blobs-dasharo-dasharo.ipxe.patch new file mode 100644 index 0000000..5bb3827 --- /dev/null +++ b/patches/0087-use-3rdparty-dasharo-blobs-dasharo-dasharo.ipxe.patch @@ -0,0 +1,85 @@ +From f935f4ea0669a2d4e746ae455f3ac8862bfef108 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= +Date: Thu, 29 May 2025 16:18:18 +0200 +Subject: [PATCH 87/88] use 3rdparty/dasharo-blobs/dasharo/dasharo.ipxe + + +Upstream-Status: Inappropriate [Custom submodule] +Signed-off-by: Michał Żygowski + +--- + configs/config.emulation_qemu_x86_q35_smm_tseg_seabios | 2 +- + configs/config.pcengines_seabios_apu2 | 2 +- + configs/config.pcengines_seabios_apu3 | 2 +- + configs/config.pcengines_seabios_apu4 | 2 +- + configs/config.pcengines_seabios_apu6 | 2 +- + 5 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/configs/config.emulation_qemu_x86_q35_smm_tseg_seabios b/configs/config.emulation_qemu_x86_q35_smm_tseg_seabios +index 37e4156d54..e8a35eb362 100644 +--- a/configs/config.emulation_qemu_x86_q35_smm_tseg_seabios ++++ b/configs/config.emulation_qemu_x86_q35_smm_tseg_seabios +@@ -7,7 +7,7 @@ CONFIG_CPU_QEMU_X86_TSEG_SMM=y + CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y + CONFIG_IPXE_ADD_SCRIPT=y + CONFIG_IPXE_CUSTOM_BUILD_ID="12345678" +-CONFIG_IPXE_SCRIPT="payloads/external/iPXE/menu.ipxe" ++CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" + CONFIG_LOCALVERSION="v24.08.00.01" + CONFIG_MEMTEST86PLUS_V5=y + CONFIG_MEMTEST_SECONDARY_PAYLOAD=y +diff --git a/configs/config.pcengines_seabios_apu2 b/configs/config.pcengines_seabios_apu2 +index 69eca3ee40..2d2f205416 100644 +--- a/configs/config.pcengines_seabios_apu2 ++++ b/configs/config.pcengines_seabios_apu2 +@@ -10,7 +10,7 @@ CONFIG_HUDSON_SATA_MODE=2 + CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 + CONFIG_IPXE_ADD_SCRIPT=y + CONFIG_IPXE_CUSTOM_BUILD_ID="12345678" +-CONFIG_IPXE_SCRIPT="payloads/external/iPXE/menu.ipxe" ++CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" + CONFIG_LOCALVERSION="v24.08.00.01" + CONFIG_MEMTEST86PLUS_V5=y + CONFIG_MEMTEST_SECONDARY_PAYLOAD=y +diff --git a/configs/config.pcengines_seabios_apu3 b/configs/config.pcengines_seabios_apu3 +index b9f7a009ef..54fc69a673 100644 +--- a/configs/config.pcengines_seabios_apu3 ++++ b/configs/config.pcengines_seabios_apu3 +@@ -11,7 +11,7 @@ CONFIG_HUDSON_SATA_MODE=2 + CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 + CONFIG_IPXE_ADD_SCRIPT=y + CONFIG_IPXE_CUSTOM_BUILD_ID="12345678" +-CONFIG_IPXE_SCRIPT="payloads/external/iPXE/menu.ipxe" ++CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" + CONFIG_LOCALVERSION="v24.08.00.01" + CONFIG_MEMTEST86PLUS_V5=y + CONFIG_MEMTEST_SECONDARY_PAYLOAD=y +diff --git a/configs/config.pcengines_seabios_apu4 b/configs/config.pcengines_seabios_apu4 +index c71e9826ee..b55a923ec2 100644 +--- a/configs/config.pcengines_seabios_apu4 ++++ b/configs/config.pcengines_seabios_apu4 +@@ -11,7 +11,7 @@ CONFIG_HUDSON_SATA_MODE=2 + CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 + CONFIG_IPXE_ADD_SCRIPT=y + CONFIG_IPXE_CUSTOM_BUILD_ID="12345678" +-CONFIG_IPXE_SCRIPT="payloads/external/iPXE/menu.ipxe" ++CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" + CONFIG_LOCALVERSION="v24.08.00.01" + CONFIG_MEMTEST86PLUS_V5=y + CONFIG_MEMTEST_SECONDARY_PAYLOAD=y +diff --git a/configs/config.pcengines_seabios_apu6 b/configs/config.pcengines_seabios_apu6 +index 764f24f198..d7055d40f8 100644 +--- a/configs/config.pcengines_seabios_apu6 ++++ b/configs/config.pcengines_seabios_apu6 +@@ -11,7 +11,7 @@ CONFIG_HUDSON_SATA_MODE=2 + CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 + CONFIG_IPXE_ADD_SCRIPT=y + CONFIG_IPXE_CUSTOM_BUILD_ID="12345678" +-CONFIG_IPXE_SCRIPT="payloads/external/iPXE/menu.ipxe" ++CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" + CONFIG_LOCALVERSION="v24.08.00.01" + CONFIG_MEMTEST86PLUS_V5=y + CONFIG_MEMTEST_SECONDARY_PAYLOAD=y +-- +2.49.0 + diff --git a/patches/0088-configs-config.pcengines_apu-Use-tagged-version-of-S.patch b/patches/0088-configs-config.pcengines_apu-Use-tagged-version-of-S.patch new file mode 100644 index 0000000..97dfbae --- /dev/null +++ b/patches/0088-configs-config.pcengines_apu-Use-tagged-version-of-S.patch @@ -0,0 +1,73 @@ +From c82656287c3615febc970118c9f13147ef122eb0 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= +Date: Fri, 30 May 2025 14:23:29 +0200 +Subject: [PATCH 88/88] configs/config.pcengines_apu: Use tagged version of + SeaBIOS +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Upstream-Status: Pending +Signed-off-by: Michał Żygowski +--- + configs/config.pcengines_seabios_apu2 | 2 +- + configs/config.pcengines_seabios_apu3 | 2 +- + configs/config.pcengines_seabios_apu4 | 2 +- + configs/config.pcengines_seabios_apu6 | 2 +- + 4 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/configs/config.pcengines_seabios_apu2 b/configs/config.pcengines_seabios_apu2 +index 2d2f205416..0a7025eec3 100644 +--- a/configs/config.pcengines_seabios_apu2 ++++ b/configs/config.pcengines_seabios_apu2 +@@ -23,7 +23,7 @@ CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(C + CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y + CONFIG_SEABIOS_DEBUG_LEVEL=0 + CONFIG_SEABIOS_REVISION=y +-CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" ++CONFIG_SEABIOS_REVISION_ID="rel-1.16.3.1" + CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 + CONFIG_SORTBOOTORDER_REVISION=y + CONFIG_SORTBOOTORDER_REVISION_ID="v24.08.00.01" +diff --git a/configs/config.pcengines_seabios_apu3 b/configs/config.pcengines_seabios_apu3 +index 54fc69a673..6cbe69da3b 100644 +--- a/configs/config.pcengines_seabios_apu3 ++++ b/configs/config.pcengines_seabios_apu3 +@@ -24,7 +24,7 @@ CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(C + CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y + CONFIG_SEABIOS_DEBUG_LEVEL=0 + CONFIG_SEABIOS_REVISION=y +-CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" ++CONFIG_SEABIOS_REVISION_ID="rel-1.16.3.1" + CONFIG_SORTBOOTORDER_REVISION=y + CONFIG_SORTBOOTORDER_REVISION_ID="v24.08.00.01" + CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y +diff --git a/configs/config.pcengines_seabios_apu4 b/configs/config.pcengines_seabios_apu4 +index b55a923ec2..1ab04f462f 100644 +--- a/configs/config.pcengines_seabios_apu4 ++++ b/configs/config.pcengines_seabios_apu4 +@@ -24,7 +24,7 @@ CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(C + CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y + CONFIG_SEABIOS_DEBUG_LEVEL=0 + CONFIG_SEABIOS_REVISION=y +-CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" ++CONFIG_SEABIOS_REVISION_ID="rel-1.16.3.1" + CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 + CONFIG_SORTBOOTORDER_REVISION=y + CONFIG_SORTBOOTORDER_REVISION_ID="v24.08.00.01" +diff --git a/configs/config.pcengines_seabios_apu6 b/configs/config.pcengines_seabios_apu6 +index d7055d40f8..ce2ff11d7a 100644 +--- a/configs/config.pcengines_seabios_apu6 ++++ b/configs/config.pcengines_seabios_apu6 +@@ -24,7 +24,7 @@ CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(C + CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y + CONFIG_SEABIOS_DEBUG_LEVEL=0 + CONFIG_SEABIOS_REVISION=y +-CONFIG_SEABIOS_REVISION_ID="ac9eb800566194692fa094375703359dc66b1491" ++CONFIG_SEABIOS_REVISION_ID="rel-1.16.3.1" + CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8 + CONFIG_SORTBOOTORDER_REVISION=y + CONFIG_SORTBOOTORDER_REVISION_ID="v24.08.00.01" +-- +2.49.0 + diff --git a/patches/add-memtestv5-to-apu3-and-apu5-configs.patch b/patches/add-memtestv5-to-apu3-and-apu5-configs.patch deleted file mode 100644 index 15a42b8..0000000 --- a/patches/add-memtestv5-to-apu3-and-apu5-configs.patch +++ /dev/null @@ -1,28 +0,0 @@ -configs: add memtest v5 as payload for apu3 and apu5 builds - -Signed-off-by: Piotr Król - -diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3 -index e4bc9914a1c7..89e4d995bd71 100644 ---- a/configs/config.pcengines_apu3 -+++ b/configs/config.pcengines_apu3 -@@ -4,6 +4,7 @@ CONFIG_APU2_PINMUX_UART_C=y - CONFIG_APU2_PINMUX_UART_D=y - CONFIG_BOARD_PCENGINES_APU3=y - CONFIG_BUILD_IPXE=y -+CONFIG_MEMTEST86PLUS_V5=y - CONFIG_MEMTEST_SECONDARY_PAYLOAD=y - CONFIG_NO_GFX_INIT=y - CONFIG_PXE=y -diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5 -index 7f405bc6900b..7e7f6558f643 100644 ---- a/configs/config.pcengines_apu5 -+++ b/configs/config.pcengines_apu5 -@@ -4,6 +4,7 @@ CONFIG_APU2_PINMUX_UART_C=y - CONFIG_APU2_PINMUX_UART_D=y - CONFIG_BOARD_PCENGINES_APU5=y - CONFIG_BUILD_IPXE=y -+CONFIG_MEMTEST86PLUS_V5=y - CONFIG_MEMTEST_SECONDARY_PAYLOAD=y - CONFIG_NO_GFX_INIT=y - CONFIG_PXE=y diff --git a/patches/gitignore-add-memstest86plus_v5-and-sortbootorder-payloads.patch b/patches/gitignore-add-memstest86plus_v5-and-sortbootorder-payloads.patch deleted file mode 100644 index dd8dacc..0000000 --- a/patches/gitignore-add-memstest86plus_v5-and-sortbootorder-payloads.patch +++ /dev/null @@ -1,19 +0,0 @@ -gitignore: add memtest86plu_v5 and sortbootorder payloads - -Signed-off-by: Piotr Król - -diff --git a/.gitignore b/.gitignore -index e813493526f3..40f0f7cd78bb 100644 ---- a/.gitignore -+++ b/.gitignore -@@ -29,6 +29,10 @@ site-local - .test - .dependencies - -+# payloads -+payloads/external/Memtest86Plus/memtest86plus_v5/ -+payloads/external/sortbootorder/sortbootorder/ -+ - # Development friendly files - tags - .clang_complete diff --git a/patches/series b/patches/series index 1dbfca2..0ca1cac 100644 --- a/patches/series +++ b/patches/series @@ -1,86 +1,88 @@ -0001-payloads-ipxe-fix-compilation-issues-with-corebood-s.patch -0001-configs-remove-apu1-and-add-apu2-4.patch -0001-configs-sort-apu3-and-apu5-configs.patch -add-memtestv5-to-apu3-and-apu5-configs.patch -0002-payloads-seabios-use-PC-Engines-repository.patch -0003-payloads-add-support-for-sortbootorder.patch -0004-mainboard-pcengines-Add-support-for-bootorder-files-.patch -0005-configs-add-support-for-bootorder-files-for-PC-Engin.patch -0006-mainboard-pcengines-add-support-for-bios-knobs.patch -0007-drivers-spi-add-secure-registers-support-for-winbond.patch -0008-src-southbridge-amd-pi-hudson-add-necessary-files-an.patch -0009-src-southbridge-amd-pi-hudson-use-AMD-common-SPI-blo.patch -0010-mainboard-pcengines-add-support-for-getting-sku-and-.patch -0011-mainboard-pcengines-add-function-to-check-whether-CO.patch -0012-mainboard-pcengines-add-memory-configuration-and-sta.patch -0013-mainboard-pcengines-enable-power-on-after-power-fail.patch -0014-mainboard-pcengines-Enable-GENINTx-as-GPIO.patch -0015-payloads-iPXE-add-support-for-custom-iPXE-general.h-.patch -0016-payloads-iPXE-Update-Makefile.inc-to-change-PXE-ROM-.patch -0017-mainboard-pcengines-add-support-for-s1-button.patch -0018-mainboard-pcengines-add-apu3-and-apu5-variants.patch -0019-gitmodules-fix-the-URLs-for-stand-alone-build.patch -0020-mainboard-pcengines-force-GPP3-PCIe-CLK-based-on-Kon.patch -0021-mainboard-pcengines-use-check_ehci0-in-BiosCallOut.patch -0022-mainboard-pcengines-use-bios-knobs.patch -0023-payloads-SeaBIOS-provide-help-for-added-SeaBIOS-opti.patch -0024-mb-apu2-locate-the-bootorder-in-CBFS-and-read-it-fro.patch -0025-mb-pcengines-apu2-mainboard.c-do-not-proceed-with-en.patch -0026-mainboard-pcengines-Fix-ECC-exclusion-range-and-enab.patch -0027-src-cpu-add-option-to-include-raw-microcode-binary-t.patch -0028-src-mb-pcengines-apu-add-custom-SeaBIOS-config.patch -0029-nb-amd-pi-00730F01-Add-initial-native-IVRS-support.patch -0030-payloads-external-iPXE-menu.ipxe-enable-autoboot-for.patch -0031-src-mb-pcengines-apux-bootorder-prepare-bootorder-fi.patch -0032-src-drivers-uart-uart8250io.c-set-correct-serial-por.patch -0033-Makefile.inc-include-microcode-patch-inside-firmware.patch -0034-payloads-iPXE-option-for-reproducible-building.patch -0035-mainboard-pcengines-add-boost-knob-check.patch -0036-src-mainboard-pcengines-apu2-OemCustomize.c-make-boo.patch -0037-src-mainboard-pcengines-apu2-bootorder-add-boost-kno.patch -0038-src-northbridge-amd-pi-00730F01-pci_devs.h-add-IOMMU.patch -0039-src-mainboard-pcengines-apu2-acpi-superio.asl-descri.patch -0040-src-mainboard-pcengines-apu2-enable-SD-3.0-mode.patch -0041-src-mainboard-pcengines-apu2-bootorder-update-bootor.patch -0042-src-mainboard-pcengines-apu2-bootorder-unify-bootord.patch -0043-src-mainboard-pcengines-apu2-bootorder-add-watchdog-.patch -0044-src-vendorcode-amd-pi-Makefile.inc-strip-quotes-from.patch -0045-src-mainboard-pcengines-apu2-Kconfig-add-necessary-o.patch -0046-mb-pcengines-apu2-Avoid-pragma-pack-on-the-rest-of-t.patch -0047-src-mainboard-pcengines-apu2-BiosCallOuts.c-fix-SPD-.patch -0048-mainboard-pcengines-add-FMAP-descriptor-files.patch -0049-src-mainboard-pcengines-apu2-acpi-add-GPIOs-LEDS-and.patch -0050-mainboard-pcengines-add-IOMMU-status-to-bootorder_de.patch -0051-mainboard-apu2-fix-watchdog-issues.patch -0052-mainboard-pcengines-send-commands-to-the-LPC-MCU.patch -0053-src-northbridge-amd-pi-00730F01-acpi-northbridge.asl.patch -0054-src-southbridge-amd-pi-hudson-sd.c-move-SD-3.0-check.patch -0055-mainboard-pcengines-add-pciepm-runtime-option.patch -0056-src-device-pciexp_device.c-enable-PCIe-PM-feature-on.patch -0057-acpi-add-DRTM-table.patch -0058-src-commonlib-include-commonlib-cbmem_id.h-add-new-I.patch -0059-src-northbridge-amd-pi-00730F01-northbridge.c-genera.patch -0060-coreboot_table-include-DRTM-TPM-log-in-coreboot-tabl.patch -0061-src-commonlib-include-commonlib-tpm_log_serialized.h.patch -0062-util-cbmem-cbmem.c-implement-DRTM-TPM-log-parser.patch -0063-mainboard-pcengines-apu2-Add-reversed-PCI-address-or.patch -0064-src-mainboard-pcengines-apu2-fix-TPM-visibility-in-O.patch -0065-src-mainboard-pcengines-apu2-add-apu6-variant.patch -0066-pcengines-apu2-OemCustomize.c-Add-specific-PCIe-orde.patch -0067-mainboard-pcengines-Update-GPIO-configuration-and-re.patch -0068-payloads-external-SeaBIOS-add-bootorder-in-FMAP-opti.patch -0069-mainboard-pcengines-Add-support-for-sercon-port.patch -0070-mainboard-pcengines-Use-FMAP-layout.patch -0071-mainboard-pcengines-avoid-ASSERT-on-the-stack-overwr.patch -0072-amdblocks-psp_efs.h-allow-for-PI-00730F01-platforms.patch -0073-pcengines-apu2-enable-EHCI-controller-by-default.patch -0074-nb-amd-enable-ProcessorScopeInSb-for-fam14-and-00730.patch -0075-src-northbridge-amd-pi-00730F01-northbridge.c-enable.patch -0076-payloads-external-SeaBIOS-add-bootorder-in-FMAP-opti.patch -0077-mb-pcengines-apu2-add-variant-apu7.patch -0078-mainboard-pcengines-fix-sign-of-life-coreboot-build-.patch -0079-mainboard-pcengines-make-HUDSON_LEGACY_FREE-n-by-def.patch -0080-src-southbridge-amd-pi-hudson-Makefile.inc-fix-AMDFW.patch -0001-configs-move-apu-2-3-4-6-configs-to-seabios_apu-2-3-.patch -makefile.mk-if-in-git-repository-use-git-describe-for-kernelversion.patch -gitignore-add-memstest86plus_v5-and-sortbootorder-payloads.patch +0001-payloads-ipxe-bump-iPXE-to-2024.08.patch +0002-configs-add-pcengines_seabios_apu-2-4.patch +0003-configs-add-pcengines_seabios_apu3.patch +0004-build.sh-dummy-patch-from-26ab7d99e984e662f6ed8ba2c0.patch +0005-build.sh-add-support-for-uefi-seabios-_apuX-builds.patch +0006-payloads-seabios-use-PC-Engines-repository.patch +0007-payloads-add-support-for-sortbootorder.patch +0008-mainboard-pcengines-Add-support-for-bootorder-files-.patch +0009-configs-add-support-for-bootorder-files-for-PC-Engin.patch +0010-mainboard-pcengines-add-support-for-bios-knobs.patch +0011-drivers-spi-add-secure-registers-support-for-winbond.patch +0012-src-southbridge-amd-pi-hudson-add-necessary-files-an.patch +0013-src-southbridge-amd-pi-hudson-use-AMD-common-SPI-blo.patch +0014-mainboard-pcengines-add-support-for-getting-sku-and-.patch +0015-mainboard-pcengines-add-function-to-check-whether-CO.patch +0016-mainboard-pcengines-add-memory-configuration-and-sta.patch +0017-mainboard-pcengines-enable-power-on-after-power-fail.patch +0018-mainboard-pcengines-Enable-GENINTx-as-GPIO.patch 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