diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 879ca4893c1..2ba4c1a12a1 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -151,7 +151,7 @@ jobs:
     strategy:
       matrix:
         vendor: [ protectli ]
-        model: [ vp66xx, vp46xx, vp32xx, vp2430, vp2420, vp2410, V1210, V1211, V1410, V1610 ]
+        model: [ vp66xx, vp46xx, vp32xx, vp2440, vp2430, vp2420, vp2410, V1210, V1211, V1410, V1610 ]
     steps:
       - name: Checkout repository
         uses: actions/checkout@v4
@@ -312,6 +312,20 @@ jobs:
       matrix:
         vendor: [ protectli ]
         model: [ vp2430 ]
+  deploy_protectli_vp2440:
+    if: startsWith(github.ref, 'refs/tags/protectli_vp2440_')
+    needs: build_protectli
+    uses: ./.github/workflows/deploy-template.yml
+    with:
+      platform: protectli
+      vendor: ${{ matrix.vendor }}
+      model: ${{ matrix.model }}
+      artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}"
+    secrets: inherit
+    strategy:
+      matrix:
+        vendor: [ protectli ]
+        model: [ vp2440 ]
   deploy_protectli_jsl:
     if: startsWith(github.ref, 'refs/tags/protectli_vault_jsl')
     needs: build_protectli
diff --git a/3rdparty/dasharo-blobs b/3rdparty/dasharo-blobs
index 79be2c819f6..88ba865d780 160000
--- a/3rdparty/dasharo-blobs
+++ b/3rdparty/dasharo-blobs
@@ -1 +1 @@
-Subproject commit 79be2c819f6578ff0287cc99bfa2b115443bc624
+Subproject commit 88ba865d780b4590092d6ea88ed7dd944d579110
diff --git a/build.sh b/build.sh
index d245ce2b6df..c5466ab5b7e 100755
--- a/build.sh
+++ b/build.sh
@@ -12,6 +12,7 @@ usage() {
   echo -e "\tvp66xx                 - build Dasharo for Protectli VP66xx"
   echo -e "\tvp46xx                 - build Dasharo for Protectli VP46xx"
   echo -e "\tvp32xx                 - build Dasharo for Protectli VP32xx"
+  echo -e "\tvp2440                 - build Dasharo for Protectli VP2440"
   echo -e "\tvp2430                 - build Dasharo for Protectli VP2430"
   echo -e "\tvp2420                 - build Dasharo for Protectli VP2420"
   echo -e "\tvp2410                 - build Dasharo for Protectli VP2410"
@@ -426,6 +427,10 @@ case "$CMD" in
         BOARD="vp2430"
         build_protectli_vault
         ;;
+    "vp2440" | "VP2440")
+        BOARD="vp2440"
+        build_protectli_vault
+        ;;
     "v1210" | "V1210" )
         build_v1x10 "v1210"
         ;;
diff --git a/configs/config.protectli_vp2440 b/configs/config.protectli_vp2440
new file mode 100644
index 00000000000..f209471a502
--- /dev/null
+++ b/configs/config.protectli_vp2440
@@ -0,0 +1,61 @@
+CONFIG_LOCALVERSION="v0.9.0-rc1"
+CONFIG_OPTION_BACKEND_NONE=y
+CONFIG_VENDOR_PROTECTLI=y
+CONFIG_VBOOT=y
+CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/vp2440/descriptor.bin"
+CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/vp2440/me.bin"
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000
+CONFIG_EDK2_BOOT_TIMEOUT=6
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_BOARD_PROTECTLI_VP2440=y
+CONFIG_EDK2_BOOTSPLASH_FILE="$(top)/3rdparty/dasharo-blobs/protectli/black_background.bmp"
+CONFIG_TPM_MEASURED_BOOT=y
+CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
+CONFIG_HAVE_ME_BIN=y
+CONFIG_INTEL_ME_DISABLED_HECI=y
+# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set
+CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y
+CONFIG_DRIVERS_EFI_VARIABLE_STORE=y
+CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y
+CONFIG_DRIVERS_GENERIC_CBFS_UUID=y
+CONFIG_TPM2=y
+CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y
+CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y
+CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y
+CONFIG_BOOTMEDIA_SMM_BWP=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
+# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set
+# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set
+CONFIG_PAYLOAD_EDK2=y
+CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2"
+CONFIG_EDK2_TAG_OR_REV="c2de870a67b7c422bb5344ee0389723c1e6aa7af"
+CONFIG_EDK2_USE_EDK2_PLATFORMS=y
+CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms"
+CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf"
+CONFIG_EDK2_CBMEM_LOGGING=y
+CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
+# CONFIG_EDK2_PRIORITIZE_INTERNAL is not set
+# CONFIG_EDK2_PS2_SUPPORT is not set
+CONFIG_EDK2_SERIAL_SUPPORT=y
+CONFIG_BUILD_IPXE=y
+CONFIG_IPXE_NO_PROMPT=y
+CONFIG_IPXE_ADD_SCRIPT=y
+CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe"
+CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789"
+CONFIG_EDK2_ENABLE_IPXE=y
+CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities"
+# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set
+CONFIG_EDK2_SETUP_PASSWORD=y
+CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y
+CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y
+CONFIG_EDK2_DASHARO_USB_CONFIG=y
+CONFIG_EDK2_DASHARO_POWER_CONFIG=y
+CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y
+CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y
+CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y
+CONFIG_EDK2_HAVE_2ND_UART=y
+CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION2_DEFAULT_ENABLE=y
+CONFIG_EDK2_BOOT_MENU_KEY=0x0015
+CONFIG_EDK2_SETUP_MENU_KEY=0x0008
+CONFIG_EDK2_DISABLE_OPTION_ROMS=y
+CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y
diff --git a/src/mainboard/protectli/vault_adl_n/Kconfig b/src/mainboard/protectli/vault_adl_n/Kconfig
index 6b9e136d00a..3af0fc0b06a 100644
--- a/src/mainboard/protectli/vault_adl_n/Kconfig
+++ b/src/mainboard/protectli/vault_adl_n/Kconfig
@@ -1,4 +1,4 @@
-if BOARD_PROTECTLI_VP32XX || BOARD_PROTECTLI_VP2430
+if BOARD_PROTECTLI_VP32XX || BOARD_PROTECTLI_VP2430 || BOARD_PROTECTLI_VP2440
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
@@ -23,10 +23,12 @@ config MAINBOARD_DIR
 config MAINBOARD_PART_NUMBER
 	default "VP32XX" if BOARD_PROTECTLI_VP32XX
 	default "VP2430" if BOARD_PROTECTLI_VP2430
+	default "VP2440" if BOARD_PROTECTLI_VP2440
 
 config VARIANT_DIR
 	default "vp32xx" if BOARD_PROTECTLI_VP32XX
 	default "vp2430" if BOARD_PROTECTLI_VP2430
+	default "vp2440" if BOARD_PROTECTLI_VP2440
 
 config MAINBOARD_VENDOR
 	default "Protectli"
diff --git a/src/mainboard/protectli/vault_adl_n/Kconfig.name b/src/mainboard/protectli/vault_adl_n/Kconfig.name
index 8008ec2b243..1d2bccacaae 100644
--- a/src/mainboard/protectli/vault_adl_n/Kconfig.name
+++ b/src/mainboard/protectli/vault_adl_n/Kconfig.name
@@ -3,3 +3,6 @@ config BOARD_PROTECTLI_VP32XX
 
 config BOARD_PROTECTLI_VP2430
 	bool "VP2430"
+
+config BOARD_PROTECTLI_VP2440
+	bool "VP2440"
diff --git a/src/mainboard/protectli/vault_adl_n/acpi/usb_pd.asl b/src/mainboard/protectli/vault_adl_n/acpi/usb_pd.asl
index 1b24c19bd53..8da6a5e6df0 100644
--- a/src/mainboard/protectli/vault_adl_n/acpi/usb_pd.asl
+++ b/src/mainboard/protectli/vault_adl_n/acpi/usb_pd.asl
@@ -15,6 +15,8 @@ Scope (\_SB.PCI0.I2C4)
 			I2cSerialBusV2 (0x0023, ControllerInitiated, 0x00061A80,
 					AddressingMode7Bit, "\\_SB.PCI0.I2C4",
 					0x00, ResourceConsumer, , Exclusive, )
+/* Only one port on VP2440 */
+#if !CONFIG(BOARD_PROTECTLI_VP2440)
 			I2cSerialBusV2 (0x0027, ControllerInitiated, 0x00061A80,
 					AddressingMode7Bit, "\\_SB.PCI0.I2C4",
 					0x00, ResourceConsumer, , Exclusive)
@@ -22,6 +24,7 @@ Scope (\_SB.PCI0.I2C4)
 			{
 				GPP_F13_IRQ
 			}
+#endif
 			/* Linux driver expects one interrupt resource per one I2C dev */
 			Interrupt (ResourceConsumer, Level, ActiveLow)
 			{
diff --git a/src/mainboard/protectli/vault_adl_n/devicetree.cb b/src/mainboard/protectli/vault_adl_n/devicetree.cb
index 85bd98632fd..d60eeca692c 100644
--- a/src/mainboard/protectli/vault_adl_n/devicetree.cb
+++ b/src/mainboard/protectli/vault_adl_n/devicetree.cb
@@ -144,6 +144,11 @@ chip soc/intel/alderlake
 						register "type" = "UPC_TYPE_INTERNAL"
 						device ref usb2_port8 on end
 					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 LTE/5G (KEY_B_5G)""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb3_port2 on end
+					end
 				end
 			end
 		end
@@ -228,11 +233,6 @@ chip soc/intel/alderlake
 						use tcss_usb3_port1 as usb3_port
 						device generic 0 alias conn0 on end
 					end
-					chip drivers/intel/pmc_mux/conn
-						use usb2_port6 as usb2_port
-						use tcss_usb3_port2 as usb3_port
-						device generic 1 alias conn1 on end
-					end
 				end
 			end
 		end
diff --git a/src/mainboard/protectli/vault_adl_n/mainboard.c b/src/mainboard/protectli/vault_adl_n/mainboard.c
index 5c1e9e3efae..daa53f285e3 100644
--- a/src/mainboard/protectli/vault_adl_n/mainboard.c
+++ b/src/mainboard/protectli/vault_adl_n/mainboard.c
@@ -14,9 +14,11 @@
 
 const char *smbios_mainboard_product_name(void)
 {
-	if (CONFIG(BOARD_PROTECTLI_VP2430)) {
+	if (CONFIG(BOARD_PROTECTLI_VP2430))
 		return "VP2430";
-	}
+
+	if (CONFIG(BOARD_PROTECTLI_VP2440))
+		return "VP2440";
 
 	u32 tmp[13];
 	const char *str = "Unknown Processor Name";
@@ -71,24 +73,49 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 		params->PcieRpEnableCpm[9] = 1;
 	}
 
+	if (CONFIG(BOARD_PROTECTLI_VP2440)) {
+		/*
+		 * All PCIe ports have an exclusive CLKREQ.
+		 */
+		params->PcieRpEnableCpm[0] = 1;
+		params->PcieRpEnableCpm[6] = 1;
+		params->PcieRpEnableCpm[8] = 1;
+		/*
+		 * Some WiFi cards do not get detected if CPM is enabled.
+		 * params->PcieRpEnableCpm[10] = 1;
+		 */
+		params->PcieRpEnableCpm[11] = 1;
+	}
+
 	// Enable port reset message on Type-C ports
 	params->PortResetMessageEnable[4] = 1;
 	params->PortResetMessageEnable[5] = 1;
 
 	/*
-	 * Configure AUX bias pads in FPS-S, becuase coreboot would do it too
+	 * Configure AUX bias pads in FPS-S, because coreboot would do it too
 	 * late and cause the Type-C displays to not work.
 	 */
 	params->IomTypeCPortPadCfg[0] = 0x09020016; // GPP_A22
 	params->IomTypeCPortPadCfg[1] = 0x09020015; // GPP_A21
-	params->IomTypeCPortPadCfg[2] = 0x0902000F; // GPP_A15
-	params->IomTypeCPortPadCfg[3] = 0x0902000E; // GPP_A14
+	if (!CONFIG(BOARD_PROTECTLI_VP2440)) {
+		params->IomTypeCPortPadCfg[2] = 0x0902000F; // GPP_A15
+		params->IomTypeCPortPadCfg[3] = 0x0902000E; // GPP_A14
+	}
 
 	// PMC-PD controller
 	params->PmcPdEnable = 1;
 
 	// IOM USB config
 	params->PchUsbOverCurrentEnable = 0;
+
+	if (CONFIG(BOARD_PROTECTLI_VP2440)) {
+		/*
+		 * Second Type-C port used as regular USB3.x for LTE.
+		 * Remap it to PCH xHCI first port.
+		 */
+		params->EnableTcssCovTypeA[1] = 1;
+		params->MappingPchXhciUsbA[1] = 1;
+	}
 }
 
 static void mainboard_final(void *chip_info)
diff --git a/src/mainboard/protectli/vault_adl_n/variants/vp2430/overridetree.cb b/src/mainboard/protectli/vault_adl_n/variants/vp2430/overridetree.cb
index c9ad4c96bbb..ec883940e4f 100644
--- a/src/mainboard/protectli/vault_adl_n/variants/vp2430/overridetree.cb
+++ b/src/mainboard/protectli/vault_adl_n/variants/vp2430/overridetree.cb
@@ -62,5 +62,17 @@ chip soc/intel/alderlake
 				device generic 0 on end
 			end
 		end
+
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port6 as usb2_port
+						use tcss_usb3_port2 as usb3_port
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end
 	end
 end
diff --git a/src/mainboard/protectli/vault_adl_n/variants/vp2440/gpio.c b/src/mainboard/protectli/vault_adl_n/variants/vp2440/gpio.c
new file mode 100644
index 00000000000..3ef8448f575
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_n/variants/vp2440/gpio.c
@@ -0,0 +1,806 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <gpio.h>
+#include <variant/gpio.h>
+
+#ifndef PAD_CFG_GPIO_BIDIRECT
+#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own)	\
+	_PAD_CFG_STRUCT(pad,										\
+		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) |		\
+		PAD_BUF(NO_DISABLE) | val,								\
+		PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
+#endif
+
+/* Pad configuration was generated automatically using intelp2m utility */
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Community 0 ------- */
+	/* ------- GPIO Group GPP_B ------- */
+	/* GPP_B0 - CORE_VID0 */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+
+	/* GPP_B1 - CORE_VID1 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+
+	/* GPP_B2 - VRALERT# */
+	PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
+
+	/* GPP_B3 - GPIO */
+	PAD_NC(GPP_B3, NONE),
+
+	/* GPP_B4 - GPIO */
+	PAD_NC(GPP_B4, NONE),
+
+	/* GPP_B5 - GPIO */
+	PAD_NC(GPP_B5, NONE),
+
+	/* GPP_B6 - GPIO */
+	PAD_NC(GPP_B6, NONE),
+
+	/* GPP_B7 - GPIO */
+	PAD_NC(GPP_B7, NONE),
+
+	/* GPP_B8 - GPIO */
+	PAD_NC(GPP_B8, NONE),
+
+	/* GPP_B9 - GPIO */
+	PAD_NC(GPP_B9, NONE),
+
+	/* GPP_B10 - GPIO */
+	PAD_NC(GPP_B10, NONE),
+
+	/* GPP_B11 - PMCALERT# */
+	PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1),
+
+	/* GPP_B12 - SLP_S0# */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+
+	/* GPP_B13 - PLTRST# */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+
+	/* GPP_B14 - SPKR */
+	PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1),
+
+	/* GPP_B15 - GPIO */
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	/* GPP_B18 - GPIO */
+	PAD_CFG_GPO(GPP_B18, 0, DEEP),
+
+	/* GPP_B19 - GPIO */
+	PAD_NC(GPP_B19, NONE),
+
+	/* GPP_B20 - GPIO */
+	PAD_NC(GPP_B20, NONE),
+
+	/* GPP_B21 - GPIO */
+	PAD_NC(GPP_B21, NONE),
+
+	/* GPP_B22 - GPIO */
+	PAD_NC(GPP_B22, NONE),
+
+	/* GPP_B23 - GPIO */
+	PAD_CFG_GPO(GPP_B23, 0, DEEP),
+
+	/* GPP_B24 - GSPI0_CLK_LOOPBK */
+	PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1),
+
+	/* GPP_B25 - GSPI1_CLK_LOOPBK */
+	PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1),
+
+	/* ------- GPIO Group GPP_A ------- */
+	/* GPP_A0 - ESPI_IO0 */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
+
+	/* GPP_A1 - ESPI_IO1 */
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
+
+	/* GPP_A2 - ESPI_IO2 */
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
+
+	/* GPP_A3 - ESPI_IO3 */
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
+
+	/* GPP_A4 - ESPI_CS0# */
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
+
+	/* GPP_A5 - ESPI_ALERT0# */
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
+
+	/* GPP_A6 - GPIO */
+	PAD_NC(GPP_A6, NONE),
+
+	/* GPP_A7 - GPIO */
+	PAD_NC(GPP_A7, NONE),
+
+	/* GPP_A8 - GPIO */
+	PAD_NC(GPP_A8, NONE),
+
+	/* GPP_A9 - ESPI_CLK */
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+
+	/* GPP_A10 - ESPI_RESET# */
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
+
+	/* GPP_A11 - GPIO */
+	PAD_NC(GPP_A11, NONE),
+
+	/* GPP_A12 - SATAXPCIE1 */
+	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
+
+	/* GPP_A13 - GPIO */
+	PAD_NC(GPP_A13, NONE),
+
+	/* GPP_A14 - GPIO */
+	PAD_NC(GPP_A14, NONE),
+
+	/* GPP_A15 - GPIO */
+	PAD_NC(GPP_A15, NONE),
+
+	/* GPP_A16 - USB_OC3# */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+
+	/* GPP_A17 - GPIO */
+	PAD_CFG_GPO(GPP_A17, 1, PLTRST),
+
+	/* GPP_A18 - DDSP_HPDB */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+
+	/* GPP_A19 - DDSP_HPD1 */
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
+
+	/* GPP_A20 - DDSP_HPD2 */
+	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
+
+	/* GPP_A21 - USB_C_GPP_A21 */
+	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6),
+
+	/* GPP_A22 - USB_C_GPP_A22 */
+	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6),
+
+	/* GPP_A23 - ESPI_CS1# */
+	PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1),
+
+	/* GPP_ESPI_CLK_LOOPBK - GPP_ESPI_CLK_LOOPBK */
+	PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1),
+
+	/* ------- GPIO Community 1 ------- */
+	/* ------- GPIO Group GPP_S ------- */
+	/* GPP_S0 - GPIO */
+	PAD_NC(GPP_S0, NONE),
+
+	/* GPP_S1 - GPIO */
+	PAD_NC(GPP_S1, NONE),
+
+	/* GPP_S2 - GPIO */
+	PAD_NC(GPP_S2, NONE),
+
+	/* GPP_S3 - GPIO */
+	PAD_NC(GPP_S3, NONE),
+
+	/* GPP_S4 - GPIO */
+	PAD_NC(GPP_S4, NONE),
+
+	/* GPP_S5 - GPIO */
+	PAD_NC(GPP_S5, NONE),
+
+	/* GPP_S6 - GPIO */
+	PAD_NC(GPP_S6, NONE),
+
+	/* GPP_S7 - GPIO */
+	PAD_NC(GPP_S7, NONE),
+
+	/* ------- GPIO Group GPP_I ------- */
+	/* GPP_I0 - GPIO */
+	PAD_NC(GPP_I0, NONE),
+
+	/* GPP_I1 - GPIO */
+	PAD_NC(GPP_I1, NONE),
+
+	/* GPP_I2 - GPIO */
+	PAD_NC(GPP_I2, NONE),
+
+	/* GPP_I3 - GPIO */
+	PAD_NC(GPP_I3, NONE),
+
+	/* GPP_I4 - GPIO */
+	PAD_NC(GPP_I4, NONE),
+
+	/* GPP_I5 - GPIO */
+	PAD_NC(GPP_I5, NONE),
+
+	/* GPP_I6 - GPIO */
+	PAD_NC(GPP_I6, NONE),
+
+	/* GPP_I7 - EMMC_CMD */
+	PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
+
+	/* GPP_I8 - EMMC_DATA0 */
+	PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
+
+	/* GPP_I9 - EMMC_DATA1 */
+	PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
+
+	/* GPP_I10 - EMMC_DATA2 */
+	PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
+
+	/* GPP_I11 - EMMC_DATA3 */
+	PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1),
+
+	/* GPP_I12 - EMMC_DATA4 */
+	PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1),
+
+	/* GPP_I13 - EMMC_DATA5 */
+	PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1),
+
+	/* GPP_I14 - EMMC_DATA6 */
+	PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1),
+
+	/* GPP_I15 - EMMC_DATA7 */
+	PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1),
+
+	/* GPP_I16 - EMMC_RCLK */
+	PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1),
+
+	/* GPP_I17 - EMMC_CLK */
+	PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1),
+
+	/* GPP_I18 - EMMC_RESET# */
+	PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1),
+
+	/* GPP_I19 - GPIO */
+	PAD_NC(GPP_I19, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	/* GPP_H0 - GPIO */
+	PAD_CFG_GPO(GPP_H0, 0, DEEP),
+
+	/* GPP_H1 - GPIO */
+	PAD_CFG_GPO(GPP_H1, 0, DEEP),
+
+	/* GPP_H2 - GPIO */
+	PAD_CFG_GPO(GPP_H2, 0, DEEP),
+
+	/* GPP_H3 - GPIO */
+	PAD_NC(GPP_H3, NONE),
+
+	/* GPP_H4 - I2C0_SDA */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+
+	/* GPP_H5 - I2C0_SCL */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+
+	/* GPP_H6 - GPIO */
+	PAD_NC(GPP_H6, NONE),
+
+	/* GPP_H7 - GPIO */
+	PAD_NC(GPP_H7, NONE),
+
+	/* GPP_H8 - I2C4_SDA */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+
+	/* GPP_H9 - I2C4_SCL */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+
+	/* GPP_H10 - GPIO */
+	PAD_NC(GPP_H10, NONE),
+
+	/* GPP_H11 - GPIO */
+	PAD_NC(GPP_H11, NONE),
+
+	/* GPP_H12 - GPIO */
+	PAD_NC(GPP_H12, NONE),
+
+	/* GPP_H13 - GPIO */
+	PAD_NC(GPP_H13, NONE),
+
+	/* GPP_H14 - GPIO */
+	PAD_NC(GPP_H14, NONE),
+
+	/* GPP_H15 - DDPB_CTRLCLK */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+
+	/* GPP_H16 - GPIO */
+	PAD_NC(GPP_H16, NONE),
+
+	/* GPP_H17 - DDPB_CTRLDATA */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+
+	/* GPP_H18 - PROC_C10_GATE# */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+
+	/* GPP_H19 - SRCCLKREQ4# */
+	/*
+	 * Some WiFi cards do not get detected if CPM is enabled.
+	 * PAD_CFG_NF(GPP_H19, UP_20K, DEEP, NF1),
+	 */
+	PAD_NC(GPP_H19, NONE),
+
+	/* GPP_H20 - GPIO */
+	PAD_NC(GPP_H20, NONE),
+
+	/* GPP_H21 - GPIO */
+	PAD_NC(GPP_H21, NONE),
+
+	/* GPP_H22 - GPIO */
+	PAD_NC(GPP_H22, NONE),
+
+	/* GPP_H23 - GPIO */
+	PAD_NC(GPP_H23, NONE),
+
+	/* ------- GPIO Group GPP_D ------- */
+	/* GPP_D0 - GPIO */
+	PAD_NC(GPP_D0, NONE),
+
+	/* GPP_D1 - GPIO */
+	PAD_NC(GPP_D1, NONE),
+
+	/* GPP_D2 - GPIO */
+	PAD_NC(GPP_D2, NONE),
+
+	/* GPP_D3 - GPIO */
+	PAD_NC(GPP_D3, NONE),
+
+	/* GPP_D4 - GPIO */
+	PAD_NC(GPP_D4, NONE),
+
+	/* GPP_D5 - SRCCLKREQ0# */
+	PAD_CFG_NF(GPP_D5, UP_20K, DEEP, NF1),
+
+	/* GPP_D6 - SRCCLKREQ1# */
+	PAD_CFG_NF(GPP_D6, UP_20K, DEEP, NF1),
+
+	/* GPP_D7 - SRCCLKREQ2# */
+	PAD_CFG_NF(GPP_D7, UP_20K, DEEP, NF1),
+
+	/* GPP_D8 - SRCCLKREQ3# */
+	PAD_CFG_NF(GPP_D8, UP_20K, DEEP, NF1),
+
+	/* GPP_D9 - GPIO */
+	PAD_NC(GPP_D11, NONE),
+
+	/* GPP_D10 - GPIO */
+	PAD_NC(GPP_D10, NONE),
+
+	/* GPP_D11 - GPIO */
+	PAD_NC(GPP_D11, NONE),
+
+	/* GPP_D12 - GPIO */
+	PAD_NC(GPP_D12, NONE),
+
+	/* GPP_D13 - GPIO */
+	PAD_NC(GPP_D13, NONE),
+
+	/* GPP_D14 - GPIO */
+	PAD_NC(GPP_D14, NONE),
+
+	/* GPP_D15 - GPIO */
+	PAD_NC(GPP_D15, NONE),
+
+	/* GPP_D16 - GPIO */
+	PAD_NC(GPP_D16, NONE),
+
+	/* GPP_D17 - GPIO */
+	PAD_NC(GPP_D17, NONE),
+
+	/* GPP_D18 - GPIO */
+	PAD_NC(GPP_D18, NONE),
+
+	/* GPP_D19 - GPIO */
+	PAD_NC(GPP_D19, NONE),
+
+	/* GPP_GSPI2_CLK_LOOPBK - GPP_GSPI2_CLK_LOOPBK */
+	PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1),
+
+	/* ------- GPIO Group vGPIO ------- */
+	/* GPP_VGPIO_0 - GPIO */
+	PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP),
+
+	/* GPP_VGPIO_4 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI),
+
+	/* GPP_VGPIO_5 - GPIO */
+	PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI),
+
+	/* GPP_VGPIO_6 - GPP_VGPIO_6 */
+	PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_7 - GPP_VGPIO_7 */
+	PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_8 - GPP_VGPIO_8 */
+	PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_9 - GPP_VGPIO_9 */
+	PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_10 - GPP_VGPIO_10 */
+	PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_11 - GPP_VGPIO_11 */
+	PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_12 - GPP_VGPIO_12 */
+	PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_13 - GPP_VGPIO_13 */
+	PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_18 - GPP_VGPIO_18 */
+	PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_19 - GPP_VGPIO_19 */
+	PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_20 - GPP_VGPIO_20 */
+	PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_21 - GPP_VGPIO_21 */
+	PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_22 - GPP_VGPIO_22 */
+	PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_23 - GPP_VGPIO_23 */
+	PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_24 - GPP_VGPIO_24 */
+	PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_25 - GPP_VGPIO_25 */
+	PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_30 - GPP_VGPIO_30 */
+	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_31 - GPP_VGPIO_31 */
+	PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_32 - GPP_VGPIO_32 */
+	PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_33 - GPP_VGPIO_33 */
+	PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_34 - GPP_VGPIO_34 */
+	PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_35 - GPP_VGPIO_35 */
+	PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_36 - GPP_VGPIO_36 */
+	PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
+
+	/* GPP_VGPIO_37 - GPP_VGPIO_37 */
+	PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
+
+	/* ------- GPIO Community 2 ------- */
+	/* ------- GPIO Group GPP_GPD ------- */
+	/* GPD0 - BATLOW# */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
+
+	/* GPD1 - ACPRESENT */
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
+
+	/* GPD2 - LAN_WAKE# */
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),
+
+	/* GPD3 - PWRBTN# */
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+
+	/* GPD4 - SLP_S3# */
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+
+	/* GPD5 - SLP_S4# */
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+
+	/* GPD6 - SLP_A# */
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+
+	/* GPD7 - GPIO */
+	PAD_CFG_GPO(GPD7, 0, PWROK),
+
+	/* GPD8 - SUSCLK */
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+
+	/* GPD9 - GPIO */
+	PAD_CFG_GPO(GPD9, 0, PWROK),
+
+	/* GPD10 - SLP_S5# */
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+
+	/* GPD11 - GPIO */
+	PAD_CFG_GPO(GPD11, 0, PWROK),
+
+	/* GPD_INPUT3VSEL - GPD_INPUT3VSEL */
+	PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1),
+
+	/* GPD_SLP_LANB - GPD_SLP_LANB */
+	PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1),
+
+	/* GPD_SLP_SUSB - GPD_SLP_SUSB */
+	PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1),
+
+	/* GPD_WAKEB - GPD_WAKEB */
+	PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1),
+
+	/* GPD_DRAM_RESETB - GPD_DRAM_RESETB */
+	PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1),
+
+	/* ------- GPIO Community 4 ------- */
+	/* ------- GPIO Group GPP_C ------- */
+	/* GPP_C0 - SMBCLK */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+
+	/* GPP_C1 - SMBDATA */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+
+	/* GPP_C2 - GPIO */
+	PAD_CFG_GPO(GPP_C2, 0, DEEP),
+
+	/* GPP_C3 - SML0CLK */
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+
+	/* GPP_C4 - SML0DATA */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+
+	/* GPP_C5 - GPIO */
+	PAD_CFG_GPO(GPP_C5, 0, DEEP),
+
+	/* GPP_C6 - SML1CLK */
+	PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1),
+
+	/* GPP_C7 - SML1DATA */
+	PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1),
+
+	/* GPP_C8 - GPIO */
+	PAD_NC(GPP_C8, NONE),
+
+	/* GPP_C9 - GPIO */
+	PAD_NC(GPP_C9, NONE),
+
+	/* GPP_C10 - GPIO */
+	PAD_NC(GPP_C10, NONE),
+
+	/* GPP_C11 - GPIO */
+	PAD_NC(GPP_C11, NONE),
+
+	/* GPP_C12 - GPIO */
+	PAD_NC(GPP_C12, NONE),
+
+	/* GPP_C13 - GPIO */
+	PAD_NC(GPP_C13, NONE),
+
+	/* GPP_C14 - GPIO */
+	PAD_NC(GPP_C14, NONE),
+
+	/* GPP_C15 - GPIO */
+	PAD_NC(GPP_C15, NONE),
+
+	/* GPP_C16 - GPIO */
+	PAD_NC(GPP_C16, NONE),
+
+	/* GPP_C17 - GPIO */
+	PAD_NC(GPP_C17, NONE),
+
+	/* GPP_C18 - GPIO */
+	PAD_NC(GPP_C18, NONE),
+
+	/* GPP_C19 - GPIO */
+	PAD_NC(GPP_C19, NONE),
+
+	/* GPP_C20 - GPIO */
+	PAD_NC(GPP_C20, NONE),
+
+	/* GPP_C21 - GPIO */
+	PAD_NC(GPP_C21, NONE),
+
+	/* GPP_C22 - GPIO */
+	PAD_NC(GPP_C22, NONE),
+
+	/* GPP_C23 - GPIO */
+	PAD_NC(GPP_C23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+	/* GPP_F0 - CNV_BRI_DT */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+
+	/* GPP_F1 - CNV_BRI_RSP */
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
+
+	/* GPP_F2 - CNV_RGI_DT */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+
+	/* GPP_F3 - CNV_RGI_RSP */
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
+
+	/* GPP_F4 - CNV_RF_RESET# */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+
+	/* GPP_F5 - MODEM_CLKREQ */
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
+
+	/* GPP_F6 - GPIO */
+	PAD_NC(GPP_F6, NONE),
+
+	/* GPP_F7 - GPIO */
+	PAD_CFG_GPO(GPP_F7, 0, DEEP),
+
+	/* GPP_F8 - GPIO */
+	PAD_NC(GPP_F8, NONE),
+
+	/* GPP_F9 - GPIO */
+	PAD_NC(GPP_F9, NONE),
+
+	/* GPP_F10 - GPIO */
+	PAD_CFG_GPO(GPP_F10, 0, DEEP),
+
+	/* GPP_F11 - GPIO */
+	PAD_NC(GPP_F11, NONE),
+
+	/* GPP_F12 - GPIO */
+	PAD_NC(GPP_F12, NONE),
+
+	/* GPP_F13 - TYPE_C_PD_IRQ */
+	PAD_CFG_GPI_APIC_LOW(GPP_F13, NONE, PLTRST),
+
+	/* GPP_F14 - GPIO */
+	PAD_NC(GPP_F14, NONE),
+
+	/* GPP_F15 - GPIO */
+	PAD_NC(GPP_F15, NONE),
+
+	/* GPP_F16 - GPIO */
+	PAD_NC(GPP_F16, NONE),
+
+	/* GPP_F17 - GPIO */
+	PAD_NC(GPP_F17, NONE),
+
+	/* GPP_F18 - GPIO */
+	PAD_NC(GPP_F18, NONE),
+
+	/* GPP_F19 - GPIO */
+	PAD_NC(GPP_F19, NONE),
+
+	/* GPP_F20 - Reserved */
+	PAD_NC(GPP_F20, NONE),
+
+	/* GPP_F21 - Reserved */
+	PAD_NC(GPP_F21, NONE),
+
+	/* GPP_F22 - GPIO */
+	PAD_NC(GPP_F22, NONE),
+
+	/* GPP_F23 - GPIO */
+	PAD_NC(GPP_F23, NONE),
+
+	/* GPP_F_CLK_LOOPBK - GPIO */
+	PAD_NC(GPP_F_CLK_LOOPBK, NONE),
+
+	/* ------- GPIO Group GPP_HVCMOS ------- */
+	/* GPP_L_BKLTEN - n/a */
+	PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1),
+
+	/* GPP_L_BKLTCTL - n/a */
+	PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1),
+
+	/* GPP_L_VDDEN - n/a */
+	PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1),
+
+	/* GPP_SYS_PWROK - n/a */
+	PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1),
+
+	/* GPP_SYS_RESETB - n/a */
+	PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1),
+
+	/* GPP_MLK_RSTB - n/a */
+	PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1),
+
+	/* ------- GPIO Group GPP_E ------- */
+	/* GPP_E0 - GPIO */
+	PAD_NC(GPP_E0, NONE),
+
+	/* GPP_E1 - GPIO */
+	PAD_NC(GPP_E1, NONE),
+
+	/* GPP_E2 - GPIO */
+	PAD_NC(GPP_E2, NONE),
+
+	/* GPP_E3 - GPIO */
+	PAD_NC(GPP_E3, NONE),
+
+	/* GPP_E4 - GPIO */
+	PAD_NC(GPP_E4, NONE),
+
+	/* GPP_E5 - GPIO */
+	PAD_NC(GPP_E5, NONE),
+
+	/* GPP_E6 - GPIO */
+	PAD_CFG_GPO(GPP_E6, 0, DEEP),
+
+	/* GPP_E7 - GPIO */
+	PAD_NC(GPP_E7, NONE),
+
+	/* GPP_E8 - GPIO */
+	PAD_NC(GPP_E8, NONE),
+
+	/* GPP_E9 - GPIO */
+	PAD_NC(GPP_E9, NONE),
+
+	/* GPP_E10 - GPIO */
+	PAD_NC(GPP_E10, NONE),
+
+	/* GPP_E11 - GPIO */
+	PAD_NC(GPP_E11, NONE),
+
+	/* GPP_E12 - GPIO */
+	PAD_NC(GPP_E12, NONE),
+
+	/* GPP_E13 - GPIO */
+	PAD_CFG_GPI_APIC_LOW(GPP_E13, NONE, PLTRST),
+
+	/* GPP_E14 - DDSP_HPDA */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+
+	/* GPP_E15 - GPIO */
+	PAD_NC(GPP_E15, NONE),
+
+	/* GPP_E16 - GPIO */
+	PAD_NC(GPP_E16, NONE),
+
+	/* GPP_E17 - GPIO */
+	PAD_NC(GPP_E17, NONE),
+
+	/* GPP_E18 - GPIO */
+	PAD_NC(GPP_E18, NATIVE),
+
+	/* GPP_E19 - GPIO */
+	PAD_NC(GPP_E19, NATIVE),
+
+	/* GPP_E20 - GPIO */
+	PAD_NC(GPP_E20, NATIVE),
+
+	/* GPP_E21 - GPIO */
+	PAD_NC(GPP_E21, NATIVE),
+
+	/* GPP_E22 - DDPA_CTRLCLK */
+	PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1),
+
+	/* GPP_E23 - DDPA_CTRLDATA */
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
+
+	/* GPP_E_CLK_LOOPBK - GPIO */
+	PAD_NC(GPP_E_CLK_LOOPBK, NONE),
+
+	/* ------- GPIO Community 5 ------- */
+	/* ------- GPIO Group GPP_R ------- */
+	/* GPP_R0 - GPIO  */
+	PAD_NC(GPP_R0, NONE),
+
+	/* GPP_R1 - GPIO  */
+	PAD_NC(GPP_R1, NONE),
+
+	/* GPP_R2 - HDA_SDO */
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
+
+	/* GPP_R3 - GPIO  */
+	PAD_NC(GPP_R3, NONE),
+
+	/* GPP_R4 - GPIO  */
+	PAD_NC(GPP_R4, NONE),
+
+	/* GPP_R5 - GPIO */
+	PAD_NC(GPP_R5, NONE),
+
+	/* GPP_R6 - GPIO */
+	PAD_NC(GPP_R6, NONE),
+
+	/* GPP_R7 - GPIO */
+	PAD_NC(GPP_R7, NONE),
+};
+
+const struct pad_config *board_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
diff --git a/src/mainboard/protectli/vault_adl_n/variants/vp2440/overridetree.cb b/src/mainboard/protectli/vault_adl_n/variants/vp2440/overridetree.cb
new file mode 100644
index 00000000000..a017b497171
--- /dev/null
+++ b/src/mainboard/protectli/vault_adl_n/variants/vp2440/overridetree.cb
@@ -0,0 +1,102 @@
+chip soc/intel/alderlake
+	# FSP configuration
+
+	device domain 0 on
+		device ref igpu on
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_1] = DDI_ENABLE_HPD,
+			}"
+		end
+
+		device ref tcss_xhci on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					register "desc" = ""USB3 LTE/5G (KEY_B_5G)""
+					register "type" = "UPC_TYPE_INTERNAL"
+					register "use_custom_pld" = "false"
+					device ref tcss_usb3_port2 on end
+				end
+			end
+		end
+
+		device ref xhci on
+			register "usb2_ports[0]" = "USB2_PORT_EMPTY"
+			register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # 5G/LTE
+			register "usb3_ports[1]" = "USB3_PORT_EMPTY"
+
+			chip drivers/usb/acpi
+				device ref usb2_port1 off end
+			end
+			chip drivers/usb/acpi
+				register "desc" = ""USB2 5G (KEY_B_5G)""
+				register "type" = "UPC_TYPE_INTERNAL"
+				register "use_custom_pld" = "false"
+				device ref usb2_port6 on end
+			end
+		end
+
+		device ref sata on
+			register "sata_ports_enable[1]" = "1"
+		end
+
+		# X710 SFP 1x4
+		device ref pcie_rp1 on
+			register "pch_pcie_rp[PCH_RP(1)]" = "{
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.clk_src = 2,
+				.clk_req = 2,
+			}"
+		end
+
+		# LAN1
+		device ref pcie_rp7 on
+			register "pch_pcie_rp[PCH_RP(7)]" = "{
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.clk_src = 0,
+				.clk_req = 0,
+			}"
+		end
+
+		# PCIe Controller 3 is configured as 1x2,2x1 with lane reversal
+
+		# M.2 NVMe x2
+		device ref pcie_rp9 on
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.clk_src = 3,
+				.clk_req = 3,
+			}"
+			smbios_slot_desc	"SlotTypeM2Socket3" "SlotLengthOther"
+						"M.2/M 2280 (KEY_E_WIFI)" "SlotDataBusWidth2X"
+		end
+
+		# M.2 WIFI (uses CLKREQ4#, but some cards might not get detected)
+		device ref pcie_rp11 on
+			register "pch_pcie_rp[PCH_RP(11)]" = "{
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED,
+				.clk_src = 4,
+			}"
+			smbios_slot_desc	"SlotTypeM2Socket1_SD" "SlotLengthOther"
+						"M.2/M 2242 (KEY_E_WIFI)" "SlotDataBusWidth1X"
+		end
+
+		# LAN2
+		device ref pcie_rp12 on
+			register "pch_pcie_rp[PCH_RP(12)]" = "{
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.clk_src = 1,
+				.clk_req = 1,
+			}"
+		end
+
+		device ref cnvi_wifi on
+			register "cnvi_bt_core" = "true"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/protectli/vault_adl_n/variants/vp32xx/overridetree.cb b/src/mainboard/protectli/vault_adl_n/variants/vp32xx/overridetree.cb
index fedbf0d31eb..0dd025e31f3 100644
--- a/src/mainboard/protectli/vault_adl_n/variants/vp32xx/overridetree.cb
+++ b/src/mainboard/protectli/vault_adl_n/variants/vp32xx/overridetree.cb
@@ -69,5 +69,17 @@ chip soc/intel/alderlake
 				device pnp 2e.a off end	# CIR
 			end
 		end
+
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port6 as usb2_port
+						use tcss_usb3_port2 as usb3_port
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end
 	end
 end