FD VD geometries have overlaps between volTPCPlaneU/V and volTPCWireU/V...

[vpec0]

I have done ROOT's geometry overlap check on the wired versions of the gdmls of version v7 of FD VD geometries, e.g. gdml/dunevd10kt_3view_30deg_v7_refactored_2x8x40.gdml and there are overlaps between the volTPCPlaneU/V and volTPCWireU/V.... I have also checked v6 and these were present there too.

...
 = Overlap ov00565: volTPCPlaneV extruded by: volTPCPlaneV/volTPCWireV60_0 ovlp=0.00499358
 = Overlap ov00566: volTPCPlaneU extruded by: volTPCPlaneU/volTPCWireU60_0 ovlp=0.00499358
 = Overlap ov00567: volTPCPlaneV extruded by: volTPCPlaneV/volTPCWireV91_0 ovlp=0.00499358
 = Overlap ov00568: volTPCPlaneV extruded by: volTPCPlaneV/volTPCWireV222_0 ovlp=0.00499358
 = Overlap ov00569: volTPCPlaneU extruded by: volTPCPlaneU/volTPCWireU222_0 ovlp=0.00499358
 = Overlap ov00570: volTPCPlaneV extruded by: volTPCPlaneV/volTPCWireV208_0 ovlp=0.00499358
 = Overlap ov00571: volTPCPlaneU extruded by: volTPCPlaneU/volTPCWireU208_0 ovlp=0.00499358

This was spotted while reviewing PR #135.