Redundant Verilog Module Generation During Registration Phase #16
Description
Currently, during the registration phase, a separate Verilog module is generated for every instruction instance, even when multiple instances represent the same instruction. This leads to the creation of excessively large Verilog or VHDL source files.
While synthesis tools may optimize some of this redundancy during the implementation phase, the initial bloated source code can negatively impact readability, maintainability, and possibly synthesis performance.
A more efficient approach would be to generate a single reusable Verilog module for each unique instruction and instantiate it multiple times as needed. This change would significantly reduce the amount of generated source code and may also reduce the hardware resource usage of the resulting firmware.