diff --git a/ultrazed_7ev_som/1.4/board.xml b/ultrazed_7ev_som/1.4/board.xml
new file mode 100644
index 0000000..19f90aa
--- /dev/null
+++ b/ultrazed_7ev_som/1.4/board.xml
@@ -0,0 +1,211 @@
+
+
+
+
+ UltraZed-7EV SOM File Image
+
+
+
+ 1.0
+
+ 1.4
+ Avnet UltraZed-7EV SOM
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ User Differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+
+
+
+ 1GB DDR4 SDRAM memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/ultrazed_7ev_som/1.4/part0_pins.xml b/ultrazed_7ev_som/1.4/part0_pins.xml
new file mode 100644
index 0000000..1dfe7d0
--- /dev/null
+++ b/ultrazed_7ev_som/1.4/part0_pins.xml
@@ -0,0 +1,58 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/ultrazed_7ev_som/1.4/preset.xml b/ultrazed_7ev_som/1.4/preset.xml
new file mode 100644
index 0000000..12e58ac
--- /dev/null
+++ b/ultrazed_7ev_som/1.4/preset.xml
@@ -0,0 +1,241 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+