Update cpuid AVX512 features

[DTL2020]

It looks cpuid.h and cpuid.cpp missed (new ?) AVX512 instructions sets:
AVX512_VNNI
AVX512_BF16

https://github.com/AviSynth/AviSynthPlus/blob/master/avs_core/include/avs/cpuid.h

They have int8/int16 and bf16 convolutions and may be also useful for resampling engines and other convolutions.

https://en.wikichip.org/wiki/x86/avx512_bf16
https://en.wikichip.org/wiki/x86/avx512_vnni

Or may be all after AVX512_VBMI.

[pinterf]

As I see, vnni is very useful, and it's generally available, even on my i7-11700 (Rocket Lake). It's not only for neural networks, but for our common accumulate of 16 bit multiple-and-add results, used at many places. I suppose that when a module is compiled with such compiler flags or function attributes like in llvm/gcc __attribute__((target("avx512vl,avx512f,avx512bw"))) then it converts the add_epi32 and madd lines to these instructions, even is we do not use the new instructions directly.

I think I intentionally did not include features which are irrelevant for Avisynth. Now I see however that the VNNI is just useful, contrary to the "neural network" hint. The bits in CPUFlags started to inflate when avx512 appeared so I had fears.

I think the BF16 is a no-go for us, unlike FP16, which is just another - different mantissa and exponent - representation of the other 16-bit FP format. I included the FP16 in the detected flags only, because VapourSynth had some kind of support for it, and did not know at that time, if we would support it in Avisynth, but finally we did not. Unnecessary.

I'm gonna include the VNNI for sure.

[pinterf]

(Done, commits come later in a bunch with others)

[DTL2020]

Most of neural-network and machine-learning accelerations are about same convolution (FMA) computing as we use in resampling and other image filtering engines. And they are expanded to more faster with current limited SIMD-word width arguments like 16bit and even 8bit sources to have more separated FMA operations per instruction. Also 16bit in AVX512_FP16 is very wide support of direct computing in FP16 (in comparison with very simple FP16C feature of only convert to and from). That mean doubling of compute samples per instruction and doubling of memory storage in samples per caches and same time host memory transfer (double RAM performance in samples per second). I hope we can some day have FP16 samples format for planes and it will make significant performance boost for unlimited in range half-precision float formats and it can replace 16bit integer formats slower in computing (32bit integer immediates and pack/unpack is required). Though as I see while AVX512_FP16 was listed in 2021 first release - it still only available in high priced Xeon chips. While AMD will support it in Zen 6 (next) ? May be to the end of 202x it may read endusers desktops.