Name: Anoushka Tripathi
Email ID: anoushka@bharatsemi.co
LinkedIN Profile: www.linkedin.com/in/anoushkastripathi/
Welcome to this hands-on journey into digital logic design! We're diving into TL-Verilog, an innovative design language pioneered by Redwood EDA. We will use the Makerchip online IDE to design, simulate, and visualize circuits. Let’s start from the basics and quickly ramp up to more advanced concepts.
| Day | Topic | Subparts |
|---|---|---|
| 1 | RISC-V ISA & GNU compiler toolchain | RISC-V Basic keywords |
| RISC-V software toolchain | ||
| Integer number representation | ||
| 2 | ABI & Basic Verification Flow | ABI Basics |
| ABI Labs | ||
| 3 | Digital logic with TL-Verilog in Makerchip IDE | Logic Gates |
| Makerchip Platform | ||
| Combinational Logic | ||
| Sequential Logic | ||
| Pipelined Logic | ||
| Validity | ||
| 4 | Coding a RISC-V CPU subset | Simple RISC-V Microarchitecture |
| Fetch & Decode | ||
| RISC-V Control logic | ||
| 5 | Pipelining and completing your CPU | Understanding CPU Pipelining |
| Solutions to Pipeline hazzards | ||
| Completing RISC-V Design |
Sandbox link: https://makerchip.com/sandbox/0n5fGhE91/0qjh8D7
makerchip.com/sandbox/0n5fGhE91/0r0h8p2
