From 5c260d64c5a09f84c23d39f80f06bdcbe393e1b8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Wed, 4 Apr 2018 14:41:58 +0200 Subject: [PATCH 01/10] PcAtChipsetPkg/PcRtc: set all bits in register D except VRT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Piotr Król --- PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c index c032e16217c3..f3f2bb08697e 100644 --- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c @@ -144,10 +144,10 @@ PcRtcInit ( RtcRead (RTC_ADDRESS_REGISTER_C); // - // Clear RTC register D + // Clear RTC register D - all bits except VRT (Valid RAM and Time) // RegisterD.Data = FixedPcdGet8 (PcdInitialValueRtcRegisterD); - RtcWrite (RTC_ADDRESS_REGISTER_D, RegisterD.Data); + RtcWrite (RTC_ADDRESS_REGISTER_D, RegisterD.Data & 0x80); // // Wait for up to 0.1 seconds for the RTC to be updated From f99fd17127f407c9accf8e5021aed2b043d955ab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Wed, 4 Apr 2018 14:55:17 +0200 Subject: [PATCH 02/10] PcAtChipsetPkg: coorect initial PCD values for RTE registers A,B and D MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Piotr Król --- CorebootPayloadPkg/CorebootPayloadPkg.dec | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.dec b/CorebootPayloadPkg/CorebootPayloadPkg.dec index b33b79c1d6bd..59a372e19c8f 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkg.dec +++ b/CorebootPayloadPkg/CorebootPayloadPkg.dec @@ -49,6 +49,17 @@ # ################################################################################ [PcdsFixedAtBuild, PcdsPatchableInModule] + ## Specifies the initial value for Register_A in RTC. + # @Prompt Initial value for Register_A in RTC. + gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterA|0x26|UINT8|0x00000006 + + ## Specifies the initial value for Register_B in RTC. + # @Prompt Initial value for Register_B in RTC. + gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterB|0x02|UINT8|0x00000002 + + ## Specifies the initial value for Register_D in RTC. + # @Prompt Initial value for Register_D in RTC. + gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD|0x00|UINT8|0x00000000 [PcdsDynamic, PcdsDynamicEx] From edfb661c91394885f7f6c4d4835d226033d651b3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Wed, 4 Apr 2018 15:25:27 +0200 Subject: [PATCH 03/10] PcAtChipsetPkg/PcRtc: remove redundant RTC reg D initialization and clear all its bits except VRT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Piotr Król --- CorebootPayloadPkg/CorebootPayloadPkg.dec | 4 ---- PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c | 2 +- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.dec b/CorebootPayloadPkg/CorebootPayloadPkg.dec index 59a372e19c8f..a3fccbf02372 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkg.dec +++ b/CorebootPayloadPkg/CorebootPayloadPkg.dec @@ -57,9 +57,5 @@ # @Prompt Initial value for Register_B in RTC. gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterB|0x02|UINT8|0x00000002 - ## Specifies the initial value for Register_D in RTC. - # @Prompt Initial value for Register_D in RTC. - gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD|0x00|UINT8|0x00000000 - [PcdsDynamic, PcdsDynamicEx] diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c index f3f2bb08697e..523538ab4f77 100644 --- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c @@ -146,7 +146,7 @@ PcRtcInit ( // // Clear RTC register D - all bits except VRT (Valid RAM and Time) // - RegisterD.Data = FixedPcdGet8 (PcdInitialValueRtcRegisterD); + RegisterD.Data = RtcRead (RTC_ADDRESS_REGISTER_D); RtcWrite (RTC_ADDRESS_REGISTER_D, RegisterD.Data & 0x80); // From b82e247d85caa1ac404e1d820aa8194b8737f0e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Sat, 15 Jul 2017 00:33:01 +0200 Subject: [PATCH 04/10] CorebootPayloadPkg: add PcdTerminalTypeGuidBuffer in DEC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Piotr Król --- CorebootPayloadPkg/CorebootPayloadPkg.dec | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.dec b/CorebootPayloadPkg/CorebootPayloadPkg.dec index a3fccbf02372..309617668c40 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkg.dec +++ b/CorebootPayloadPkg/CorebootPayloadPkg.dec @@ -48,7 +48,7 @@ # declaration, other packages should not. # ################################################################################ -[PcdsFixedAtBuild, PcdsPatchableInModule] +[PcdsFixedAtBuild] ## Specifies the initial value for Register_A in RTC. # @Prompt Initial value for Register_A in RTC. gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterA|0x26|UINT8|0x00000006 @@ -57,5 +57,14 @@ # @Prompt Initial value for Register_B in RTC. gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterB|0x02|UINT8|0x00000002 + # + # Binary representation of the GUID that determines the terminal type. The + # size must be exactly 16 bytes. The default value corresponds to + # EFI_VT_100_GUID. + # + gUefiCorebootPayloadPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x65, 0x60, 0xA6, 0xDF, 0x19, 0xB4, 0xD3, 0x11, 0x9A, 0x2D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}|VOID*|0x00000007 + +[PcdsPatchableInModule] + [PcdsDynamic, PcdsDynamicEx] From d6d95a516779882427f3c77dff0007bca32059f7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Sat, 15 Jul 2017 00:33:34 +0200 Subject: [PATCH 05/10] CorebootPayloadPkg: change SHELL_TYPE to BUILD_SHELL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Piotr Król --- CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc index 2492142b972d..b499dbbdd685 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc @@ -85,7 +85,7 @@ # # Shell options: [BUILD_SHELL, FULL_BIN, MIN_BIN, NONE, UEFI] # - DEFINE SHELL_TYPE = FULL_BIN + DEFINE SHELL_TYPE = BUILD_SHELL [BuildOptions] *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES From 17cd574bcc33d11a2b5a9b286818a53bb505fd7d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Sat, 15 Jul 2017 00:35:48 +0200 Subject: [PATCH 06/10] CorebootPayloadPkg/PlatformBootManagerLib: add the hardcoded device paths for ConIn/ConOut/ErrOut MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Piotr Król --- .../PlatformBootManager.c | 71 +++++++++++++++++++ .../PlatformBootManagerLib.inf | 1 + 2 files changed, 72 insertions(+) diff --git a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c index 7e92441da11f..200127e2440d 100644 --- a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c +++ b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c @@ -16,6 +16,65 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #include "PlatformBootManager.h" #include "PlatformConsole.h" +#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >> 8) } + +#pragma pack (1) +typedef struct { + VENDOR_DEVICE_PATH SerialDxe; + UART_DEVICE_PATH Uart; + VENDOR_DEFINED_DEVICE_PATH TermType; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_SERIAL_CONSOLE; +#pragma pack () + +#define SERIAL_DXE_FILE_GUID { \ + 0xD3987D4B, 0x971A, 0x435F, \ + { 0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41 } \ + } + +STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = { + // + // VENDOR_DEVICE_PATH SerialDxe + // + { + { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) }, + SERIAL_DXE_FILE_GUID + }, + + // + // UART_DEVICE_PATH Uart + // + { + { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) }, + 0, // Reserved + FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate + FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits + FixedPcdGet8 (PcdUartDefaultParity), // Parity + FixedPcdGet8 (PcdUartDefaultStopBits) // StopBits + }, + + // + // VENDOR_DEFINED_DEVICE_PATH TermType + // + { + { + MESSAGING_DEVICE_PATH, MSG_VENDOR_DP, + DP_NODE_LEN (VENDOR_DEFINED_DEVICE_PATH) + } + // + // Guid to be filled in dynamically + // + }, + + // + // EFI_DEVICE_PATH_PROTOCOL End + // + { + END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, + DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL) + } +}; + VOID InstallReadyToLock ( VOID @@ -188,6 +247,18 @@ PlatformBootManagerBeforeConsole ( EfiBootManagerGetBootManagerMenu (&BootOption); EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumber, 0, &Down, NULL); + // + // Add the hardcoded serial console device path to ConIn, ConOut, ErrOut. + // + CopyGuid (&mSerialConsole.TermType.Guid, + PcdGetPtr (PcdTerminalTypeGuidBuffer)); + EfiBootManagerUpdateConsoleVariable (ConIn, + (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL); + EfiBootManagerUpdateConsoleVariable (ConOut, + (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL); + EfiBootManagerUpdateConsoleVariable (ErrOut, + (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL); + // // Install ready to lock. // This needs to be done before option rom dispatched. diff --git a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf index 9e8ae9b36a0e..0c62cbcead35 100644 --- a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf +++ b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf @@ -78,3 +78,4 @@ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits + gUefiCorebootPayloadPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer From b2c2b022c64f4e2a3ec73c5a222f0ec8105312c2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Sat, 5 Aug 2017 02:04:36 +0200 Subject: [PATCH 07/10] CorebootPayloadPkg/PlatformBootManagerLib: get UART PCDs on runtime MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Piotr Król --- .../PlatformBootManagerLib/PlatformBootManager.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c index 200127e2440d..bf3ddab65c4b 100644 --- a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c +++ b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c @@ -46,11 +46,11 @@ STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = { // { { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) }, - 0, // Reserved - FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate - FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits - FixedPcdGet8 (PcdUartDefaultParity), // Parity - FixedPcdGet8 (PcdUartDefaultStopBits) // StopBits + 0, // Reserved + 0, // BaudRate + 0, // DataBits + 0, // Parity + 0 // StopBits }, // @@ -247,6 +247,10 @@ PlatformBootManagerBeforeConsole ( EfiBootManagerGetBootManagerMenu (&BootOption); EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumber, 0, &Down, NULL); + mSerialConsole.Uart.BaudRate = PcdGet64 (PcdUartDefaultBaudRate); + mSerialConsole.Uart.DataBits = PcdGet8 (PcdUartDefaultDataBits); + mSerialConsole.Uart.Parity = PcdGet8 (PcdUartDefaultParity); + mSerialConsole.Uart.StopBits = PcdGet8 (PcdUartDefaultStopBits); // // Add the hardcoded serial console device path to ConIn, ConOut, ErrOut. // From e94b8ca255dadf1c80e14d41448a0fafe34e850a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Wed, 4 Apr 2018 15:49:21 +0200 Subject: [PATCH 08/10] CorebootPayloadPkg/CorebootPayloadPkg: fix typo in gUefiCorebootPayloadPkgTokenSpaceGuid MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Piotr Król --- CorebootPayloadPkg/CorebootPayloadPkg.dec | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.dec b/CorebootPayloadPkg/CorebootPayloadPkg.dec index 309617668c40..cacdc30944e6 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkg.dec +++ b/CorebootPayloadPkg/CorebootPayloadPkg.dec @@ -26,7 +26,7 @@ # ## Defines the token space for the Coreboot Payload Package PCDs. # - gUEfiCorebootPayloadPkgTokenSpaceGuid = {0x1d127ea, 0xf6f1, 0x4ef6, {0x94, 0x15, 0x8a, 0x0, 0x0, 0x93, 0xf8, 0x9d}} + gUefiCorebootPayloadPkgTokenSpaceGuid = {0x1d127ea, 0xf6f1, 0x4ef6, {0x94, 0x15, 0x8a, 0x0, 0x0, 0x93, 0xf8, 0x9d}} # # Gop Temp From 68956c91935e470e48d425902619065a64d2e121 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Kr=C3=B3l?= Date: Wed, 4 Apr 2018 17:22:13 +0200 Subject: [PATCH 09/10] CorebootPayloadPkg: use Duet's PciNoEnumeration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Piotr Król --- CorebootPayloadPkg/CorebootPayloadPkg.fdf | 4 ++-- CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 7 ++----- CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 7 ++----- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf index 7994f0c94928..3ab69d43cdc8 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf +++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf @@ -124,8 +124,8 @@ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf # # PCI Support # -INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf -INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf +INF DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf +INF DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf # # ISA Support diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc index ace1bc0a3726..706096a1fa2f 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc @@ -450,11 +450,8 @@ # # PCI Support # - MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { - - PciHostBridgeLib|CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf - } + DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf + DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf # # SCSI/ATA/IDE/DISK Support diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc index b499dbbdd685..3e3aee3d2e2b 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc @@ -451,11 +451,8 @@ # # PCI Support # - MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { - - PciHostBridgeLib|CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf - } + DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf + DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf # # SCSI/ATA/IDE/DISK Support From 132a07437bc0c62877de044155f8cfc46ba0a5df Mon Sep 17 00:00:00 2001 From: Piotr Kleinschmidt Date: Mon, 1 Jul 2019 14:19:49 +0200 Subject: [PATCH 10/10] CorebootPayloadPkg: disable StatusCodeSerial for release build Signed-off-by: Piotr Kleinschmidt --- CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc index 3e3aee3d2e2b..ee04b96052c2 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc @@ -260,7 +260,11 @@ # ################################################################################ [PcdsFeatureFlag] +!if $(TARGET) == DEBUG gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!endif gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE