diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.dec b/CorebootPayloadPkg/CorebootPayloadPkg.dec
index b33b79c1d6bd..cacdc30944e6 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkg.dec
+++ b/CorebootPayloadPkg/CorebootPayloadPkg.dec
@@ -26,7 +26,7 @@
   #
   ## Defines the token space for the Coreboot Payload Package PCDs.
   #
-  gUEfiCorebootPayloadPkgTokenSpaceGuid  = {0x1d127ea, 0xf6f1, 0x4ef6, {0x94, 0x15, 0x8a, 0x0, 0x0, 0x93, 0xf8, 0x9d}}
+  gUefiCorebootPayloadPkgTokenSpaceGuid  = {0x1d127ea, 0xf6f1, 0x4ef6, {0x94, 0x15, 0x8a, 0x0, 0x0, 0x93, 0xf8, 0x9d}}
 
   #
   # Gop Temp
@@ -48,7 +48,23 @@
 #                            declaration, other packages should not.
 #
 ################################################################################
-[PcdsFixedAtBuild, PcdsPatchableInModule]
+[PcdsFixedAtBuild]
+  ## Specifies the initial value for Register_A in RTC.
+  # @Prompt Initial value for Register_A in RTC.
+  gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterA|0x26|UINT8|0x00000006
+
+  ## Specifies the initial value for Register_B in RTC.
+  # @Prompt Initial value for Register_B in RTC.
+  gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterB|0x02|UINT8|0x00000002
+
+  #
+  # Binary representation of the GUID that determines the terminal type. The
+  # size must be exactly 16 bytes. The default value corresponds to
+  # EFI_VT_100_GUID.
+  #
+  gUefiCorebootPayloadPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x65, 0x60, 0xA6, 0xDF, 0x19, 0xB4, 0xD3, 0x11, 0x9A, 0x2D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}|VOID*|0x00000007
+
+[PcdsPatchableInModule]
 
 [PcdsDynamic, PcdsDynamicEx]
 
diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
index 7994f0c94928..3ab69d43cdc8 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
@@ -124,8 +124,8 @@ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
 #
 # PCI Support
 #
-INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
-INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+INF DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf

+INF DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf

 
 #
 # ISA Support
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index ace1bc0a3726..706096a1fa2f 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -450,11 +450,8 @@
   #
   # PCI Support
   #
-  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
-  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
-    <LibraryClasses>
-      PciHostBridgeLib|CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
-  }
+  DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf

+  DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf

 
   #
   # SCSI/ATA/IDE/DISK Support
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
index 2492142b972d..ee04b96052c2 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -85,7 +85,7 @@
   #
   # Shell options: [BUILD_SHELL, FULL_BIN, MIN_BIN, NONE, UEFI]
   #
-  DEFINE SHELL_TYPE              = FULL_BIN
+  DEFINE SHELL_TYPE              = BUILD_SHELL
 
 [BuildOptions]
   *_*_*_CC_FLAGS                 = -D DISABLE_NEW_DEPRECATED_INTERFACES
@@ -260,7 +260,11 @@
 #
 ################################################################################
 [PcdsFeatureFlag]
+!if $(TARGET) == DEBUG
   gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!endif
   gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
   gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
   gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
@@ -451,11 +455,8 @@
   #
   # PCI Support
   #
-  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
-  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
-    <LibraryClasses>
-      PciHostBridgeLib|CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
-  }
+  DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf

+  DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf

 
   #
   # SCSI/ATA/IDE/DISK Support
diff --git a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
index 7e92441da11f..bf3ddab65c4b 100644
--- a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
+++ b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
@@ -16,6 +16,65 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #include "PlatformBootManager.h"
 #include "PlatformConsole.h"
 
+#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >> 8) }
+
+#pragma pack (1)
+typedef struct {
+  VENDOR_DEVICE_PATH         SerialDxe;
+  UART_DEVICE_PATH           Uart;
+  VENDOR_DEFINED_DEVICE_PATH TermType;
+  EFI_DEVICE_PATH_PROTOCOL   End;
+} PLATFORM_SERIAL_CONSOLE;
+#pragma pack ()
+
+#define SERIAL_DXE_FILE_GUID { \
+          0xD3987D4B, 0x971A, 0x435F, \
+          { 0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41 } \
+          }
+
+STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = {
+  //
+  // VENDOR_DEVICE_PATH SerialDxe
+  //
+  {
+    { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) },
+    SERIAL_DXE_FILE_GUID
+  },
+
+  //
+  // UART_DEVICE_PATH Uart
+  //
+  {
+    { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) },
+    0, // Reserved
+    0, // BaudRate
+    0, // DataBits
+    0, // Parity
+    0  // StopBits
+  },
+
+  //
+  // VENDOR_DEFINED_DEVICE_PATH TermType
+  //
+  {
+    {
+      MESSAGING_DEVICE_PATH, MSG_VENDOR_DP,
+      DP_NODE_LEN (VENDOR_DEFINED_DEVICE_PATH)
+    }
+    //
+    // Guid to be filled in dynamically
+    //
+  },
+
+  //
+  // EFI_DEVICE_PATH_PROTOCOL End
+  //
+  {
+    END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
+    DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)
+  }
+};
+
 VOID
 InstallReadyToLock (
   VOID
@@ -188,6 +247,22 @@ PlatformBootManagerBeforeConsole (
   EfiBootManagerGetBootManagerMenu (&BootOption);
   EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumber, 0, &Down, NULL);
 
+  mSerialConsole.Uart.BaudRate = PcdGet64 (PcdUartDefaultBaudRate);
+  mSerialConsole.Uart.DataBits = PcdGet8 (PcdUartDefaultDataBits);
+  mSerialConsole.Uart.Parity = PcdGet8 (PcdUartDefaultParity);
+  mSerialConsole.Uart.StopBits = PcdGet8 (PcdUartDefaultStopBits);
+  //
+  // Add the hardcoded serial console device path to ConIn, ConOut, ErrOut.
+  //
+  CopyGuid (&mSerialConsole.TermType.Guid,
+    PcdGetPtr (PcdTerminalTypeGuidBuffer));
+  EfiBootManagerUpdateConsoleVariable (ConIn,
+    (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
+  EfiBootManagerUpdateConsoleVariable (ConOut,
+    (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
+  EfiBootManagerUpdateConsoleVariable (ErrOut,
+    (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
+
   //
   // Install ready to lock.
   // This needs to be done before option rom dispatched.
diff --git a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
index 9e8ae9b36a0e..0c62cbcead35 100644
--- a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -78,3 +78,4 @@
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
+  gUefiCorebootPayloadPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer
diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
index c032e16217c3..523538ab4f77 100644
--- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
+++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
@@ -144,10 +144,10 @@ PcRtcInit (
   RtcRead (RTC_ADDRESS_REGISTER_C);
 
   //
-  // Clear RTC register D
+  // Clear RTC register D - all bits except VRT (Valid RAM and Time)
   //
-  RegisterD.Data = FixedPcdGet8 (PcdInitialValueRtcRegisterD);
-  RtcWrite (RTC_ADDRESS_REGISTER_D, RegisterD.Data);
+  RegisterD.Data = RtcRead (RTC_ADDRESS_REGISTER_D);
+  RtcWrite (RTC_ADDRESS_REGISTER_D, RegisterD.Data & 0x80);
 
   //
   // Wait for up to 0.1 seconds for the RTC to be updated