uart_tx.v

module uart_tx #(
    parameter integer DATA_BIT = 8
) (
  // clocks & ticks
  input  wire clk,
  input  wire rst_n,
  input  wire tick,

  // transmit handshake
  input  wire tx_valid,
  output reg  tx_ready,

  // data to send
  input wire [DATA_BIT-1:0] tx_data,

  // serial output Idle: 1 Start:0 Stop:1 
  output reg tx_serial
);
    localparam integer bit_cnt_size = 3;
    /*
    IDLE: 4'd0
    START: 4'd1
    DATA_0-DATA_7: 4'd2-4'd9
    STOP: 4'd10
    */
    localparam IDLE=0, START=1, DATA=2, STOP=3;

    reg [bit_cnt_size-1:0] bit_cnt,next_bit_cnt;
    reg [DATA_BIT-1:0] shift,next_shift;
    reg [3:0] state, next_state;
    reg next_tx_ready, next_tx_serial;

    //FSM
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            state <= IDLE;
            shift <= 0;
            tx_ready <= 1;
            tx_serial <= 1;
            bit_cnt <= 0;
        end else begin
            state <= next_state;
            shift <= next_shift;
            tx_ready <= next_tx_ready;
            tx_serial <= next_tx_serial;
            bit_cnt <= next_bit_cnt;
        end
    end

    //Combinational Logic
    always @(*) begin
        //Default
        next_state = state;
        next_shift = shift;
        next_tx_serial = 1;      
        next_tx_ready = 0;
        next_bit_cnt = bit_cnt;   

        case (state)
            //IDLE
            IDLE: begin
                next_tx_ready = 1;
                if (tx_valid) begin
                    next_shift = tx_data;
                    next_state = START;
                    next_tx_ready = 0;
            end

            end

            //Start
            START: begin
                next_tx_serial = 0;
                if (tick) begin
                    next_state = DATA;
                    next_bit_cnt = 0;
                end
            end

            //data 0 - 7
            DATA: begin
                next_tx_ready = 0;
                next_tx_serial = shift[0];
                if(tick) begin
                    next_shift = shift >> 1;
                    if (bit_cnt == DATA_BIT-1) begin
                        next_state = STOP;
                        next_bit_cnt = 0;
                    end else begin
                        next_state = DATA;
                        next_bit_cnt = bit_cnt + 1;
                    end              
                end
            end

            //Stop
            STOP:  begin
                next_tx_ready = 0;
                next_tx_serial = 1;
                if (tick) 
                    next_state = IDLE;
            end      

        endcase   
    end
    //Log 2 
    // function integer log2;
    // input integer value;
    // integer v;
    // begin
    //     log2 = 0;
    //     v = value - 1;
    //     while (v > 0) begin
    //         log2 = log2 + 1;
    //         v = v >> 1;
    //     end
    // end
    // endfunction

endmodule