uart_rx.v

module uart_rx #(
    parameter integer DATA_BIT = 8,
    parameter integer OVERSAMPLE = 16
) (
    input  wire                 clk,
    input  wire                 rst_n,
    input  wire                 tick,

    input  wire                 rx_ready,
    output reg                  rx_valid,

    output reg  [DATA_BIT-1:0]  rx_data,
    input  wire                 rx_serial
);

    localparam IDLE=0, START=1, DATA=2, STOP=3;

    reg [DATA_BIT-1:0] shift, next_shift;
    reg [2:0]          bit_cnt, next_bit_cnt;   // 0..7
    reg [3:0]          os_cnt,  next_os_cnt;    // 0..15
    reg [1:0]          sync_rx_serial;

    reg [1:0]          state, next_state;
    reg                next_rx_valid;
    reg [DATA_BIT-1:0] next_rx_data;

    wire rx_sync = sync_rx_serial[0];

    // Sequential
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            rx_valid       <= 1'b0;
            rx_data        <= {DATA_BIT{1'b0}};
            shift          <= {DATA_BIT{1'b0}};
            bit_cnt        <= 3'd0;
            os_cnt         <= 4'd0;
            state          <= IDLE;
            sync_rx_serial <= 2'b11; // idle high
        end else begin
            rx_valid <= next_rx_valid;
            rx_data  <= next_rx_data;
            shift    <= next_shift;
            bit_cnt  <= next_bit_cnt;
            os_cnt   <= next_os_cnt;
            state    <= next_state;

            // 2-flop synchronizer
            sync_rx_serial[1] <= rx_serial;
            sync_rx_serial[0] <= sync_rx_serial[1];
        end
    end

    // Combinational
    always @(*) begin
        // defaults: hold
        next_state   = state;
        next_shift   = shift;
        next_bit_cnt = bit_cnt;
        next_os_cnt  = os_cnt;

        // hold data/valid by default
        next_rx_data  = rx_data;
        next_rx_valid = rx_valid;

        if (rx_valid && rx_ready) begin
            next_rx_valid = 1'b0;
        end

        case (state)

            IDLE: begin
                next_os_cnt  = 4'd0;
                next_bit_cnt = 3'd0;

                if (!rx_valid) begin
                    if (!rx_sync) begin
                        next_state  = START;
                        next_os_cnt = 4'd0;
                    end
                end
            end

            START: begin
                if (tick) begin
                    if (os_cnt == 4'd8) begin
                        if (rx_sync) begin
                            next_state  = IDLE;
                            next_os_cnt = 4'd0;
                        end
                    end

                    if (os_cnt == 4'd15) begin
                        next_state   = DATA;
                        next_os_cnt  = 4'd0;
                        next_bit_cnt = 3'd0;
                        next_shift   = {DATA_BIT{1'b0}};
                    end else begin
                        next_os_cnt = os_cnt + 4'd1;
                    end
                end
            end

            DATA: begin
                if (tick) begin
                    if (os_cnt == 4'd8) begin
                        next_shift = shift;
                        next_shift[bit_cnt] = rx_sync; // LSB-first
                    end

                    if (os_cnt == 4'd15) begin
                        next_os_cnt = 4'd0;

                        if (bit_cnt == 3'd7) begin
                            next_bit_cnt = 3'd0;
                            next_state   = STOP;
                        end else begin
                            next_bit_cnt = bit_cnt + 3'd1;
                        end
                    end else begin
                        next_os_cnt = os_cnt + 4'd1;
                    end
                end
            end

            STOP: begin
                if (tick) begin
                    if (os_cnt == 4'd15) begin
                        next_os_cnt = 4'd0;
                        next_state  = IDLE;
                        if (!rx_valid) begin
                            next_rx_data  = shift;
                            next_rx_valid = 1'b1;
                        end
                    end else begin
                        next_os_cnt = os_cnt + 4'd1;
                    end
                end
            end

            default: begin
                next_state = IDLE;
            end

        endcase
    end

endmodule