top_uart.v

module top_uart #(
    parameter integer CLK_FREQ  = 100_000_000,
    parameter integer BAUD_RATE =   115_200,
    parameter integer OVERSAMPLE = 16,
    parameter integer DATA_BIT = 8
) (
    input  wire clk,
    input  wire rst_n,
    
    // Transmitter
    input  wire                   tx_valid,
    input  wire [DATA_BIT-1:0]    tx_data,
    output wire                   tx_ready,

    // Receiver
    input  wire                   rx_ready,
    output wire                   rx_valid,
    output wire [DATA_BIT-1:0]    rx_data,

    // The single serial wire
    output wire                   tx_serial,
    input  wire                   rx_serial
    );

    //Tick Generation
    wire rx_tick,tx_tick;
    //rx tick runs overtsample times faster then tx tick
    baud_gen #(
        .CLK_FREQ  (CLK_FREQ),
        .BAUD_RATE (BAUD_RATE)
    ) baud_rx (
        .clk   (clk),
        .rst_n (rst_n),
        .tick  (rx_tick)
    );
    baud_gen #(
        .CLK_FREQ  (CLK_FREQ),
        .BAUD_RATE (BAUD_RATE),
        .OVERSAMPLE (1)
    ) baud_tx (
        .clk   (clk),
        .rst_n (rst_n),
        .tick  (tx_tick)
    );

    //TX
    uart_tx #(.DATA_BIT(DATA_BIT)) u_tx (
        .clk        (clk),
        .rst_n      (rst_n),
        .tick       (tx_tick),
        .tx_valid   (tx_valid),
        .tx_ready   (tx_ready),
        .tx_data    (tx_data),
        .tx_serial  (tx_serial)
    );

    //RX
    uart_rx #(.DATA_BIT(DATA_BIT), .OVERSAMPLE(OVERSAMPLE)) u_rx (
        .clk        (clk),
        .rst_n      (rst_n),
        .tick       (rx_tick),
        .rx_ready   (rx_ready),
        .rx_valid   (rx_valid),
        .rx_data    (rx_data),
        .rx_serial  (rx_serial)
    );



endmodule